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[/] [apbi2c/] [trunk/] [rtl/] [fifo.v] - Blame information for rev 13

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//////////////////////////////////////////////////////////////////
////
////
////    FIFO BLOCK to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: This block inst functional yet when you try only write half registers and it didnt go correctly FULL and EMPTY
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////              Ronal Dario Celaya
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module fifo
#(
        parameter integer DWIDTH = 32,
        parameter integer AWIDTH = 4
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in,
        output f_full, f_empty,
        output [DWIDTH-1:0] data_out
);
 
 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
        reg [AWIDTH-1:0] wr_ptr;
        reg [AWIDTH-1:0] rd_ptr;
        reg [AWIDTH-1:0] last_position;
 
        reg last_was_write;
 
        always@(posedge clock)
        begin
 
                if (reset)
                //SYNCHRONOUS RESET
                begin
                rd_ptr <= {AWIDTH{1'b0}};
                wr_ptr <= {AWIDTH{1'b0}};
                last_position <= {AWIDTH{1'b0}};
                last_was_write <= 1'b1;
 
                // NONBLOCKING
                end
                else
                begin
 
                        if(wr_en)//WRITE OPERATION
                        begin
                                mem[wr_ptr] <= data_in; //WRITE TO ARRAY
                                wr_ptr <= wr_ptr + 11'd1;
                                last_position <= last_position + 11'd1;
 
                                last_was_write <= 1'b0;
 
                                rd_ptr <= {AWIDTH{1'b0}};
 
                        end
                        else if(rd_en)// READ OPERATION
                        begin
                                wr_ptr <= {AWIDTH{1'b0}};
 
                                if(rd_ptr != {AWIDTH{1'b1}} && last_position == {AWIDTH{1'b0}})
                                begin
                                        rd_ptr <= rd_ptr + 11'd1;
                                end
                                else if(rd_ptr != last_position)
                                begin
                                        rd_ptr <= rd_ptr + 11'd1;
                                end
 
                                if(rd_ptr == last_position - 11'b1 || rd_ptr == {AWIDTH{1'b1}})
                                begin
                                        last_was_write <= 1'b1;
                                        last_position <= {AWIDTH{1'b0}};
                                end
 
                        end
 
                end
 
        end
 
 
        assign f_full = (!last_was_write | last_position != {AWIDTH{1'b0}} )? 1'b1:1'b0;
        assign f_empty = (last_was_write)? 1'b1:1'b0;
        assign data_out = mem[rd_ptr];//WRITE ON OUTPUT
 
endmodule

Line No.	Rev	Author	Line
1	2	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// FIFO BLOCK to I2C Core`
5			`////`
6			`////`
7			`////`
8			`//// This file is part of the APB to I2C project`
9			`////`
10			`//// http://www.opencores.org/cores/apbi2c/`
11			`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// apbi2c_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: This block inst functional yet when you try only write half registers and it didnt go correctly FULL and EMPTY`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29			`//// Ronal Dario Celaya`
30			`////`
31			`/////////////////////////////////////////////////////////////////`
32			`////`
33			`////`
34			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
35			`////`
36			`////`
37			`////`
38			`//// This source file may be used and distributed without`
39			`////`
40			`//// restriction provided that this copyright statement is not`
41			`////`
42			`//// removed from the file and that any derivative work contains`
43			`//// the original copyright notice and the associated disclaimer.`
44			`////`
45			`////`
46			`//// This source file is free software; you can redistribute it`
47			`////`
48			`//// and/or modify it under the terms of the GNU Lesser General`
49			`////`
50			`//// Public License as published by the Free Software Foundation;`
51			`//// either version 2.1 of the License, or (at your option) any`
52			`////`
53			`//// later version.`
54			`////`
55			`////`
56			`////`
57			`//// This source is distributed in the hope that it will be`
58			`////`
59			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
60			`////`
61			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
62			`////`
63			`//// PURPOSE. See the GNU Lesser General Public License for more`
64			`//// details.`
65			`////`
66			`////`
67			`////`
68			`//// You should have received a copy of the GNU Lesser General`
69			`////`
70			`//// Public License along with this source; if not, download it`
71			`////`
72			`//// from http://www.opencores.org/lgpl.shtml`
73			`////`
74			`////`
75			`///////////////////////////////////////////////////////////////////`
76			`module fifo`
77			`#(`
78			`parameter integer DWIDTH = 32,`
79			`parameter integer AWIDTH = 4`
80			`)`
81
82			`(`
83			`input clock, reset, wr_en, rd_en,`
84			`input [DWIDTH-1:0] data_in,`
85			`output f_full, f_empty,`
86			`output [DWIDTH-1:0] data_out`
87			`);`
88
89
90			`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`
91
92			`reg [AWIDTH-1:0] wr_ptr;`
93			`reg [AWIDTH-1:0] rd_ptr;`
94	13	redbear	`reg [AWIDTH-1:0] last_position;`
95	2	redbear
96			`reg last_was_write;`
97
98	13	redbear	`always@(posedge clock)`
99			`begin`
100
101	2	redbear	`if (reset)`
102			`//SYNCHRONOUS RESET`
103			`begin`
104			`rd_ptr <= {AWIDTH{1'b0}};`
105			`wr_ptr <= {AWIDTH{1'b0}};`
106	13	redbear	`last_position <= {AWIDTH{1'b0}};`
107	2	redbear	`last_was_write <= 1'b1;`
108	13	redbear
109	2	redbear	`// NONBLOCKING`
110			`end`
111			`else`
112			`begin`
113
114	13	redbear	`if(wr_en)//WRITE OPERATION`
115	2	redbear	`begin`
116	13	redbear	`mem[wr_ptr] <= data_in; //WRITE TO ARRAY`
117			`wr_ptr <= wr_ptr + 11'd1;`
118			`last_position <= last_position + 11'd1;`
119
120	2	redbear	`last_was_write <= 1'b0;`
121
122	13	redbear	`rd_ptr <= {AWIDTH{1'b0}};`
123	2	redbear
124			`end`
125	13	redbear	`else if(rd_en)// READ OPERATION`
126	2	redbear	`begin`
127	13	redbear	`wr_ptr <= {AWIDTH{1'b0}};`
128	2	redbear
129	13	redbear	`if(rd_ptr != {AWIDTH{1'b1}} && last_position == {AWIDTH{1'b0}})`
130			`begin`
131			`rd_ptr <= rd_ptr + 11'd1;`
132			`end`
133			`else if(rd_ptr != last_position)`
134			`begin`
135			`rd_ptr <= rd_ptr + 11'd1;`
136			`end`
137
138			`if(rd_ptr == last_position - 11'b1 \|\| rd_ptr == {AWIDTH{1'b1}})`
139			`begin`
140			`last_was_write <= 1'b1;`
141			`last_position <= {AWIDTH{1'b0}};`
142			`end`
143	2	redbear
144	13	redbear	`end`
145	2	redbear
146			`end`
147
148	13	redbear	`end`
149	2	redbear
150	13	redbear
151			`assign f_full = (!last_was_write \| last_position != {AWIDTH{1'b0}} )? 1'b1:1'b0;`
152	2	redbear	`assign f_empty = (last_was_write)? 1'b1:1'b0;`
153			`assign data_out = mem[rd_ptr];//WRITE ON OUTPUT`
154
155			`endmodule`

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[/] [apbi2c/] [trunk/] [rtl/] [fifo.v] - Blame information for rev 13