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[/] [apbi2c/] [trunk/] [rtl/] [fifo.v] - Blame information for rev 2

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//////////////////////////////////////////////////////////////////
////
////
////    FIFO BLOCK to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: This block inst functional yet when you try only write half registers and it didnt go correctly FULL and EMPTY
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////              Ronal Dario Celaya
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module fifo
#(
        parameter integer DWIDTH = 32,
        parameter integer AWIDTH = 4
)
 
(
        input clock, reset, wr_en, rd_en,
        input [DWIDTH-1:0] data_in,
        output f_full, f_empty,
        output [DWIDTH-1:0] data_out
);
 
 
        reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];
 
        reg [AWIDTH-1:0] wr_ptr;
        reg [AWIDTH-1:0] rd_ptr;
 
        reg last_was_write;
 
        always @ (posedge clock)
                if (reset)
                //SYNCHRONOUS RESET
                begin
                rd_ptr <= {AWIDTH{1'b0}};
                wr_ptr <= {AWIDTH{1'b0}};
                last_was_write <= 1'b1;
                // NONBLOCKING
                end
                else
                begin
                if (wr_en )//WRITE OPERATION
                begin
                        mem[wr_ptr] <= data_in; //WRITE TO ARRAY
                        wr_ptr <= wr_ptr + 11'd1;
 
                        if(wr_ptr == {AWIDTH{1'b1}})
                        begin
                                last_was_write <= 1'b0;
                        end
 
                        rd_ptr <= {AWIDTH{1'b0}};//POINTER GOES TO INITIAL ADDRESSS
 
                end
                else if (rd_en)// READ OPERATION
                begin
 
                        rd_ptr <= rd_ptr + 11'd1;
 
                        if(rd_ptr == {AWIDTH{1'b1}})//SIGNAL USED TO NOTICE I2C FIFO IS EMPTY
                        begin
                                last_was_write <= 1'b1;
                                wr_ptr <= {AWIDTH{1'b0}};//POINTER GOES TO INITIAL ADDRESSS
                        end
                        else if(wr_ptr != {AWIDTH{1'b0}} && wr_ptr == rd_ptr )//HALF FULL EMPTY CONDITION
                        begin
                                last_was_write <= 1'b1;
                                wr_ptr <= {AWIDTH{1'b0}};//POINTER GOES TO INITIAL ADDRESSS
                        end
 
 
 
                end
                else if(wr_ptr != rd_ptr && !wr_en)//THIS INST TESTED YET
                begin
                        last_was_write <= 1'b0;
                end
 
                end
 
 
        assign f_full = (!last_was_write)? 1'b1:1'b0;
        assign f_empty = (last_was_write)? 1'b1:1'b0;
        assign data_out = mem[rd_ptr];//WRITE ON OUTPUT
 
endmodule

Line No.	Rev	Author	Line
1	2	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// FIFO BLOCK to I2C Core`
5			`////`
6			`////`
7			`////`
8			`//// This file is part of the APB to I2C project`
9			`////`
10			`//// http://www.opencores.org/cores/apbi2c/`
11			`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// apbi2c_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: This block inst functional yet when you try only write half registers and it didnt go correctly FULL and EMPTY`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29			`//// Ronal Dario Celaya`
30			`////`
31			`/////////////////////////////////////////////////////////////////`
32			`////`
33			`////`
34			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
35			`////`
36			`////`
37			`////`
38			`//// This source file may be used and distributed without`
39			`////`
40			`//// restriction provided that this copyright statement is not`
41			`////`
42			`//// removed from the file and that any derivative work contains`
43			`//// the original copyright notice and the associated disclaimer.`
44			`////`
45			`////`
46			`//// This source file is free software; you can redistribute it`
47			`////`
48			`//// and/or modify it under the terms of the GNU Lesser General`
49			`////`
50			`//// Public License as published by the Free Software Foundation;`
51			`//// either version 2.1 of the License, or (at your option) any`
52			`////`
53			`//// later version.`
54			`////`
55			`////`
56			`////`
57			`//// This source is distributed in the hope that it will be`
58			`////`
59			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
60			`////`
61			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
62			`////`
63			`//// PURPOSE. See the GNU Lesser General Public License for more`
64			`//// details.`
65			`////`
66			`////`
67			`////`
68			`//// You should have received a copy of the GNU Lesser General`
69			`////`
70			`//// Public License along with this source; if not, download it`
71			`////`
72			`//// from http://www.opencores.org/lgpl.shtml`
73			`////`
74			`////`
75			`///////////////////////////////////////////////////////////////////`
76			`module fifo`
77			`#(`
78			`parameter integer DWIDTH = 32,`
79			`parameter integer AWIDTH = 4`
80			`)`
81
82			`(`
83			`input clock, reset, wr_en, rd_en,`
84			`input [DWIDTH-1:0] data_in,`
85			`output f_full, f_empty,`
86			`output [DWIDTH-1:0] data_out`
87			`);`
88
89
90			`reg [DWIDTH-1:0] mem [0:2**AWIDTH-1];`
91
92			`reg [AWIDTH-1:0] wr_ptr;`
93			`reg [AWIDTH-1:0] rd_ptr;`
94
95			`reg last_was_write;`
96
97			`always @ (posedge clock)`
98			`if (reset)`
99			`//SYNCHRONOUS RESET`
100			`begin`
101			`rd_ptr <= {AWIDTH{1'b0}};`
102			`wr_ptr <= {AWIDTH{1'b0}};`
103			`last_was_write <= 1'b1;`
104			`// NONBLOCKING`
105			`end`
106			`else`
107			`begin`
108			`if (wr_en )//WRITE OPERATION`
109			`begin`
110			`mem[wr_ptr] <= data_in; //WRITE TO ARRAY`
111			`wr_ptr <= wr_ptr + 11'd1;`
112
113			`if(wr_ptr == {AWIDTH{1'b1}})`
114			`begin`
115			`last_was_write <= 1'b0;`
116			`end`
117
118			`rd_ptr <= {AWIDTH{1'b0}};//POINTER GOES TO INITIAL ADDRESSS`
119
120			`end`
121			`else if (rd_en)// READ OPERATION`
122			`begin`
123
124			`rd_ptr <= rd_ptr + 11'd1;`
125
126			`if(rd_ptr == {AWIDTH{1'b1}})//SIGNAL USED TO NOTICE I2C FIFO IS EMPTY`
127			`begin`
128			`last_was_write <= 1'b1;`
129			`wr_ptr <= {AWIDTH{1'b0}};//POINTER GOES TO INITIAL ADDRESSS`
130			`end`
131			`else if(wr_ptr != {AWIDTH{1'b0}} && wr_ptr == rd_ptr )//HALF FULL EMPTY CONDITION`
132			`begin`
133			`last_was_write <= 1'b1;`
134			`wr_ptr <= {AWIDTH{1'b0}};//POINTER GOES TO INITIAL ADDRESSS`
135			`end`
136
137
138
139			`end`
140			`else if(wr_ptr != rd_ptr && !wr_en)//THIS INST TESTED YET`
141			`begin`
142			`last_was_write <= 1'b0;`
143			`end`
144
145			`end`
146
147
148			`assign f_full = (!last_was_write)? 1'b1:1'b0;`
149			`assign f_empty = (last_was_write)? 1'b1:1'b0;`
150			`assign data_out = mem[rd_ptr];//WRITE ON OUTPUT`
151
152			`endmodule`

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[/] [apbi2c/] [trunk/] [rtl/] [fifo.v] - Blame information for rev 2