URL https://opencores.org/ocsvn/apbi2c/apbi2c/trunk

Subversion Repositories apbi2c

[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Blame information for rev 19

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////
////
////
////    TOP I2C BLOCK to I2C Core
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// apbi2c_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////              Ronal Dario Celaya ,rcelaya.dario@gmail.com
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
 
 
`timescale 1ns/1ps //timescale 
 
module module_i2c#(
                        //THIS IS USED ONLY LIKE PARAMETER TO BEM CONFIGURABLE
                        parameter integer DWIDTH = 32,
                        parameter integer AWIDTH = 14
                )
                (
                //I2C INTERFACE WITH ANOTHER BLOCKS
                 input PCLK,
                 input PRESETn,
 
                //INTERFACE WITH FIFO TRANSMISSION
                 input fifo_tx_f_full,
                 input fifo_tx_f_empty,
                 input [DWIDTH-1:0] fifo_tx_data_out,
 
                //INTERFACE WITH FIFO RECEIVER
                 input fifo_rx_f_full,
                 input fifo_rx_f_empty,
                 output reg fifo_rx_wr_en,
                 output reg [DWIDTH-1:0] fifo_rx_data_in,
 
                //INTERFACE WITH REGISTER CONFIGURATION
                 input [AWIDTH-1:0] DATA_CONFIG_REG,
 
                //INTERFACE TO APB AND READ FOR FIFO TX
                 output reg fifo_tx_rd_en,
                 output TX_EMPTY,
                 output RX_EMPTY,
                 output ERROR,
 
                //I2C BI DIRETIONAL PORTS
                inout SDA,
                inout SCL
 
 
                 );
 
//THIS IS USED TO GENERATE INTERRUPTIONS
assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;
assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;
 
        //THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM        
        reg [1:0] count_tx;
        //CONTROL CLOCK AND COUNTER
        reg [11:0] count_send_data;
        reg BR_CLK_O;
        reg SDA_OUT;
 
        //RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
        reg RESPONSE;
 
// TX PARAMETERS USED TO STATE MACHINE
 
localparam [5:0] RX_TX_IDLE = 6'd0, //IDLE
 
           RX_TX_START = 6'd1,//START BIT
 
           RX_TX_CONTROLIN_1 = 6'd2, //START BYTE
           RX_TX_CONTROLIN_2 = 6'd3,
           RX_TX_CONTROLIN_3 = 6'd4,
           RX_TX_CONTROLIN_4 = 6'd5,
           RX_TX_CONTROLIN_5 = 6'd6,
           RX_TX_CONTROLIN_6 = 6'd7,
           RX_TX_CONTROLIN_7 = 6'd8,
           RX_TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE
 
           RX_TX_RESPONSE_CIN =6'd10, //RESPONSE
 
           RX_TX_ADRESS_1 = 6'd11,//START BYTE
           RX_TX_ADRESS_2 = 6'd12,
           RX_TX_ADRESS_3 = 6'd13,
           RX_TX_ADRESS_4 = 6'd14,
           RX_TX_ADRESS_5 = 6'd15,
           RX_TX_ADRESS_6 = 6'd16,
           RX_TX_ADRESS_7 = 6'd17,
           RX_TX_ADRESS_8 = 6'd18,//END FIRST BYTE
 
           RX_TX_RESPONSE_ADRESS =6'd19, //RESPONSE
 
           RX_TX_DATA0_1 = 6'd20,//START BYTE
           RX_TX_DATA0_2 = 6'd21,
           RX_TX_DATA0_3 = 6'd22,
           RX_TX_DATA0_4 = 6'd23,
           RX_TX_DATA0_5 = 6'd24,
           RX_TX_DATA0_6 = 6'd25,
           RX_TX_DATA0_7 = 6'd26,
           RX_TX_DATA0_8 = 6'd27,//END FIRST BYTE
 
           RX_TX_RESPONSE_DATA0_1 = 6'd28,  //RESPONSE
 
           RX_TX_DATA1_1 = 6'd29,//START BYTE
           RX_TX_DATA1_2 = 6'd30,
           RX_TX_DATA1_3 = 6'd31,
           RX_TX_DATA1_4 = 6'd32,
           RX_TX_DATA1_5 = 6'd33,
           RX_TX_DATA1_6 = 6'd34,
           RX_TX_DATA1_7 = 6'd35,
           RX_TX_DATA1_8 = 6'd36,//END FIRST BYTE
 
           RX_TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE
 
           RX_TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
           RX_TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
           RX_TX_STOP = 6'd40;//USED TO SEND STOP BIT
 
        //STATE CONTROL 
        reg [5:0] state_tx_rx;
        reg [5:0] next_state_tx_rx;
 
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'b0;
assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:1'b0;
 
//STANDARD ERROR
assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
 
//COMBINATIONAL BLOCK TO TX
always@(*)
begin
 
        //THE FUN START HERE :-)
        //COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
        next_state_tx_rx = state_tx_rx;
 
        case(state_tx_rx)//state_tx_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING 
        RX_TX_IDLE:
        begin
                //OBEYING SPEC
                if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
                begin
                        next_state_tx_rx = RX_TX_IDLE;
                end
                else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
                begin
                        next_state_tx_rx = RX_TX_IDLE;
                end
                else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
                begin
                        next_state_tx_rx = RX_TX_START;
                end
 
 
        end
        RX_TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_START;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_1;
                end
 
        end
        RX_TX_CONTROLIN_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_1;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_2;
                end
 
        end
        RX_TX_CONTROLIN_2:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_2;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_3;
                end
 
        end
        RX_TX_CONTROLIN_3:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_3;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_4;
                end
        end
        RX_TX_CONTROLIN_4:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_4;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_5;
                end
        end
        RX_TX_CONTROLIN_5:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_5;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_6;
                end
        end
        RX_TX_CONTROLIN_6:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_6;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_7;
                end
        end
        RX_TX_CONTROLIN_7:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_7;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_8;
                end
        end
        RX_TX_CONTROLIN_8:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_CONTROLIN_8;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_CIN;
                end
        end
        RX_TX_RESPONSE_CIN:
        begin
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_CIN;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx_rx = RX_TX_DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_tx_rx = RX_TX_NACK;
                end
 
        end
 
        //NOW SENDING ADDRESS
        RX_TX_ADRESS_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_1;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_2;
                end
        end
        RX_TX_ADRESS_2:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_2;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_3;
                end
        end
        RX_TX_ADRESS_3:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_3;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_4;
                end
        end
        RX_TX_ADRESS_4:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_4;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_5;
                end
        end
        RX_TX_ADRESS_5:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_5;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_6;
                end
        end
        RX_TX_ADRESS_6:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_6;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_7;
                end
        end
        RX_TX_ADRESS_7:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_7;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_ADRESS_8;
                end
        end
        RX_TX_ADRESS_8:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_ADRESS_8;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
                end
        end
        RX_TX_RESPONSE_ADRESS:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_ADRESS;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx_rx = RX_TX_DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
                begin
                        next_state_tx_rx = RX_TX_NACK;
                end
        end
 
        //data in
        RX_TX_DATA0_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_1;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_2;
                end
        end
        RX_TX_DATA0_2:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_2;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_3;
                end
        end
        RX_TX_DATA0_3:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_3;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_4;
                end
        end
        RX_TX_DATA0_4:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_4;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_5;
                end
        end
        RX_TX_DATA0_5:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_5;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_6;
                end
        end
        RX_TX_DATA0_6:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_6;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_7;
                end
        end
        RX_TX_DATA0_7:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_7;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA0_8;
                end
        end
        RX_TX_DATA0_8:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA0_8;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
                end
        end
        RX_TX_RESPONSE_DATA0_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_DATA0_1;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx_rx = RX_TX_DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_tx_rx = RX_TX_NACK;
                end
        end
 
        //second byte
        RX_TX_DATA1_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_1;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_2;
                end
        end
        RX_TX_DATA1_2:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_2;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_3;
                end
        end
        RX_TX_DATA1_3:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_3;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_4;
                end
        end
        RX_TX_DATA1_4:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_4;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_5;
                end
        end
        RX_TX_DATA1_5:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_5;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_6;
                end
        end
        RX_TX_DATA1_6:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_6;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_7;
                end
        end
        RX_TX_DATA1_7:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_7;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_DATA1_8;
                end
        end
        RX_TX_DATA1_8:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DATA1_8;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
                end
        end
        RX_TX_RESPONSE_DATA1_1:
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_RESPONSE_DATA1_1;
                end
                else if(RESPONSE == 1'b0)//ACK
                begin
                        next_state_tx_rx = RX_TX_DELAY_BYTES;
                end
                else if(RESPONSE == 1'b1)//NACK
                begin
                        next_state_tx_rx = RX_TX_NACK;
                end
        end
        RX_TX_DELAY_BYTES://THIS FORM WORKS 
        begin
 
 
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_DELAY_BYTES;
                end
                else
                begin
 
                        if(count_tx == 2'd0)
                        begin
                                next_state_tx_rx = RX_TX_ADRESS_1;
                        end
                        else if(count_tx == 2'd1)
                        begin
                                next_state_tx_rx = RX_TX_DATA0_1;
                        end
                        else if(count_tx == 2'd2)
                        begin
                                next_state_tx_rx = RX_TX_DATA1_1;
                        end
                        else if(count_tx == 2'd3)
                        begin
                                next_state_tx_rx = RX_TX_STOP;
                        end
 
                end
 
        end
        RX_TX_NACK://NOT TESTED YET !!!!
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
                begin
                        next_state_tx_rx = RX_TX_NACK;
                end
                else
                begin
                        if(count_tx == 2'd0)
                        begin
                                next_state_tx_rx = RX_TX_CONTROLIN_1;
                        end
                        else if(count_tx == 2'd1)
                        begin
                                next_state_tx_rx = RX_TX_ADRESS_1;
                        end
                        else if(count_tx == 2'd2)
                        begin
                                next_state_tx_rx = RX_TX_DATA0_1;
                        end
                        else if(count_tx == 2'd3)
                        begin
                                next_state_tx_rx = RX_TX_DATA1_1;
                        end
                end
        end
        RX_TX_STOP://THIS WORK
        begin
                if(count_send_data != DATA_CONFIG_REG[13:2])
                begin
                        next_state_tx_rx = RX_TX_STOP;
                end
                else
                begin
                        next_state_tx_rx = RX_TX_IDLE;
                end
        end
        default:
        begin
                next_state_tx_rx = RX_TX_IDLE;
        end
        endcase
 
 
end
 
 
 
//SEQUENTIAL TX
always@(posedge PCLK)
begin
 
        //RESET SYNC
        if(!PRESETn)
        begin
                //SIGNALS MUST BE RESETED
                count_send_data <= 12'd0;
                state_tx_rx <= RX_TX_IDLE;
                SDA_OUT<= 1'b1;
                fifo_tx_rd_en <= 1'b0;
                count_tx <= 2'd0;
                BR_CLK_O <= 1'b1;
                RESPONSE<= 1'b0;
        end
        else
        begin
 
                // SEQUENTIAL FUN START
                state_tx_rx <= next_state_tx_rx;
 
                case(state_tx_rx)
                RX_TX_IDLE:
                begin
 
                        fifo_tx_rd_en <= 1'b0;
 
 
                        if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<= 1'b1;
                                BR_CLK_O <= 1'b1;
                        end
                        else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=1'b0;
                        end
                        else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<= 1'b1;
                                BR_CLK_O <= 1'b1;
                        end
 
                end
                RX_TX_START:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                BR_CLK_O <= 1'b0;
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
                        if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
                        begin
                                SDA_OUT<=fifo_tx_data_out[0:0];
                                count_tx <= 2'd0;
                        end
 
                end
                RX_TX_CONTROLIN_1:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
 
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[0:0];
 
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[1:1];
                        end
 
 
                end
 
                RX_TX_CONTROLIN_2:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[1:1];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[2:2];
                        end
 
                end
 
                RX_TX_CONTROLIN_3:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[2:2];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[3:3];
                        end
 
 
 
                end
                RX_TX_CONTROLIN_4:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[3:3];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[4:4];
                        end
 
                end
 
                RX_TX_CONTROLIN_5:
                begin
 
 
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[4:4];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[5:5];
                        end
 
                end
 
 
                RX_TX_CONTROLIN_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[5:5];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[6:6];
                        end
 
 
                end
 
                RX_TX_CONTROLIN_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[6:6];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[7:7];
                        end
 
 
                end
                RX_TX_CONTROLIN_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[7:7];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<= 1'b0;
                        end
 
 
                end
                RX_TX_RESPONSE_CIN:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
 
                end
                RX_TX_ADRESS_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[8:8];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[9:9];
                        end
 
                end
                RX_TX_ADRESS_2:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[9:9];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[10:10];
                        end
 
                end
                RX_TX_ADRESS_3:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[10:10];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[11:11];
                        end
 
                end
                RX_TX_ADRESS_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[11:11];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[12:12];
                        end
                end
                RX_TX_ADRESS_5:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[12:12];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[13:13];
                        end
 
 
                end
                RX_TX_ADRESS_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[13:13];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[14:14];
                        end
 
                end
                RX_TX_ADRESS_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[14:14];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[15:15];
                        end
 
 
                end
                RX_TX_ADRESS_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[15:15];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=1'b0;
                        end
 
                end
                RX_TX_RESPONSE_ADRESS:
                begin
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
                end
                RX_TX_DATA0_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[16:16];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[17:17];
                        end
 
 
                end
                RX_TX_DATA0_2:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[17:17];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[18:18];
                        end
 
 
                end
                RX_TX_DATA0_3:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[18:18];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[19:19];
                        end
 
                end
                RX_TX_DATA0_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[19:19];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[20:20];
                        end
 
                end
                RX_TX_DATA0_5:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[20:20];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[21:21];
                        end
 
                end
                RX_TX_DATA0_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[21:21];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[22:22];
                        end
 
                end
                RX_TX_DATA0_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[22:22];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[23:23];
                        end
 
                end
                RX_TX_DATA0_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[23:23];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=1'b0;
                        end
 
                end
                RX_TX_RESPONSE_DATA0_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
 
                end
                RX_TX_DATA1_1:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[24:24];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[25:25];
 
                        end
 
 
                end
                RX_TX_DATA1_2:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[25:25];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[26:26];
                        end
 
                end
                RX_TX_DATA1_3:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[26:26];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[27:27];
                        end
 
                end
                RX_TX_DATA1_4:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[27:27];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[28:28];
                        end
 
                end
                RX_TX_DATA1_5:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[28:28];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[29:29];
                        end
 
                end
                RX_TX_DATA1_6:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[29:29];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[30:30];
                        end
 
                end
                RX_TX_DATA1_7:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[30:30];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=fifo_tx_data_out[31:31];
                        end
 
 
                end
                RX_TX_DATA1_8:
                begin
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
                                SDA_OUT<=fifo_tx_data_out[31:31];
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                SDA_OUT<=1'b0;
                        end
 
                end
                RX_TX_RESPONSE_DATA1_1:
                begin
                        //fifo_tx_rd_en <= 1'b1;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
                                RESPONSE<= SDA;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                                fifo_tx_rd_en <= 1'b1;
                        end
 
                end
                RX_TX_DELAY_BYTES:
                begin
 
                        fifo_tx_rd_en <= 1'b0;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
 
                                count_send_data <= count_send_data + 12'd1;
                                BR_CLK_O <= 1'b0;
                                SDA_OUT<=1'b0;
                        end
                        else
                        begin
 
 
                                if(count_tx == 2'd0)
                                begin
                                        count_tx <= count_tx + 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[8:8];
                                end
                                else if(count_tx == 2'd1)
                                begin
                                        count_tx <= count_tx + 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[16:16];
                                end
                                else if(count_tx == 2'd2)
                                begin
                                        count_tx <= count_tx + 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[24:24];
                                end
                                else if(count_tx == 2'd3)
                                begin
                                        count_tx <= 2'd0;
                                end
 
                                count_send_data <= 12'd0;
 
                        end
 
                end
                //THIS BLOCK MUST BE CHECKED WITH CARE
                RX_TX_NACK:// MORE A RESTART 
                begin
                        fifo_tx_rd_en <= 1'b0;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
                                begin
                                        SDA_OUT<=1'b0;
                                end
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
                                begin
                                        SDA_OUT<=1'b1;
                                end
                                else if(count_send_data  == DATA_CONFIG_REG[13:2]*2'd2)
                                begin
                                        SDA_OUT<=1'b0;
                                end
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
                                begin
                                        BR_CLK_O <= 1'b0;
                                end
                                else if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
                                begin
                                        BR_CLK_O <= 1'b1;
                                end
 
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
 
                                if(count_tx == 2'd0)
                                begin
                                        count_tx <= 2'd0;
                                        SDA_OUT<=fifo_tx_data_out[0:0];
                                end
                                else if(count_tx == 2'd1)
                                begin
                                        count_tx <= 2'd1;
                                        SDA_OUT<=fifo_tx_data_out[8:8];
                                end
                                else if(count_tx == 2'd2)
                                begin
                                        count_tx <= 2'd2;
                                        SDA_OUT<=fifo_tx_data_out[16:16];
                                end
                                else if(count_tx == 2'd3)
                                begin
                                        count_tx <= 2'd3;
                                        SDA_OUT<=fifo_tx_data_out[24:24];
                                end
 
 
                        end
                end
                RX_TX_STOP:
                begin
 
                        BR_CLK_O <= 1'b1;
 
                        if(count_send_data < DATA_CONFIG_REG[13:2])
                        begin
                                count_send_data <= count_send_data + 12'd1;
 
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
                                begin
                                        SDA_OUT<=1'b0;
                                end
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
                                begin
                                        SDA_OUT<=1'b1;
                                end
                        end
                        else
                        begin
                                count_send_data <= 12'd0;
                        end
                end
                default:
                begin
                        fifo_tx_rd_en <= 1'b0;
                        count_send_data <= 12'd4095;
                end
                endcase
 
        end
 
 
end
 
endmodule
 

Line No.	Rev	Author	Line
1	2	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// TOP I2C BLOCK to I2C Core`
5			`////`
6			`////`
7			`////`
8			`//// This file is part of the APB to I2C project`
9			`////`
10			`//// http://www.opencores.org/cores/apbi2c/`
11			`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// apbi2c_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: Things are right here but always all block can suffer changes`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29	4	redbear	`//// Ronal Dario Celaya ,rcelaya.dario@gmail.com`
30	2	redbear	`////`
31			`/////////////////////////////////////////////////////////////////`
32			`////`
33			`////`
34			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
35			`////`
36			`////`
37			`////`
38			`//// This source file may be used and distributed without`
39			`////`
40			`//// restriction provided that this copyright statement is not`
41			`////`
42			`//// removed from the file and that any derivative work contains`
43			`//// the original copyright notice and the associated disclaimer.`
44			`////`
45			`////`
46			`//// This source file is free software; you can redistribute it`
47			`////`
48			`//// and/or modify it under the terms of the GNU Lesser General`
49			`////`
50			`//// Public License as published by the Free Software Foundation;`
51			`//// either version 2.1 of the License, or (at your option) any`
52			`////`
53			`//// later version.`
54			`////`
55			`////`
56			`////`
57			`//// This source is distributed in the hope that it will be`
58			`////`
59			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
60			`////`
61			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
62			`////`
63			`//// PURPOSE. See the GNU Lesser General Public License for more`
64			`//// details.`
65			`////`
66			`////`
67			`////`
68			`//// You should have received a copy of the GNU Lesser General`
69			`////`
70			`//// Public License along with this source; if not, download it`
71			`////`
72			`//// from http://www.opencores.org/lgpl.shtml`
73			`////`
74			`////`
75			`///////////////////////////////////////////////////////////////////`
76
77
78			`timescale 1ns/1ps //timescale
79
80			`module module_i2c#(`
81			`//THIS IS USED ONLY LIKE PARAMETER TO BEM CONFIGURABLE`
82			`parameter integer DWIDTH = 32,`
83			`parameter integer AWIDTH = 14`
84			`)`
85			`(`
86			`//I2C INTERFACE WITH ANOTHER BLOCKS`
87			`input PCLK,`
88			`input PRESETn,`
89
90			`//INTERFACE WITH FIFO TRANSMISSION`
91			`input fifo_tx_f_full,`
92			`input fifo_tx_f_empty,`
93			`input [DWIDTH-1:0] fifo_tx_data_out,`
94
95			`//INTERFACE WITH FIFO RECEIVER`
96			`input fifo_rx_f_full,`
97			`input fifo_rx_f_empty,`
98	6	redbear	`output reg fifo_rx_wr_en,`
99			`output reg [DWIDTH-1:0] fifo_rx_data_in,`
100	2	redbear
101			`//INTERFACE WITH REGISTER CONFIGURATION`
102			`input [AWIDTH-1:0] DATA_CONFIG_REG,`
103
104			`//INTERFACE TO APB AND READ FOR FIFO TX`
105			`output reg fifo_tx_rd_en,`
106			`output TX_EMPTY,`
107			`output RX_EMPTY,`
108			`output ERROR,`
109
110			`//I2C BI DIRETIONAL PORTS`
111			`inout SDA,`
112			`inout SCL`
113
114
115			`);`
116
117			`//THIS IS USED TO GENERATE INTERRUPTIONS`
118			`assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;`
119			`assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;`
120
121			`//THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM`
122	6	redbear	`reg [1:0] count_tx;`
123	2	redbear	`//CONTROL CLOCK AND COUNTER`
124			`reg [11:0] count_send_data;`
125			`reg BR_CLK_O;`
126			`reg SDA_OUT;`
127
128			`//RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK`
129			`reg RESPONSE;`
130
131			`// TX PARAMETERS USED TO STATE MACHINE`
132
133	19	redbear	`localparam [5:0] RX_TX_IDLE = 6'd0, //IDLE`
134	2	redbear
135	19	redbear	`RX_TX_START = 6'd1,//START BIT`
136	2	redbear
137	19	redbear	`RX_TX_CONTROLIN_1 = 6'd2, //START BYTE`
138			`RX_TX_CONTROLIN_2 = 6'd3,`
139			`RX_TX_CONTROLIN_3 = 6'd4,`
140			`RX_TX_CONTROLIN_4 = 6'd5,`
141			`RX_TX_CONTROLIN_5 = 6'd6,`
142			`RX_TX_CONTROLIN_6 = 6'd7,`
143			`RX_TX_CONTROLIN_7 = 6'd8,`
144			`RX_TX_CONTROLIN_8 = 6'd9, //END FIRST BYTE`
145	2	redbear
146	19	redbear	`RX_TX_RESPONSE_CIN =6'd10, //RESPONSE`
147	2	redbear
148	19	redbear	`RX_TX_ADRESS_1 = 6'd11,//START BYTE`
149			`RX_TX_ADRESS_2 = 6'd12,`
150			`RX_TX_ADRESS_3 = 6'd13,`
151			`RX_TX_ADRESS_4 = 6'd14,`
152			`RX_TX_ADRESS_5 = 6'd15,`
153			`RX_TX_ADRESS_6 = 6'd16,`
154			`RX_TX_ADRESS_7 = 6'd17,`
155			`RX_TX_ADRESS_8 = 6'd18,//END FIRST BYTE`
156	2	redbear
157	19	redbear	`RX_TX_RESPONSE_ADRESS =6'd19, //RESPONSE`
158	2	redbear
159	19	redbear	`RX_TX_DATA0_1 = 6'd20,//START BYTE`
160			`RX_TX_DATA0_2 = 6'd21,`
161			`RX_TX_DATA0_3 = 6'd22,`
162			`RX_TX_DATA0_4 = 6'd23,`
163			`RX_TX_DATA0_5 = 6'd24,`
164			`RX_TX_DATA0_6 = 6'd25,`
165			`RX_TX_DATA0_7 = 6'd26,`
166			`RX_TX_DATA0_8 = 6'd27,//END FIRST BYTE`
167	2	redbear
168	19	redbear	`RX_TX_RESPONSE_DATA0_1 = 6'd28, //RESPONSE`
169	2	redbear
170	19	redbear	`RX_TX_DATA1_1 = 6'd29,//START BYTE`
171			`RX_TX_DATA1_2 = 6'd30,`
172			`RX_TX_DATA1_3 = 6'd31,`
173			`RX_TX_DATA1_4 = 6'd32,`
174			`RX_TX_DATA1_5 = 6'd33,`
175			`RX_TX_DATA1_6 = 6'd34,`
176			`RX_TX_DATA1_7 = 6'd35,`
177			`RX_TX_DATA1_8 = 6'd36,//END FIRST BYTE`
178	2	redbear
179	19	redbear	`RX_TX_RESPONSE_DATA1_1 = 6'd37,//RESPONSE`
180	2	redbear
181	19	redbear	`RX_TX_DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN`
182			`RX_TX_NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES`
183			`RX_TX_STOP = 6'd40;//USED TO SEND STOP BIT`
184	2	redbear
185			`//STATE CONTROL`
186	19	redbear	`reg [5:0] state_tx_rx;`
187			`reg [5:0] next_state_tx_rx;`
188	2	redbear
189			`//ASSIGN REGISTERS TO BIDIRETIONAL PORTS`
190	11	redbear	`assign SDA = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?SDA_OUT:1'b0;`
191			`assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:1'b0;`
192	2	redbear
193	4	redbear	`//STANDARD ERROR`
194			`assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;`
195	2	redbear
196			`//COMBINATIONAL BLOCK TO TX`
197			`always@(*)`
198			`begin`
199
200			`//THE FUN START HERE :-)`
201			`//COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE`
202	19	redbear	`next_state_tx_rx = state_tx_rx;`
203	2	redbear
204	19	redbear	`case(state_tx_rx)//state_tx_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING`
205			`RX_TX_IDLE:`
206	2	redbear	`begin`
207			`//OBEYING SPEC`
208	18	redbear	`if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
209	2	redbear	`begin`
210	19	redbear	`next_state_tx_rx = RX_TX_IDLE;`
211	2	redbear	`end`
212	18	redbear	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)`
213	2	redbear	`begin`
214	19	redbear	`next_state_tx_rx = RX_TX_IDLE;`
215	4	redbear	`end`
216	18	redbear	`else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 \|\| fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)`
217	4	redbear	`begin`
218	19	redbear	`next_state_tx_rx = RX_TX_START;`
219	2	redbear	`end`
220
221
222			`end`
223	19	redbear	`RX_TX_START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA`
224	2	redbear	`begin`
225			`if(count_send_data != DATA_CONFIG_REG[13:2])`
226			`begin`
227	19	redbear	`next_state_tx_rx = RX_TX_START;`
228	2	redbear	`end`
229			`else`
230			`begin`
231	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_1;`
232	2	redbear	`end`
233
234			`end`
235	19	redbear	`RX_TX_CONTROLIN_1:`
236	2	redbear	`begin`
237			`if(count_send_data != DATA_CONFIG_REG[13:2])`
238			`begin`
239	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_1;`
240	2	redbear	`end`
241			`else`
242			`begin`
243	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_2;`
244	2	redbear	`end`
245
246			`end`
247	19	redbear	`RX_TX_CONTROLIN_2:`
248	2	redbear	`begin`
249
250			`if(count_send_data != DATA_CONFIG_REG[13:2])`
251			`begin`
252	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_2;`
253	2	redbear	`end`
254			`else`
255			`begin`
256	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_3;`
257	2	redbear	`end`
258
259			`end`
260	19	redbear	`RX_TX_CONTROLIN_3:`
261	2	redbear	`begin`
262
263			`if(count_send_data != DATA_CONFIG_REG[13:2])`
264			`begin`
265	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_3;`
266	2	redbear	`end`
267			`else`
268			`begin`
269	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_4;`
270	2	redbear	`end`
271			`end`
272	19	redbear	`RX_TX_CONTROLIN_4:`
273	2	redbear	`begin`
274
275			`if(count_send_data != DATA_CONFIG_REG[13:2])`
276			`begin`
277	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_4;`
278	2	redbear	`end`
279			`else`
280			`begin`
281	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_5;`
282	2	redbear	`end`
283			`end`
284	19	redbear	`RX_TX_CONTROLIN_5:`
285	2	redbear	`begin`
286
287			`if(count_send_data != DATA_CONFIG_REG[13:2])`
288			`begin`
289	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_5;`
290	2	redbear	`end`
291			`else`
292			`begin`
293	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_6;`
294	2	redbear	`end`
295			`end`
296	19	redbear	`RX_TX_CONTROLIN_6:`
297	2	redbear	`begin`
298
299			`if(count_send_data != DATA_CONFIG_REG[13:2])`
300			`begin`
301	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_6;`
302	2	redbear	`end`
303			`else`
304			`begin`
305	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_7;`
306	2	redbear	`end`
307			`end`
308	19	redbear	`RX_TX_CONTROLIN_7:`
309	2	redbear	`begin`
310
311			`if(count_send_data != DATA_CONFIG_REG[13:2])`
312			`begin`
313	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_7;`
314	2	redbear	`end`
315			`else`
316			`begin`
317	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_8;`
318	2	redbear	`end`
319			`end`
320	19	redbear	`RX_TX_CONTROLIN_8:`
321	2	redbear	`begin`
322
323			`if(count_send_data != DATA_CONFIG_REG[13:2])`
324			`begin`
325	19	redbear	`next_state_tx_rx = RX_TX_CONTROLIN_8;`
326	2	redbear	`end`
327			`else`
328			`begin`
329	19	redbear	`next_state_tx_rx = RX_TX_RESPONSE_CIN;`
330	2	redbear	`end`
331			`end`
332	19	redbear	`RX_TX_RESPONSE_CIN:`
333	2	redbear	`begin`
334
335			`if(count_send_data != DATA_CONFIG_REG[13:2])`
336			`begin`
337	19	redbear	`next_state_tx_rx = RX_TX_RESPONSE_CIN;`
338	2	redbear	`end`
339			`else if(RESPONSE == 1'b0)//ACK`
340			`begin`
341	19	redbear	`next_state_tx_rx = RX_TX_DELAY_BYTES;`
342	2	redbear	`end`
343			`else if(RESPONSE == 1'b1)//NACK`
344			`begin`
345	19	redbear	`next_state_tx_rx = RX_TX_NACK;`
346	2	redbear	`end`
347
348			`end`
349
350			`//NOW SENDING ADDRESS`
351	19	redbear	`RX_TX_ADRESS_1:`
352	2	redbear	`begin`
353			`if(count_send_data != DATA_CONFIG_REG[13:2])`
354			`begin`
355	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_1;`
356	2	redbear	`end`
357			`else`
358			`begin`
359	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_2;`
360	2	redbear	`end`
361			`end`
362	19	redbear	`RX_TX_ADRESS_2:`
363	2	redbear	`begin`
364			`if(count_send_data != DATA_CONFIG_REG[13:2])`
365			`begin`
366	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_2;`
367	2	redbear	`end`
368			`else`
369			`begin`
370	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_3;`
371	2	redbear	`end`
372			`end`
373	19	redbear	`RX_TX_ADRESS_3:`
374	2	redbear	`begin`
375			`if(count_send_data != DATA_CONFIG_REG[13:2])`
376			`begin`
377	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_3;`
378	2	redbear	`end`
379			`else`
380			`begin`
381	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_4;`
382	2	redbear	`end`
383			`end`
384	19	redbear	`RX_TX_ADRESS_4:`
385	2	redbear	`begin`
386			`if(count_send_data != DATA_CONFIG_REG[13:2])`
387			`begin`
388	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_4;`
389	2	redbear	`end`
390			`else`
391			`begin`
392	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_5;`
393	2	redbear	`end`
394			`end`
395	19	redbear	`RX_TX_ADRESS_5:`
396	2	redbear	`begin`
397			`if(count_send_data != DATA_CONFIG_REG[13:2])`
398			`begin`
399	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_5;`
400	2	redbear	`end`
401			`else`
402			`begin`
403	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_6;`
404	2	redbear	`end`
405			`end`
406	19	redbear	`RX_TX_ADRESS_6:`
407	2	redbear	`begin`
408			`if(count_send_data != DATA_CONFIG_REG[13:2])`
409			`begin`
410	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_6;`
411	2	redbear	`end`
412			`else`
413			`begin`
414	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_7;`
415	2	redbear	`end`
416			`end`
417	19	redbear	`RX_TX_ADRESS_7:`
418	2	redbear	`begin`
419			`if(count_send_data != DATA_CONFIG_REG[13:2])`
420			`begin`
421	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_7;`
422	2	redbear	`end`
423			`else`
424			`begin`
425	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_8;`
426	2	redbear	`end`
427			`end`
428	19	redbear	`RX_TX_ADRESS_8:`
429	2	redbear	`begin`
430			`if(count_send_data != DATA_CONFIG_REG[13:2])`
431			`begin`
432	19	redbear	`next_state_tx_rx = RX_TX_ADRESS_8;`
433	2	redbear	`end`
434			`else`
435			`begin`
436	19	redbear	`next_state_tx_rx = RX_TX_RESPONSE_ADRESS;`
437	2	redbear	`end`
438			`end`
439	19	redbear	`RX_TX_RESPONSE_ADRESS:`
440	2	redbear	`begin`
441			`if(count_send_data != DATA_CONFIG_REG[13:2])`
442			`begin`
443	19	redbear	`next_state_tx_rx = RX_TX_RESPONSE_ADRESS;`
444	2	redbear	`end`
445			`else if(RESPONSE == 1'b0)//ACK`
446			`begin`
447	19	redbear	`next_state_tx_rx = RX_TX_DELAY_BYTES;`
448	2	redbear	`end`
449			`else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN`
450			`begin`
451	19	redbear	`next_state_tx_rx = RX_TX_NACK;`
452	2	redbear	`end`
453			`end`
454
455			`//data in`
456	19	redbear	`RX_TX_DATA0_1:`
457	2	redbear	`begin`
458			`if(count_send_data != DATA_CONFIG_REG[13:2])`
459			`begin`
460	19	redbear	`next_state_tx_rx = RX_TX_DATA0_1;`
461	2	redbear	`end`
462			`else`
463			`begin`
464	19	redbear	`next_state_tx_rx = RX_TX_DATA0_2;`
465	2	redbear	`end`
466			`end`
467	19	redbear	`RX_TX_DATA0_2:`
468	2	redbear	`begin`
469			`if(count_send_data != DATA_CONFIG_REG[13:2])`
470			`begin`
471	19	redbear	`next_state_tx_rx = RX_TX_DATA0_2;`
472	2	redbear	`end`
473			`else`
474			`begin`
475	19	redbear	`next_state_tx_rx = RX_TX_DATA0_3;`
476	2	redbear	`end`
477			`end`
478	19	redbear	`RX_TX_DATA0_3:`
479	2	redbear	`begin`
480			`if(count_send_data != DATA_CONFIG_REG[13:2])`
481			`begin`
482	19	redbear	`next_state_tx_rx = RX_TX_DATA0_3;`
483	2	redbear	`end`
484			`else`
485			`begin`
486	19	redbear	`next_state_tx_rx = RX_TX_DATA0_4;`
487	2	redbear	`end`
488			`end`
489	19	redbear	`RX_TX_DATA0_4:`
490	2	redbear	`begin`
491			`if(count_send_data != DATA_CONFIG_REG[13:2])`
492			`begin`
493	19	redbear	`next_state_tx_rx = RX_TX_DATA0_4;`
494	2	redbear	`end`
495			`else`
496			`begin`
497	19	redbear	`next_state_tx_rx = RX_TX_DATA0_5;`
498	2	redbear	`end`
499			`end`
500	19	redbear	`RX_TX_DATA0_5:`

Browse

Tools

Subversion Repositories apbi2c

[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Blame information for rev 19