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[/] [apbi2c/] [trunk/] [rtl/] [module_i2c.v] - Blame information for rev 24

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1 2 redbear
//////////////////////////////////////////////////////////////////
2
////
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////
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////    TOP I2C BLOCK to I2C Core
5
////
6
////
7
////
8
//// This file is part of the APB to I2C project
9
////
10
//// http://www.opencores.org/cores/apbi2c/
11
////
12
////
13
////
14
//// Description
15
////
16
//// Implementation of APB IP core according to
17
////
18
//// apbi2c_spec IP core specification document.
19
////
20
////
21
////
22
//// To Do: Things are right here but always all block can suffer changes
23
////
24
////
25
////
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////
27
////
28
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
29 4 redbear
////              Ronal Dario Celaya ,rcelaya.dario@gmail.com
30 2 redbear
////
31
///////////////////////////////////////////////////////////////// 
32
////
33
////
34
//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
38
//// This source file may be used and distributed without
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////
40
//// restriction provided that this copyright statement is not
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////
42
//// removed from the file and that any derivative work contains
43
//// the original copyright notice and the associated disclaimer.
44
////
45
////
46
//// This source file is free software; you can redistribute it
47
////
48
//// and/or modify it under the terms of the GNU Lesser General
49
////
50
//// Public License as published by the Free Software Foundation;
51
//// either version 2.1 of the License, or (at your option) any
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////
53
//// later version.
54
////
55
////
56
////
57
//// This source is distributed in the hope that it will be
58
////
59
//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
61
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
63
//// PURPOSE. See the GNU Lesser General Public License for more
64
//// details.
65
////
66
////
67
////
68
//// You should have received a copy of the GNU Lesser General
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////
70
//// Public License along with this source; if not, download it
71
////
72
//// from http://www.opencores.org/lgpl.shtml
73
////
74
////
75
///////////////////////////////////////////////////////////////////
76
 
77
 
78
`timescale 1ns/1ps //timescale 
79
 
80
module module_i2c#(
81
                        //THIS IS USED ONLY LIKE PARAMETER TO BEM CONFIGURABLE
82
                        parameter integer DWIDTH = 32,
83
                        parameter integer AWIDTH = 14
84
                )
85
                (
86
                //I2C INTERFACE WITH ANOTHER BLOCKS
87
                 input PCLK,
88
                 input PRESETn,
89
 
90
                //INTERFACE WITH FIFO TRANSMISSION
91
                 input fifo_tx_f_full,
92
                 input fifo_tx_f_empty,
93
                 input [DWIDTH-1:0] fifo_tx_data_out,
94
 
95
                //INTERFACE WITH FIFO RECEIVER
96
                 input fifo_rx_f_full,
97
                 input fifo_rx_f_empty,
98 6 redbear
                 output reg fifo_rx_wr_en,
99
                 output reg [DWIDTH-1:0] fifo_rx_data_in,
100 2 redbear
 
101
                //INTERFACE WITH REGISTER CONFIGURATION
102
                 input [AWIDTH-1:0] DATA_CONFIG_REG,
103 20 redbear
                 input [AWIDTH-1:0] TIMEOUT_TX,
104 2 redbear
 
105 20 redbear
                //INTERFACE TO APB AND READ FOR FIFO   
106 2 redbear
                 output reg fifo_tx_rd_en,
107 20 redbear
                 output   TX_EMPTY,
108
                 output   RX_EMPTY,
109 2 redbear
                 output ERROR,
110 20 redbear
                 output ENABLE_SDA,
111
                 output ENABLE_SCL,
112 2 redbear
 
113
                //I2C BI DIRETIONAL PORTS
114
                inout SDA,
115
                inout SCL
116
 
117
 
118
                 );
119
 
120
//THIS IS USED TO GENERATE INTERRUPTIONS
121
assign TX_EMPTY = (fifo_tx_f_empty == 1'b1)? 1'b1:1'b0;
122
assign RX_EMPTY = (fifo_rx_f_empty == 1'b1)? 1'b1:1'b0;
123
 
124
        //THIS COUNT IS USED TO CONTROL DATA ACCROSS FSM        
125 6 redbear
        reg [1:0] count_tx;
126 20 redbear
        reg [1:0] count_rx;
127 2 redbear
        //CONTROL CLOCK AND COUNTER
128
        reg [11:0] count_send_data;
129 20 redbear
        reg [11:0] count_receive_data;
130
        reg [11:0] count_timeout;
131 2 redbear
        reg BR_CLK_O;
132
        reg SDA_OUT;
133
 
134 20 redbear
        reg BR_CLK_O_RX;
135
        reg SDA_OUT_RX;
136
 
137 2 redbear
        //RESPONSE USED TO HOLD SIGNAL TO ACK OR NACK
138
        reg RESPONSE;
139
 
140 20 redbear
//    PARAMETERS USED TO STATE MACHINE
141 2 redbear
 
142 20 redbear
localparam [5:0] IDLE = 6'd0, //IDLE
143 2 redbear
 
144 20 redbear
           START = 6'd1,//START BIT
145 2 redbear
 
146 20 redbear
             CONTROLIN_1 = 6'd2, //START BYTE
147
             CONTROLIN_2 = 6'd3,
148
             CONTROLIN_3 = 6'd4,
149
             CONTROLIN_4 = 6'd5,
150
             CONTROLIN_5 = 6'd6,
151
             CONTROLIN_6 = 6'd7,
152
             CONTROLIN_7 = 6'd8,
153
             CONTROLIN_8 = 6'd9, //END FIRST BYTE
154 2 redbear
 
155 20 redbear
             RESPONSE_CIN =6'd10, //RESPONSE
156 2 redbear
 
157 20 redbear
             ADDRESS_1 = 6'd11,//START BYTE
158
             ADDRESS_2 = 6'd12,
159
             ADDRESS_3 = 6'd13,
160
             ADDRESS_4 = 6'd14,
161
             ADDRESS_5 = 6'd15,
162
             ADDRESS_6 = 6'd16,
163
             ADDRESS_7 = 6'd17,
164
             ADDRESS_8 = 6'd18,//END FIRST BYTE
165 2 redbear
 
166 20 redbear
             RESPONSE_ADDRESS =6'd19, //RESPONSE
167 2 redbear
 
168 20 redbear
             DATA0_1 = 6'd20,//START BYTE
169
             DATA0_2 = 6'd21,
170
             DATA0_3 = 6'd22,
171
             DATA0_4 = 6'd23,
172
             DATA0_5 = 6'd24,
173
             DATA0_6 = 6'd25,
174
             DATA0_7 = 6'd26,
175
             DATA0_8 = 6'd27,//END FIRST BYTE
176 2 redbear
 
177 20 redbear
             RESPONSE_DATA0_1 = 6'd28,  //RESPONSE
178 2 redbear
 
179 20 redbear
             DATA1_1 = 6'd29,//START BYTE
180
             DATA1_2 = 6'd30,
181
             DATA1_3 = 6'd31,
182
             DATA1_4 = 6'd32,
183
             DATA1_5 = 6'd33,
184
             DATA1_6 = 6'd34,
185
             DATA1_7 = 6'd35,
186
             DATA1_8 = 6'd36,//END FIRST BYTE
187 2 redbear
 
188 20 redbear
             RESPONSE_DATA1_1 = 6'd37,//RESPONSE
189 2 redbear
 
190 20 redbear
             DELAY_BYTES = 6'd38,//USED ONLY IN ACK TO DELAY BETWEEN
191
             NACK = 6'd39,//USED ONLY IN ACK TO DELAY BETWEEN BYTES
192
             STOP = 6'd40;//USED TO SEND STOP BIT
193 2 redbear
 
194
        //STATE CONTROL 
195 20 redbear
        reg [5:0] state_tx;
196
        reg [5:0] next_state_tx;
197 2 redbear
 
198
//ASSIGN REGISTERS TO BIDIRETIONAL PORTS
199 22 redbear
assign SDA =(DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0 & state_tx != RESPONSE_CIN & state_tx != RESPONSE_ADDRESS & state_tx != RESPONSE_DATA0_1 & state_tx != RESPONSE_DATA1_1)?SDA_OUT:SDA_OUT_RX;
200 2 redbear
 
201 22 redbear
 
202
assign SCL = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b0)?BR_CLK_O:BR_CLK_O_RX;
203
 
204 4 redbear
//STANDARD ERROR
205
assign ERROR = (DATA_CONFIG_REG[0] == 1'b1 & DATA_CONFIG_REG[1] == 1'b1)?1'b1:1'b0;
206 2 redbear
 
207 20 redbear
 
208
//COMBINATIONAL BLOCK TO   
209 2 redbear
always@(*)
210
begin
211
 
212
        //THE FUN START HERE :-)
213
        //COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
214 20 redbear
        next_state_tx=state_tx;
215 2 redbear
 
216 20 redbear
        case(state_tx)//state_   IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING 
217
        IDLE:
218 2 redbear
        begin
219
                //OBEYING SPEC
220 18 redbear
                if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
221 2 redbear
                begin
222 20 redbear
                        next_state_tx   = IDLE;
223 2 redbear
                end
224 18 redbear
                else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 || fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
225 2 redbear
                begin
226 20 redbear
                        next_state_tx   = IDLE;
227 4 redbear
                end
228 23 redbear
                else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_full == 1'b0 && fifo_tx_f_empty == 1'b0) || fifo_tx_f_full == 1'b1) && DATA_CONFIG_REG[1] == 1'b0 && count_timeout < TIMEOUT_TX)
229 4 redbear
                begin
230 20 redbear
                        next_state_tx   = START;
231 2 redbear
                end
232
 
233
 
234
        end
235 20 redbear
        START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
236 2 redbear
        begin
237
                if(count_send_data != DATA_CONFIG_REG[13:2])
238
                begin
239 20 redbear
                        next_state_tx   = START;
240 2 redbear
                end
241
                else
242
                begin
243 20 redbear
                        next_state_tx   = CONTROLIN_1;
244 2 redbear
                end
245
 
246
        end
247 20 redbear
        CONTROLIN_1:
248 2 redbear
        begin
249
                if(count_send_data != DATA_CONFIG_REG[13:2])
250
                begin
251 20 redbear
                        next_state_tx  = CONTROLIN_1;
252 2 redbear
                end
253
                else
254
                begin
255 20 redbear
                        next_state_tx  =  CONTROLIN_2;
256 2 redbear
                end
257
 
258
        end
259 20 redbear
        CONTROLIN_2:
260 2 redbear
        begin
261
 
262
                if(count_send_data != DATA_CONFIG_REG[13:2])
263
                begin
264 20 redbear
                        next_state_tx   = CONTROLIN_2;
265 2 redbear
                end
266
                else
267
                begin
268 20 redbear
                        next_state_tx   = CONTROLIN_3;
269 2 redbear
                end
270
 
271
        end
272 20 redbear
        CONTROLIN_3:
273 2 redbear
        begin
274
 
275
                if(count_send_data != DATA_CONFIG_REG[13:2])
276
                begin
277 20 redbear
                        next_state_tx  =  CONTROLIN_3;
278 2 redbear
                end
279
                else
280
                begin
281 20 redbear
                        next_state_tx   = CONTROLIN_4;
282 2 redbear
                end
283
        end
284 20 redbear
        CONTROLIN_4:
285 2 redbear
        begin
286
 
287
                if(count_send_data != DATA_CONFIG_REG[13:2])
288
                begin
289 20 redbear
                        next_state_tx   = CONTROLIN_4;
290 2 redbear
                end
291
                else
292
                begin
293 20 redbear
                        next_state_tx   = CONTROLIN_5;
294 2 redbear
                end
295
        end
296 20 redbear
        CONTROLIN_5:
297 2 redbear
        begin
298
 
299
                if(count_send_data != DATA_CONFIG_REG[13:2])
300
                begin
301 20 redbear
                        next_state_tx = CONTROLIN_5;
302 2 redbear
                end
303
                else
304
                begin
305 20 redbear
                        next_state_tx = CONTROLIN_6;
306 2 redbear
                end
307
        end
308 20 redbear
        CONTROLIN_6:
309 2 redbear
        begin
310
 
311
                if(count_send_data != DATA_CONFIG_REG[13:2])
312
                begin
313 20 redbear
                        next_state_tx = CONTROLIN_6;
314 2 redbear
                end
315
                else
316
                begin
317 20 redbear
                        next_state_tx = CONTROLIN_7;
318 2 redbear
                end
319
        end
320 20 redbear
        CONTROLIN_7:
321 2 redbear
        begin
322
 
323
                if(count_send_data != DATA_CONFIG_REG[13:2])
324
                begin
325 20 redbear
                        next_state_tx = CONTROLIN_7;
326 2 redbear
                end
327
                else
328
                begin
329 20 redbear
                        next_state_tx = CONTROLIN_8;
330 2 redbear
                end
331
        end
332 20 redbear
        CONTROLIN_8:
333 2 redbear
        begin
334
 
335
                if(count_send_data != DATA_CONFIG_REG[13:2])
336
                begin
337 20 redbear
                        next_state_tx  = CONTROLIN_8;
338 2 redbear
                end
339
                else
340
                begin
341 22 redbear
                        next_state_tx  = RESPONSE_CIN;
342 2 redbear
                end
343
        end
344 20 redbear
        RESPONSE_CIN:
345 2 redbear
        begin
346
 
347
                if(count_send_data != DATA_CONFIG_REG[13:2])
348
                begin
349 20 redbear
                        next_state_tx = RESPONSE_CIN;
350 2 redbear
                end
351
                else if(RESPONSE == 1'b0)//ACK
352
                begin
353 20 redbear
                        next_state_tx = DELAY_BYTES;
354 2 redbear
                end
355
                else if(RESPONSE == 1'b1)//NACK
356
                begin
357 20 redbear
                        next_state_tx = NACK;
358 2 redbear
                end
359
 
360
        end
361
 
362
        //NOW SENDING ADDRESS
363 20 redbear
        ADDRESS_1:
364 2 redbear
        begin
365
                if(count_send_data != DATA_CONFIG_REG[13:2])
366
                begin
367 20 redbear
                        next_state_tx  = ADDRESS_1;
368 2 redbear
                end
369
                else
370
                begin
371 20 redbear
                        next_state_tx  =  ADDRESS_2;
372 2 redbear
                end
373
        end
374 20 redbear
        ADDRESS_2:
375 2 redbear
        begin
376
                if(count_send_data != DATA_CONFIG_REG[13:2])
377
                begin
378 20 redbear
                        next_state_tx = ADDRESS_2;
379 2 redbear
                end
380
                else
381
                begin
382 20 redbear
                        next_state_tx = ADDRESS_3;
383 2 redbear
                end
384
        end
385 20 redbear
        ADDRESS_3:
386 2 redbear
        begin
387
                if(count_send_data != DATA_CONFIG_REG[13:2])
388
                begin
389 20 redbear
                        next_state_tx = ADDRESS_3;
390 2 redbear
                end
391
                else
392
                begin
393 20 redbear
                        next_state_tx = ADDRESS_4;
394 2 redbear
                end
395
        end
396 20 redbear
        ADDRESS_4:
397 2 redbear
        begin
398
                if(count_send_data != DATA_CONFIG_REG[13:2])
399
                begin
400 20 redbear
                        next_state_tx = ADDRESS_4;
401 2 redbear
                end
402
                else
403
                begin
404 20 redbear
                        next_state_tx = ADDRESS_5;
405 2 redbear
                end
406
        end
407 20 redbear
        ADDRESS_5:
408 2 redbear
        begin
409
                if(count_send_data != DATA_CONFIG_REG[13:2])
410
                begin
411 20 redbear
                        next_state_tx = ADDRESS_5;
412 2 redbear
                end
413
                else
414
                begin
415 20 redbear
                        next_state_tx = ADDRESS_6;
416 2 redbear
                end
417
        end
418 20 redbear
        ADDRESS_6:
419 2 redbear
        begin
420
                if(count_send_data != DATA_CONFIG_REG[13:2])
421
                begin
422 20 redbear
                        next_state_tx = ADDRESS_6;
423 2 redbear
                end
424
                else
425
                begin
426 20 redbear
                        next_state_tx = ADDRESS_7;
427 2 redbear
                end
428
        end
429 20 redbear
        ADDRESS_7:
430 2 redbear
        begin
431
                if(count_send_data != DATA_CONFIG_REG[13:2])
432
                begin
433 20 redbear
                        next_state_tx = ADDRESS_7;
434 2 redbear
                end
435
                else
436
                begin
437 20 redbear
                        next_state_tx = ADDRESS_8;
438 2 redbear
                end
439
        end
440 20 redbear
        ADDRESS_8:
441 2 redbear
        begin
442
                if(count_send_data != DATA_CONFIG_REG[13:2])
443
                begin
444 20 redbear
                        next_state_tx = ADDRESS_8;
445 2 redbear
                end
446
                else
447
                begin
448 20 redbear
                        next_state_tx = RESPONSE_ADDRESS;
449 2 redbear
                end
450
        end
451 20 redbear
        RESPONSE_ADDRESS:
452 2 redbear
        begin
453
                if(count_send_data != DATA_CONFIG_REG[13:2])
454
                begin
455 20 redbear
                        next_state_tx = RESPONSE_ADDRESS;
456 2 redbear
                end
457
                else if(RESPONSE == 1'b0)//ACK
458
                begin
459 20 redbear
                        next_state_tx = DELAY_BYTES;
460 2 redbear
                end
461
                else if(RESPONSE == 1'b1)//NACK --> RESTART CONDITION AND BACK TO START BYTE AGAIN
462
                begin
463 20 redbear
                        next_state_tx = NACK;
464 2 redbear
                end
465
        end
466
 
467
        //data in
468 20 redbear
        DATA0_1:
469 2 redbear
        begin
470
                if(count_send_data != DATA_CONFIG_REG[13:2])
471
                begin
472 20 redbear
                        next_state_tx = DATA0_1;
473 2 redbear
                end
474
                else
475
                begin
476 20 redbear
                        next_state_tx = DATA0_2;
477 2 redbear
                end
478
        end
479 20 redbear
        DATA0_2:
480 2 redbear
        begin
481
                if(count_send_data != DATA_CONFIG_REG[13:2])
482
                begin
483 20 redbear
                        next_state_tx = DATA0_2;
484 2 redbear
                end
485
                else
486
                begin
487 20 redbear
                        next_state_tx = DATA0_3;
488 2 redbear
                end
489
        end
490 20 redbear
        DATA0_3:
491 2 redbear
        begin
492
                if(count_send_data != DATA_CONFIG_REG[13:2])
493
                begin
494 20 redbear
                        next_state_tx = DATA0_3;
495 2 redbear
                end
496
                else
497
                begin
498 20 redbear
                        next_state_tx = DATA0_4;
499 2 redbear
                end
500
        end
501 20 redbear
        DATA0_4:
502 2 redbear
        begin
503
                if(count_send_data != DATA_CONFIG_REG[13:2])
504
                begin
505 20 redbear
                        next_state_tx = DATA0_4;
506 2 redbear
                end
507
                else
508
                begin
509 20 redbear
                        next_state_tx = DATA0_5;
510 2 redbear
                end
511
        end
512 20 redbear
        DATA0_5:
513 2 redbear
        begin
514
                if(count_send_data != DATA_CONFIG_REG[13:2])
515
                begin
516 20 redbear
                        next_state_tx = DATA0_5;
517 2 redbear
                end
518
                else
519
                begin
520 20 redbear
                        next_state_tx   = DATA0_6;
521 2 redbear
                end
522
        end
523 20 redbear
        DATA0_6:
524 2 redbear
        begin
525
                if(count_send_data != DATA_CONFIG_REG[13:2])
526
                begin
527 20 redbear
                        next_state_tx  = DATA0_6;
528 2 redbear
                end
529
                else
530
                begin
531 20 redbear
                        next_state_tx  = DATA0_7;
532 2 redbear
                end
533
        end
534 20 redbear
        DATA0_7:
535 2 redbear
        begin
536
                if(count_send_data != DATA_CONFIG_REG[13:2])
537
                begin
538 20 redbear
                        next_state_tx  = DATA0_7;
539 2 redbear
                end
540
                else
541
                begin
542 20 redbear
                        next_state_tx  = DATA0_8;
543 2 redbear
                end
544
        end
545 20 redbear
        DATA0_8:
546 2 redbear
        begin
547
                if(count_send_data != DATA_CONFIG_REG[13:2])
548
                begin
549 20 redbear
                        next_state_tx  = DATA0_8;
550 2 redbear
                end
551
                else
552
                begin
553 20 redbear
                        next_state_tx  =  RESPONSE_DATA0_1;
554 2 redbear
                end
555
        end
556 20 redbear
        RESPONSE_DATA0_1:
557 2 redbear
        begin
558
                if(count_send_data != DATA_CONFIG_REG[13:2])
559
                begin
560 20 redbear
                        next_state_tx  =  RESPONSE_DATA0_1;
561 2 redbear
                end
562
                else if(RESPONSE == 1'b0)//ACK
563
                begin
564 20 redbear
                        next_state_tx  =   DELAY_BYTES;
565 2 redbear
                end
566
                else if(RESPONSE == 1'b1)//NACK
567
                begin
568 20 redbear
                        next_state_tx  =   NACK;
569 2 redbear
                end
570
        end
571
 
572
        //second byte
573 20 redbear
        DATA1_1:
574 2 redbear
        begin
575
                if(count_send_data != DATA_CONFIG_REG[13:2])
576
                begin
577 20 redbear
                        next_state_tx  = DATA1_1;
578 2 redbear
                end
579
                else
580
                begin
581 20 redbear
                        next_state_tx  = DATA1_2;
582 2 redbear
                end
583
        end
584 20 redbear
        DATA1_2:
585 2 redbear
        begin
586
                if(count_send_data != DATA_CONFIG_REG[13:2])
587
                begin
588 20 redbear
                        next_state_tx = DATA1_2;
589 2 redbear
                end
590
                else
591
                begin
592 20 redbear
                        next_state_tx = DATA1_3;
593 2 redbear
                end
594
        end
595 20 redbear
        DATA1_3:
596 2 redbear
        begin
597
                if(count_send_data != DATA_CONFIG_REG[13:2])
598
                begin
599 20 redbear
                        next_state_tx  = DATA1_3;
600 2 redbear
                end
601
                else
602
                begin
603 20 redbear
                        next_state_tx  =  DATA1_4;
604 2 redbear
                end
605
        end
606 20 redbear
        DATA1_4:
607 2 redbear
        begin
608
                if(count_send_data != DATA_CONFIG_REG[13:2])
609
                begin
610 20 redbear
                        next_state_tx  = DATA1_4;
611 2 redbear
                end
612
                else
613
                begin
614 20 redbear
                        next_state_tx  = DATA1_5;
615 2 redbear
                end
616
        end
617 20 redbear
        DATA1_5:
618 2 redbear
        begin
619
                if(count_send_data != DATA_CONFIG_REG[13:2])
620
                begin
621 20 redbear
                        next_state_tx = DATA1_5;
622 2 redbear
                end
623
                else
624
                begin
625 20 redbear
                        next_state_tx = DATA1_6;
626 2 redbear
                end
627
        end
628 20 redbear
        DATA1_6:
629 2 redbear
        begin
630
                if(count_send_data != DATA_CONFIG_REG[13:2])
631
                begin
632 20 redbear
                        next_state_tx  =  DATA1_6;
633 2 redbear
                end
634
                else
635
                begin
636 20 redbear
                        next_state_tx  =  DATA1_7;
637 2 redbear
                end
638
        end
639 20 redbear
        DATA1_7:
640 2 redbear
        begin
641
                if(count_send_data != DATA_CONFIG_REG[13:2])
642
                begin
643 20 redbear
                        next_state_tx =  DATA1_7;
644 2 redbear
                end
645
                else
646
                begin
647 20 redbear
                        next_state_tx =  DATA1_8;
648 2 redbear
                end
649
        end
650 20 redbear
        DATA1_8:
651 2 redbear
        begin
652
                if(count_send_data != DATA_CONFIG_REG[13:2])
653
                begin
654 20 redbear
                        next_state_tx = DATA1_8;
655 2 redbear
                end
656
                else
657
                begin
658 20 redbear
                        next_state_tx = RESPONSE_DATA1_1;
659 2 redbear
                end
660
        end
661 20 redbear
        RESPONSE_DATA1_1:
662 2 redbear
        begin
663
                if(count_send_data != DATA_CONFIG_REG[13:2])
664
                begin
665 20 redbear
                        next_state_tx   =  RESPONSE_DATA1_1;
666 2 redbear
                end
667
                else if(RESPONSE == 1'b0)//ACK
668
                begin
669 20 redbear
                        next_state_tx   =  DELAY_BYTES;
670 2 redbear
                end
671
                else if(RESPONSE == 1'b1)//NACK
672
                begin
673 20 redbear
                        next_state_tx   =  NACK;
674 2 redbear
                end
675
        end
676 20 redbear
        DELAY_BYTES://THIS FORM WORKS 
677 2 redbear
        begin
678
 
679
 
680
                if(count_send_data != DATA_CONFIG_REG[13:2])
681
                begin
682 20 redbear
                        next_state_tx =  DELAY_BYTES;
683 2 redbear
                end
684
                else
685
                begin
686
 
687 6 redbear
                        if(count_tx == 2'd0)
688 2 redbear
                        begin
689 20 redbear
                                next_state_tx = ADDRESS_1;
690 2 redbear
                        end
691 20 redbear
                        else if(count_tx   == 2'd1)
692 2 redbear
                        begin
693 20 redbear
                                next_state_tx = DATA0_1;
694 2 redbear
                        end
695 20 redbear
                        else if(count_tx   == 2'd2)
696 2 redbear
                        begin
697 20 redbear
                                next_state_tx = DATA1_1;
698 2 redbear
                        end
699 20 redbear
                        else if(count_tx   == 2'd3)
700 2 redbear
                        begin
701 20 redbear
                                next_state_tx = STOP;
702 2 redbear
                        end
703
 
704
                end
705
 
706
        end
707 20 redbear
        NACK://NOT TESTED YET !!!!
708 2 redbear
        begin
709
                if(count_send_data != DATA_CONFIG_REG[13:2]*2'd2)
710
                begin
711 20 redbear
                        next_state_tx  = NACK;
712 2 redbear
                end
713
                else
714
                begin
715 6 redbear
                        if(count_tx == 2'd0)
716 2 redbear
                        begin
717 20 redbear
                                next_state_tx = CONTROLIN_1;
718 2 redbear
                        end
719 6 redbear
                        else if(count_tx == 2'd1)
720 2 redbear
                        begin
721 20 redbear
                                next_state_tx = ADDRESS_1;
722 2 redbear
                        end
723 20 redbear
                        else if(count_tx  == 2'd2)
724 2 redbear
                        begin
725 20 redbear
                                next_state_tx   = DATA0_1;
726 2 redbear
                        end
727 6 redbear
                        else if(count_tx == 2'd3)
728 2 redbear
                        begin
729 20 redbear
                                next_state_tx = DATA1_1;
730 2 redbear
                        end
731
                end
732
        end
733 20 redbear
        STOP://THIS WORK
734 2 redbear
        begin
735
                if(count_send_data != DATA_CONFIG_REG[13:2])
736
                begin
737 20 redbear
                        next_state_tx = STOP;
738 2 redbear
                end
739
                else
740
                begin
741 20 redbear
                        next_state_tx = IDLE;
742 2 redbear
                end
743
        end
744
        default:
745
        begin
746 20 redbear
                next_state_tx =  IDLE;
747 2 redbear
        end
748
        endcase
749
 
750
 
751
end
752 19 redbear
 
753
 
754
 
755 20 redbear
//SEQUENTIAL   
756 2 redbear
always@(posedge PCLK)
757
begin
758
 
759
        //RESET SYNC
760
        if(!PRESETn)
761
        begin
762
                //SIGNALS MUST BE RESETED
763
                count_send_data <= 12'd0;
764 20 redbear
                state_tx   <= IDLE;
765 2 redbear
                SDA_OUT<= 1'b1;
766
                fifo_tx_rd_en <= 1'b0;
767 20 redbear
                count_tx   <= 2'd0;
768 2 redbear
                BR_CLK_O <= 1'b1;
769
                RESPONSE<= 1'b0;
770
        end
771
        else
772
        begin
773
 
774
                // SEQUENTIAL FUN START
775 20 redbear
                state_tx  <= next_state_tx;
776 2 redbear
 
777 20 redbear
                case(state_tx)
778
                IDLE:
779 2 redbear
                begin
780
 
781
                        fifo_tx_rd_en <= 1'b0;
782
 
783
 
784 18 redbear
                        if(DATA_CONFIG_REG[0] == 1'b0 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b0)
785 2 redbear
                        begin
786
                                count_send_data <= 12'd0;
787
                                SDA_OUT<= 1'b1;
788
                                BR_CLK_O <= 1'b1;
789
                        end
790 23 redbear
                        else if(DATA_CONFIG_REG[0] == 1'b1 && ((fifo_tx_f_empty == 1'b0 && fifo_tx_f_full == 1'b0 )|| fifo_tx_f_full == 1'b1 ) && DATA_CONFIG_REG[1] == 1'b0)
791 2 redbear
                        begin
792
                                count_send_data <= count_send_data + 12'd1;
793
                                SDA_OUT<=1'b0;
794 4 redbear
                        end
795 18 redbear
                        else if(DATA_CONFIG_REG[0] == 1'b1 && (fifo_tx_f_full == 1'b1 ||fifo_tx_f_empty == 1'b0) && DATA_CONFIG_REG[1] == 1'b1)
796 4 redbear
                        begin
797
                                count_send_data <= 12'd0;
798
                                SDA_OUT<= 1'b1;
799
                                BR_CLK_O <= 1'b1;
800 2 redbear
                        end
801
 
802
                end
803 20 redbear
                START:
804 2 redbear
                begin
805
 
806
                        if(count_send_data < DATA_CONFIG_REG[13:2])
807
                        begin
808
                                count_send_data <= count_send_data + 12'd1;
809
                                BR_CLK_O <= 1'b0;
810
                        end
811
                        else
812
                        begin
813 7 redbear
                                count_send_data <= 12'd0;
814 2 redbear
                        end
815
 
816
                        if(count_send_data == DATA_CONFIG_REG[13:2]- 12'd1)
817
                        begin
818 6 redbear
                                SDA_OUT<=fifo_tx_data_out[0:0];
819 20 redbear
                                count_tx   <= 2'd0;
820 2 redbear
                        end
821
 
822
                end
823 20 redbear
                CONTROLIN_1:
824 2 redbear
                begin
825
 
826
 
827
 
828
                        if(count_send_data < DATA_CONFIG_REG[13:2])
829
                        begin
830
 
831
                                count_send_data <= count_send_data + 12'd1;
832
                                SDA_OUT<=fifo_tx_data_out[0:0];
833
 
834 7 redbear
 
835
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
836 2 redbear
                                begin
837 7 redbear
                                        BR_CLK_O <= 1'b0;
838
                                end
839
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
840
                                begin
841 2 redbear
                                        BR_CLK_O <= 1'b1;
842
                                end
843 7 redbear
                                else
844 2 redbear
                                begin
845
                                        BR_CLK_O <= 1'b0;
846
                                end
847
                        end
848
                        else
849
                        begin
850
                                count_send_data <= 12'd0;
851
                                SDA_OUT<=fifo_tx_data_out[1:1];
852
                        end
853
 
854
 
855
                end
856
 
857 20 redbear
                CONTROLIN_2:
858 2 redbear
                begin
859
 
860
 
861
 
862
                        if(count_send_data < DATA_CONFIG_REG[13:2])
863
                        begin
864
                                count_send_data <= count_send_data + 12'd1;
865
                                SDA_OUT<=fifo_tx_data_out[1:1];
866
 
867 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
868 2 redbear
                                begin
869 7 redbear
                                        BR_CLK_O <= 1'b0;
870
                                end
871
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
872
                                begin
873 2 redbear
                                        BR_CLK_O <= 1'b1;
874
                                end
875 7 redbear
                                else
876 2 redbear
                                begin
877
                                        BR_CLK_O <= 1'b0;
878 7 redbear
                                end
879 2 redbear
                        end
880
                        else
881
                        begin
882
                                count_send_data <= 12'd0;
883
                                SDA_OUT<=fifo_tx_data_out[2:2];
884
                        end
885
 
886
                end
887
 
888 20 redbear
                CONTROLIN_3:
889 2 redbear
                begin
890
 
891
 
892
 
893
                        if(count_send_data < DATA_CONFIG_REG[13:2])
894
                        begin
895
                                count_send_data <= count_send_data + 12'd1;
896
                                SDA_OUT<=fifo_tx_data_out[2:2];
897
 
898 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
899 2 redbear
                                begin
900 7 redbear
                                        BR_CLK_O <= 1'b0;
901
                                end
902
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
903
                                begin
904 2 redbear
                                        BR_CLK_O <= 1'b1;
905
                                end
906 7 redbear
                                else
907 2 redbear
                                begin
908
                                        BR_CLK_O <= 1'b0;
909 7 redbear
                                end
910 2 redbear
                        end
911
                        else
912
                        begin
913
                                count_send_data <= 12'd0;
914
                                SDA_OUT<=fifo_tx_data_out[3:3];
915
                        end
916
 
917
 
918
 
919
                end
920 20 redbear
                CONTROLIN_4:
921 2 redbear
                begin
922
 
923
                        if(count_send_data < DATA_CONFIG_REG[13:2])
924
                        begin
925
                                count_send_data <= count_send_data + 12'd1;
926
                                SDA_OUT<=fifo_tx_data_out[3:3];
927
 
928 22 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
929 2 redbear
                                begin
930 7 redbear
                                        BR_CLK_O <= 1'b0;
931
                                end
932
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
933
                                begin
934 2 redbear
                                        BR_CLK_O <= 1'b1;
935
                                end
936 7 redbear
                                else
937 2 redbear
                                begin
938
                                        BR_CLK_O <= 1'b0;
939 7 redbear
                                end
940 2 redbear
                        end
941
                        else
942
                        begin
943
                                count_send_data <= 12'd0;
944
                                SDA_OUT<=fifo_tx_data_out[4:4];
945
                        end
946
 
947
                end
948
 
949 20 redbear
                CONTROLIN_5:
950 2 redbear
                begin
951
 
952
 
953
 
954
                        if(count_send_data < DATA_CONFIG_REG[13:2])
955
                        begin
956
                                count_send_data <= count_send_data + 12'd1;
957
                                SDA_OUT<=fifo_tx_data_out[4:4];
958
 
959 22 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
960 2 redbear
                                begin
961 7 redbear
                                        BR_CLK_O <= 1'b0;
962
                                end
963
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
964
                                begin
965 2 redbear
                                        BR_CLK_O <= 1'b1;
966
                                end
967 7 redbear
                                else
968 2 redbear
                                begin
969
                                        BR_CLK_O <= 1'b0;
970 7 redbear
                                end
971 2 redbear
                        end
972
                        else
973
                        begin
974
                                count_send_data <= 12'd0;
975
                                SDA_OUT<=fifo_tx_data_out[5:5];
976
                        end
977
 
978
                end
979 20 redbear
                CONTROLIN_6:
980 2 redbear
                begin
981
 
982
                        if(count_send_data < DATA_CONFIG_REG[13:2])
983
                        begin
984
                                count_send_data <= count_send_data + 12'd1;
985
                                SDA_OUT<=fifo_tx_data_out[5:5];
986
 
987 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
988 2 redbear
                                begin
989 7 redbear
                                        BR_CLK_O <= 1'b0;
990
                                end
991
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
992
                                begin
993 2 redbear
                                        BR_CLK_O <= 1'b1;
994
                                end
995 7 redbear
                                else
996 2 redbear
                                begin
997
                                        BR_CLK_O <= 1'b0;
998
                                end
999
                        end
1000
                        else
1001
                        begin
1002
                                count_send_data <= 12'd0;
1003
                                SDA_OUT<=fifo_tx_data_out[6:6];
1004
                        end
1005
 
1006
 
1007
                end
1008
 
1009 20 redbear
                CONTROLIN_7:
1010 2 redbear
                begin
1011
 
1012
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1013
                        begin
1014
                                count_send_data <= count_send_data + 12'd1;
1015
                                SDA_OUT<=fifo_tx_data_out[6:6];
1016
 
1017 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1018 2 redbear
                                begin
1019 7 redbear
                                        BR_CLK_O <= 1'b0;
1020
                                end
1021
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1022
                                begin
1023 2 redbear
                                        BR_CLK_O <= 1'b1;
1024
                                end
1025 7 redbear
                                else
1026 2 redbear
                                begin
1027
                                        BR_CLK_O <= 1'b0;
1028
                                end
1029
                        end
1030
                        else
1031
                        begin
1032
                                count_send_data <= 12'd0;
1033
                                SDA_OUT<=fifo_tx_data_out[7:7];
1034
                        end
1035
 
1036
 
1037
                end
1038 20 redbear
                CONTROLIN_8:
1039 2 redbear
                begin
1040
 
1041
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1042
                        begin
1043
                                count_send_data <= count_send_data + 12'd1;
1044
                                SDA_OUT<=fifo_tx_data_out[7:7];
1045
 
1046 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1047 2 redbear
                                begin
1048 7 redbear
                                        BR_CLK_O <= 1'b0;
1049
                                end
1050
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1051
                                begin
1052 2 redbear
                                        BR_CLK_O <= 1'b1;
1053
                                end
1054 7 redbear
                                else
1055 2 redbear
                                begin
1056
                                        BR_CLK_O <= 1'b0;
1057 7 redbear
                                end
1058 2 redbear
                        end
1059
                        else
1060
                        begin
1061
                                count_send_data <= 12'd0;
1062
                                SDA_OUT<= 1'b0;
1063
                        end
1064
 
1065
 
1066
                end
1067 20 redbear
                RESPONSE_CIN:
1068 2 redbear
                begin
1069
 
1070
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1071
                        begin
1072
                                count_send_data <= count_send_data + 12'd1;
1073
 
1074
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
1075
                                RESPONSE<= SDA;
1076
 
1077 22 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1078 2 redbear
                                begin
1079 7 redbear
                                        BR_CLK_O <= 1'b0;
1080
                                end
1081
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1082
                                begin
1083 2 redbear
                                        BR_CLK_O <= 1'b1;
1084
                                end
1085 7 redbear
                                else
1086 2 redbear
                                begin
1087
                                        BR_CLK_O <= 1'b0;
1088 7 redbear
                                end
1089 2 redbear
                        end
1090
                        else
1091
                        begin
1092
                                count_send_data <= 12'd0;
1093
                        end
1094
 
1095
 
1096
                end
1097 20 redbear
                ADDRESS_1:
1098 2 redbear
                begin
1099
 
1100
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1101
                        begin
1102
                                count_send_data <= count_send_data + 12'd1;
1103
                                SDA_OUT<=fifo_tx_data_out[8:8];
1104
 
1105 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1106 2 redbear
                                begin
1107 7 redbear
                                        BR_CLK_O <= 1'b0;
1108
                                end
1109
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1110
                                begin
1111 2 redbear
                                        BR_CLK_O <= 1'b1;
1112
                                end
1113 7 redbear
                                else
1114 2 redbear
                                begin
1115
                                        BR_CLK_O <= 1'b0;
1116 7 redbear
                                end
1117 2 redbear
                        end
1118
                        else
1119
                        begin
1120
                                count_send_data <= 12'd0;
1121
                                SDA_OUT<=fifo_tx_data_out[9:9];
1122
                        end
1123
 
1124
                end
1125 20 redbear
                ADDRESS_2:
1126 2 redbear
                begin
1127
 
1128
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1129
                        begin
1130
                                count_send_data <= count_send_data + 12'd1;
1131
                                SDA_OUT<=fifo_tx_data_out[9:9];
1132
 
1133 24 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1134 2 redbear
                                begin
1135 7 redbear
                                        BR_CLK_O <= 1'b0;
1136
                                end
1137
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1138
                                begin
1139 2 redbear
                                        BR_CLK_O <= 1'b1;
1140
                                end
1141 7 redbear
                                else
1142 2 redbear
                                begin
1143
                                        BR_CLK_O <= 1'b0;
1144 7 redbear
                                end
1145 2 redbear
                        end
1146
                        else
1147
                        begin
1148
                                count_send_data <= 12'd0;
1149
                                SDA_OUT<=fifo_tx_data_out[10:10];
1150
                        end
1151
 
1152
                end
1153 20 redbear
                ADDRESS_3:
1154 2 redbear
                begin
1155
 
1156
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1157
                        begin
1158
                                count_send_data <= count_send_data + 12'd1;
1159
                                SDA_OUT<=fifo_tx_data_out[10:10];
1160
 
1161 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1162 2 redbear
                                begin
1163 7 redbear
                                        BR_CLK_O <= 1'b0;
1164
                                end
1165
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1166
                                begin
1167 2 redbear
                                        BR_CLK_O <= 1'b1;
1168
                                end
1169 7 redbear
                                else
1170 2 redbear
                                begin
1171
                                        BR_CLK_O <= 1'b0;
1172 7 redbear
                                end
1173 2 redbear
                        end
1174
                        else
1175
                        begin
1176
                                count_send_data <= 12'd0;
1177
                                SDA_OUT<=fifo_tx_data_out[11:11];
1178
                        end
1179
 
1180
                end
1181 20 redbear
                ADDRESS_4:
1182 2 redbear
                begin
1183
 
1184
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1185
                        begin
1186
                                count_send_data <= count_send_data + 12'd1;
1187
                                SDA_OUT<=fifo_tx_data_out[11:11];
1188
 
1189 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1190 2 redbear
                                begin
1191 7 redbear
                                        BR_CLK_O <= 1'b0;
1192
                                end
1193
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1194
                                begin
1195 2 redbear
                                        BR_CLK_O <= 1'b1;
1196
                                end
1197 7 redbear
                                else
1198 2 redbear
                                begin
1199
                                        BR_CLK_O <= 1'b0;
1200 7 redbear
                                end
1201 2 redbear
                        end
1202
                        else
1203
                        begin
1204
                                count_send_data <= 12'd0;
1205
                                SDA_OUT<=fifo_tx_data_out[12:12];
1206
                        end
1207
                end
1208 20 redbear
                ADDRESS_5:
1209 2 redbear
                begin
1210
 
1211
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1212
                        begin
1213 22 redbear
                                count_send_data <= count_send_data + 12'd1;
1214 2 redbear
                                SDA_OUT<=fifo_tx_data_out[12:12];
1215
 
1216 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1217 2 redbear
                                begin
1218 7 redbear
                                        BR_CLK_O <= 1'b0;
1219
                                end
1220
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1221
                                begin
1222 2 redbear
                                        BR_CLK_O <= 1'b1;
1223
                                end
1224 7 redbear
                                else
1225 2 redbear
                                begin
1226
                                        BR_CLK_O <= 1'b0;
1227 7 redbear
                                end
1228 2 redbear
                        end
1229
                        else
1230
                        begin
1231
                                count_send_data <= 12'd0;
1232
                                SDA_OUT<=fifo_tx_data_out[13:13];
1233
                        end
1234
 
1235
 
1236
                end
1237 20 redbear
                ADDRESS_6:
1238 2 redbear
                begin
1239
 
1240
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1241
                        begin
1242
                                count_send_data <= count_send_data + 12'd1;
1243
                                SDA_OUT<=fifo_tx_data_out[13:13];
1244
 
1245 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1246 2 redbear
                                begin
1247 7 redbear
                                        BR_CLK_O <= 1'b0;
1248
                                end
1249
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1250
                                begin
1251 2 redbear
                                        BR_CLK_O <= 1'b1;
1252
                                end
1253 7 redbear
                                else
1254 2 redbear
                                begin
1255
                                        BR_CLK_O <= 1'b0;
1256
                                end
1257
                        end
1258
                        else
1259
                        begin
1260 7 redbear
                                count_send_data <= 12'd0;
1261 2 redbear
                                SDA_OUT<=fifo_tx_data_out[14:14];
1262
                        end
1263
 
1264
                end
1265 20 redbear
                ADDRESS_7:
1266 2 redbear
                begin
1267
 
1268
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1269
                        begin
1270
                                count_send_data <= count_send_data + 12'd1;
1271
                                SDA_OUT<=fifo_tx_data_out[14:14];
1272
 
1273 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1274 2 redbear
                                begin
1275 7 redbear
                                        BR_CLK_O <= 1'b0;
1276
                                end
1277
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1278
                                begin
1279 2 redbear
                                        BR_CLK_O <= 1'b1;
1280
                                end
1281 7 redbear
                                else
1282 2 redbear
                                begin
1283
                                        BR_CLK_O <= 1'b0;
1284 7 redbear
                                end
1285 2 redbear
                        end
1286
                        else
1287
                        begin
1288
                                count_send_data <= 12'd0;
1289
                                SDA_OUT<=fifo_tx_data_out[15:15];
1290
                        end
1291
 
1292
 
1293
                end
1294 20 redbear
                ADDRESS_8:
1295 2 redbear
                begin
1296
 
1297
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1298
                        begin
1299
                                count_send_data <= count_send_data + 12'd1;
1300
                                SDA_OUT<=fifo_tx_data_out[15:15];
1301
 
1302 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1303 2 redbear
                                begin
1304 7 redbear
                                        BR_CLK_O <= 1'b0;
1305
                                end
1306
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1307
                                begin
1308 2 redbear
                                        BR_CLK_O <= 1'b1;
1309
                                end
1310 7 redbear
                                else
1311 2 redbear
                                begin
1312
                                        BR_CLK_O <= 1'b0;
1313
                                end
1314
                        end
1315
                        else
1316
                        begin
1317
                                count_send_data <= 12'd0;
1318 18 redbear
                                SDA_OUT<=1'b0;
1319 2 redbear
                        end
1320
 
1321
                end
1322 20 redbear
                RESPONSE_ADDRESS:
1323 2 redbear
                begin
1324
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1325
                        begin
1326
                                count_send_data <= count_send_data + 12'd1;
1327
 
1328
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
1329
                                RESPONSE<= SDA;
1330
 
1331 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1332 2 redbear
                                begin
1333 7 redbear
                                        BR_CLK_O <= 1'b0;
1334
                                end
1335
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1336
                                begin
1337 2 redbear
                                        BR_CLK_O <= 1'b1;
1338
                                end
1339 7 redbear
                                else
1340 2 redbear
                                begin
1341
                                        BR_CLK_O <= 1'b0;
1342
                                end
1343
                        end
1344
                        else
1345
                        begin
1346
                                count_send_data <= 12'd0;
1347
                        end
1348
 
1349
                end
1350 20 redbear
                DATA0_1:
1351 2 redbear
                begin
1352
 
1353
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1354
                        begin
1355
                                count_send_data <= count_send_data + 12'd1;
1356
                                SDA_OUT<=fifo_tx_data_out[16:16];
1357
 
1358 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1359 2 redbear
                                begin
1360 7 redbear
                                        BR_CLK_O <= 1'b0;
1361
                                end
1362
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1363
                                begin
1364 2 redbear
                                        BR_CLK_O <= 1'b1;
1365
                                end
1366 7 redbear
                                else
1367 2 redbear
                                begin
1368
                                        BR_CLK_O <= 1'b0;
1369
                                end
1370
                        end
1371
                        else
1372
                        begin
1373
                                count_send_data <= 12'd0;
1374
                                SDA_OUT<=fifo_tx_data_out[17:17];
1375
                        end
1376
 
1377
 
1378
                end
1379 20 redbear
                DATA0_2:
1380 2 redbear
                begin
1381
 
1382
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1383
                        begin
1384 22 redbear
                                count_send_data <= count_send_data + 12'd1;
1385 2 redbear
                                SDA_OUT<=fifo_tx_data_out[17:17];
1386
 
1387 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1388 2 redbear
                                begin
1389 7 redbear
                                        BR_CLK_O <= 1'b0;
1390
                                end
1391
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1392
                                begin
1393 2 redbear
                                        BR_CLK_O <= 1'b1;
1394
                                end
1395 7 redbear
                                else
1396 2 redbear
                                begin
1397
                                        BR_CLK_O <= 1'b0;
1398 7 redbear
                                end
1399 2 redbear
                        end
1400
                        else
1401
                        begin
1402
                                count_send_data <= 12'd0;
1403
                                SDA_OUT<=fifo_tx_data_out[18:18];
1404
                        end
1405
 
1406
 
1407
                end
1408 20 redbear
                DATA0_3:
1409 2 redbear
                begin
1410
 
1411
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1412
                        begin
1413
                                count_send_data <= count_send_data + 12'd1;
1414
                                SDA_OUT<=fifo_tx_data_out[18:18];
1415
 
1416 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1417 2 redbear
                                begin
1418 7 redbear
                                        BR_CLK_O <= 1'b0;
1419
                                end
1420
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1421
                                begin
1422 2 redbear
                                        BR_CLK_O <= 1'b1;
1423
                                end
1424 7 redbear
                                else
1425 2 redbear
                                begin
1426
                                        BR_CLK_O <= 1'b0;
1427 7 redbear
                                end
1428 2 redbear
                        end
1429
                        else
1430
                        begin
1431
                                count_send_data <= 12'd0;
1432
                                SDA_OUT<=fifo_tx_data_out[19:19];
1433
                        end
1434
 
1435
                end
1436 20 redbear
                DATA0_4:
1437 2 redbear
                begin
1438
 
1439
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1440
                        begin
1441
                                count_send_data <= count_send_data + 12'd1;
1442
                                SDA_OUT<=fifo_tx_data_out[19:19];
1443
 
1444 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1445 2 redbear
                                begin
1446 7 redbear
                                        BR_CLK_O <= 1'b0;
1447
                                end
1448
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1449
                                begin
1450 2 redbear
                                        BR_CLK_O <= 1'b1;
1451
                                end
1452 7 redbear
                                else
1453 2 redbear
                                begin
1454
                                        BR_CLK_O <= 1'b0;
1455 7 redbear
                                end
1456 2 redbear
                        end
1457
                        else
1458
                        begin
1459
                                count_send_data <= 12'd0;
1460
                                SDA_OUT<=fifo_tx_data_out[20:20];
1461
                        end
1462
 
1463
                end
1464 20 redbear
                DATA0_5:
1465 2 redbear
                begin
1466
 
1467
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1468
                        begin
1469
                                count_send_data <= count_send_data + 12'd1;
1470
                                SDA_OUT<=fifo_tx_data_out[20:20];
1471
 
1472 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1473 2 redbear
                                begin
1474 7 redbear
                                        BR_CLK_O <= 1'b0;
1475
                                end
1476
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1477
                                begin
1478 2 redbear
                                        BR_CLK_O <= 1'b1;
1479
                                end
1480 7 redbear
                                else
1481 2 redbear
                                begin
1482
                                        BR_CLK_O <= 1'b0;
1483
                                end
1484
                        end
1485
                        else
1486
                        begin
1487
                                count_send_data <= 12'd0;
1488
                                SDA_OUT<=fifo_tx_data_out[21:21];
1489
                        end
1490
 
1491
                end
1492 20 redbear
                DATA0_6:
1493 2 redbear
                begin
1494
 
1495
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1496
                        begin
1497
                                count_send_data <= count_send_data + 12'd1;
1498
                                SDA_OUT<=fifo_tx_data_out[21:21];
1499
 
1500 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1501 2 redbear
                                begin
1502 7 redbear
                                        BR_CLK_O <= 1'b0;
1503
                                end
1504
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1505
                                begin
1506 2 redbear
                                        BR_CLK_O <= 1'b1;
1507
                                end
1508 7 redbear
                                else
1509 2 redbear
                                begin
1510
                                        BR_CLK_O <= 1'b0;
1511
                                end
1512
                        end
1513
                        else
1514
                        begin
1515
                                count_send_data <= 12'd0;
1516
                                SDA_OUT<=fifo_tx_data_out[22:22];
1517
                        end
1518
 
1519
                end
1520 20 redbear
                DATA0_7:
1521 2 redbear
                begin
1522
 
1523
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1524
                        begin
1525
                                count_send_data <= count_send_data + 12'd1;
1526
                                SDA_OUT<=fifo_tx_data_out[22:22];
1527
 
1528 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1529 2 redbear
                                begin
1530 7 redbear
                                        BR_CLK_O <= 1'b0;
1531
                                end
1532
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1533
                                begin
1534 2 redbear
                                        BR_CLK_O <= 1'b1;
1535
                                end
1536 7 redbear
                                else
1537 2 redbear
                                begin
1538
                                        BR_CLK_O <= 1'b0;
1539 7 redbear
                                end
1540 2 redbear
                        end
1541
                        else
1542
                        begin
1543
                                count_send_data <= 12'd0;
1544
                                SDA_OUT<=fifo_tx_data_out[23:23];
1545
                        end
1546
 
1547
                end
1548 20 redbear
                DATA0_8:
1549 2 redbear
                begin
1550
 
1551
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1552
                        begin
1553
                                count_send_data <= count_send_data + 12'd1;
1554
                                SDA_OUT<=fifo_tx_data_out[23:23];
1555
 
1556 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1557 2 redbear
                                begin
1558 7 redbear
                                        BR_CLK_O <= 1'b0;
1559
                                end
1560
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1561
                                begin
1562 2 redbear
                                        BR_CLK_O <= 1'b1;
1563
                                end
1564 7 redbear
                                else
1565 2 redbear
                                begin
1566
                                        BR_CLK_O <= 1'b0;
1567
                                end
1568
 
1569
                        end
1570
                        else
1571
                        begin
1572
                                count_send_data <= 12'd0;
1573 18 redbear
                                SDA_OUT<=1'b0;
1574 2 redbear
                        end
1575
 
1576
                end
1577 20 redbear
                RESPONSE_DATA0_1:
1578 2 redbear
                begin
1579
 
1580
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1581
                        begin
1582
                                count_send_data <= count_send_data + 12'd1;
1583
 
1584
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
1585
                                RESPONSE<= SDA;
1586
 
1587 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1588 2 redbear
                                begin
1589 7 redbear
                                        BR_CLK_O <= 1'b0;
1590
                                end
1591
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1592
                                begin
1593 2 redbear
                                        BR_CLK_O <= 1'b1;
1594
                                end
1595 7 redbear
                                else
1596 2 redbear
                                begin
1597
                                        BR_CLK_O <= 1'b0;
1598 7 redbear
                                end
1599 2 redbear
                        end
1600
                        else
1601
                        begin
1602
                                count_send_data <= 12'd0;
1603
                        end
1604
 
1605
                end
1606 20 redbear
                DATA1_1:
1607 2 redbear
                begin
1608
 
1609
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1610
                        begin
1611
                                count_send_data <= count_send_data + 12'd1;
1612
                                SDA_OUT<=fifo_tx_data_out[24:24];
1613
 
1614 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1615 2 redbear
                                begin
1616 7 redbear
                                        BR_CLK_O <= 1'b0;
1617
                                end
1618
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1619
                                begin
1620 2 redbear
                                        BR_CLK_O <= 1'b1;
1621
                                end
1622 7 redbear
                                else
1623 2 redbear
                                begin
1624
                                        BR_CLK_O <= 1'b0;
1625 7 redbear
                                end
1626 2 redbear
                        end
1627
                        else
1628
                        begin
1629
                                count_send_data <= 12'd0;
1630
                                SDA_OUT<=fifo_tx_data_out[25:25];
1631
 
1632
                        end
1633
 
1634
 
1635
                end
1636 20 redbear
                DATA1_2:
1637 2 redbear
                begin
1638
 
1639
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1640
                        begin
1641
                                count_send_data <= count_send_data + 12'd1;
1642
                                SDA_OUT<=fifo_tx_data_out[25:25];
1643
 
1644 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1645 2 redbear
                                begin
1646 7 redbear
                                        BR_CLK_O <= 1'b0;
1647
                                end
1648
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1649
                                begin
1650 2 redbear
                                        BR_CLK_O <= 1'b1;
1651
                                end
1652 7 redbear
                                else
1653 2 redbear
                                begin
1654
                                        BR_CLK_O <= 1'b0;
1655 7 redbear
                                end
1656 2 redbear
                        end
1657
                        else
1658
                        begin
1659
                                count_send_data <= 12'd0;
1660
                                SDA_OUT<=fifo_tx_data_out[26:26];
1661
                        end
1662
 
1663
                end
1664 20 redbear
                DATA1_3:
1665 2 redbear
                begin
1666
 
1667
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1668
                        begin
1669
                                count_send_data <= count_send_data + 12'd1;
1670
                                SDA_OUT<=fifo_tx_data_out[26:26];
1671
 
1672 24 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1673 2 redbear
                                begin
1674 7 redbear
                                        BR_CLK_O <= 1'b0;
1675
                                end
1676
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1677
                                begin
1678 2 redbear
                                        BR_CLK_O <= 1'b1;
1679
                                end
1680 7 redbear
                                else
1681 2 redbear
                                begin
1682
                                        BR_CLK_O <= 1'b0;
1683
                                end
1684
 
1685
                        end
1686
                        else
1687
                        begin
1688
                                count_send_data <= 12'd0;
1689
                                SDA_OUT<=fifo_tx_data_out[27:27];
1690
                        end
1691
 
1692
                end
1693 20 redbear
                DATA1_4:
1694 2 redbear
                begin
1695
 
1696
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1697
                        begin
1698
                                count_send_data <= count_send_data + 12'd1;
1699
                                SDA_OUT<=fifo_tx_data_out[27:27];
1700
 
1701 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1702 2 redbear
                                begin
1703 7 redbear
                                        BR_CLK_O <= 1'b0;
1704
                                end
1705
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1706
                                begin
1707 2 redbear
                                        BR_CLK_O <= 1'b1;
1708
                                end
1709 7 redbear
                                else
1710 2 redbear
                                begin
1711
                                        BR_CLK_O <= 1'b0;
1712 7 redbear
                                end
1713 2 redbear
 
1714
                        end
1715
                        else
1716
                        begin
1717
                                count_send_data <= 12'd0;
1718
                                SDA_OUT<=fifo_tx_data_out[28:28];
1719
                        end
1720
 
1721
                end
1722 20 redbear
                DATA1_5:
1723 2 redbear
                begin
1724
 
1725
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1726
                        begin
1727
                                count_send_data <= count_send_data + 12'd1;
1728
                                SDA_OUT<=fifo_tx_data_out[28:28];
1729
 
1730 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1731 2 redbear
                                begin
1732 7 redbear
                                        BR_CLK_O <= 1'b0;
1733
                                end
1734
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1735
                                begin
1736 2 redbear
                                        BR_CLK_O <= 1'b1;
1737
                                end
1738 7 redbear
                                else
1739 2 redbear
                                begin
1740
                                        BR_CLK_O <= 1'b0;
1741
                                end
1742
 
1743
                        end
1744
                        else
1745
                        begin
1746
                                count_send_data <= 12'd0;
1747
                                SDA_OUT<=fifo_tx_data_out[29:29];
1748
                        end
1749
 
1750
                end
1751 20 redbear
                DATA1_6:
1752 2 redbear
                begin
1753
 
1754
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1755
                        begin
1756
                                count_send_data <= count_send_data + 12'd1;
1757
                                SDA_OUT<=fifo_tx_data_out[29:29];
1758
 
1759 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1760 2 redbear
                                begin
1761 7 redbear
                                        BR_CLK_O <= 1'b0;
1762
                                end
1763
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1764
                                begin
1765 2 redbear
                                        BR_CLK_O <= 1'b1;
1766
                                end
1767 7 redbear
                                else
1768 2 redbear
                                begin
1769
                                        BR_CLK_O <= 1'b0;
1770
                                end
1771
 
1772
                        end
1773
                        else
1774
                        begin
1775
                                count_send_data <= 12'd0;
1776
                                SDA_OUT<=fifo_tx_data_out[30:30];
1777
                        end
1778
 
1779
                end
1780 20 redbear
                DATA1_7:
1781 2 redbear
                begin
1782
 
1783
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1784
                        begin
1785
                                count_send_data <= count_send_data + 12'd1;
1786
                                SDA_OUT<=fifo_tx_data_out[30:30];
1787
 
1788 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1789 2 redbear
                                begin
1790 7 redbear
                                        BR_CLK_O <= 1'b0;
1791
                                end
1792
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1793
                                begin
1794 2 redbear
                                        BR_CLK_O <= 1'b1;
1795
                                end
1796 7 redbear
                                else
1797 2 redbear
                                begin
1798
                                        BR_CLK_O <= 1'b0;
1799
                                end
1800
 
1801
                        end
1802
                        else
1803
                        begin
1804
                                count_send_data <= 12'd0;
1805
                                SDA_OUT<=fifo_tx_data_out[31:31];
1806
                        end
1807
 
1808
 
1809
                end
1810 20 redbear
                DATA1_8:
1811 2 redbear
                begin
1812
 
1813
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1814
                        begin
1815
                                count_send_data <= count_send_data + 12'd1;
1816
                                SDA_OUT<=fifo_tx_data_out[31:31];
1817
 
1818 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1819 2 redbear
                                begin
1820 7 redbear
                                        BR_CLK_O <= 1'b0;
1821
                                end
1822
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1823
                                begin
1824 2 redbear
                                        BR_CLK_O <= 1'b1;
1825
                                end
1826 7 redbear
                                else
1827 2 redbear
                                begin
1828
                                        BR_CLK_O <= 1'b0;
1829
                                end
1830
 
1831
                        end
1832
                        else
1833
                        begin
1834
                                count_send_data <= 12'd0;
1835 18 redbear
                                SDA_OUT<=1'b0;
1836 2 redbear
                        end
1837
 
1838
                end
1839 20 redbear
                RESPONSE_DATA1_1:
1840 2 redbear
                begin
1841 20 redbear
                        //fifo_  _rd_en <= 1'b1;
1842 2 redbear
 
1843
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1844
                        begin
1845
                                count_send_data <= count_send_data + 12'd1;
1846
 
1847
                                //LETS TRY USE THIS BUT I DONT THINK IF WORKS  
1848
                                RESPONSE<= SDA;
1849
 
1850 7 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd4)
1851 2 redbear
                                begin
1852 7 redbear
                                        BR_CLK_O <= 1'b0;
1853
                                end
1854
                                else if(count_send_data >= DATA_CONFIG_REG[13:2]/12'd4 && count_send_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
1855
                                begin
1856 2 redbear
                                        BR_CLK_O <= 1'b1;
1857
                                end
1858 7 redbear
                                else
1859 2 redbear
                                begin
1860
                                        BR_CLK_O <= 1'b0;
1861 7 redbear
                                end
1862 2 redbear
                        end
1863
                        else
1864
                        begin
1865
                                count_send_data <= 12'd0;
1866
                                fifo_tx_rd_en <= 1'b1;
1867
                        end
1868
 
1869
                end
1870 20 redbear
                DELAY_BYTES:
1871 2 redbear
                begin
1872
 
1873
                        fifo_tx_rd_en <= 1'b0;
1874
 
1875
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1876
                        begin
1877
 
1878
                                count_send_data <= count_send_data + 12'd1;
1879
                                BR_CLK_O <= 1'b0;
1880
                                SDA_OUT<=1'b0;
1881
                        end
1882
                        else
1883
                        begin
1884
 
1885
 
1886 6 redbear
                                if(count_tx == 2'd0)
1887 2 redbear
                                begin
1888 6 redbear
                                        count_tx <= count_tx + 2'd1;
1889 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[8:8];
1890
                                end
1891 20 redbear
                                else if(count_tx   == 2'd1)
1892 2 redbear
                                begin
1893 6 redbear
                                        count_tx <= count_tx + 2'd1;
1894 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[16:16];
1895
                                end
1896 6 redbear
                                else if(count_tx == 2'd2)
1897 2 redbear
                                begin
1898 6 redbear
                                        count_tx <= count_tx + 2'd1;
1899 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[24:24];
1900
                                end
1901 6 redbear
                                else if(count_tx == 2'd3)
1902 2 redbear
                                begin
1903 6 redbear
                                        count_tx <= 2'd0;
1904 2 redbear
                                end
1905
 
1906
                                count_send_data <= 12'd0;
1907
 
1908
                        end
1909
 
1910
                end
1911
                //THIS BLOCK MUST BE CHECKED WITH CARE
1912 20 redbear
                NACK:// MORE A RESTART 
1913 2 redbear
                begin
1914
                        fifo_tx_rd_en <= 1'b0;
1915
 
1916 24 redbear
                        if(count_send_data < DATA_CONFIG_REG[13:2]*2'd3)
1917 2 redbear
                        begin
1918
                                count_send_data <= count_send_data + 12'd1;
1919
 
1920 20 redbear
                                if(count_receive_data < DATA_CONFIG_REG[13:2]/12'd2)
1921 2 redbear
                                begin
1922
                                        SDA_OUT<=1'b0;
1923
                                end
1924
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
1925
                                begin
1926
                                        SDA_OUT<=1'b1;
1927
                                end
1928
                                else if(count_send_data  == DATA_CONFIG_REG[13:2]*2'd2)
1929
                                begin
1930
                                        SDA_OUT<=1'b0;
1931
                                end
1932
 
1933 6 redbear
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2)
1934 2 redbear
                                begin
1935
                                        BR_CLK_O <= 1'b1;
1936
                                end
1937
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
1938
                                begin
1939
                                        BR_CLK_O <= 1'b0;
1940
                                end
1941
                                else if(count_send_data < DATA_CONFIG_REG[13:2]*2'd2)
1942
                                begin
1943
                                        BR_CLK_O <= 1'b1;
1944
                                end
1945
 
1946
                        end
1947
                        else
1948
                        begin
1949
                                count_send_data <= 12'd0;
1950
 
1951 6 redbear
                                if(count_tx == 2'd0)
1952 2 redbear
                                begin
1953 6 redbear
                                        count_tx <= 2'd0;
1954 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[0:0];
1955
                                end
1956 6 redbear
                                else if(count_tx == 2'd1)
1957 2 redbear
                                begin
1958 6 redbear
                                        count_tx <= 2'd1;
1959 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[8:8];
1960
                                end
1961 6 redbear
                                else if(count_tx == 2'd2)
1962 2 redbear
                                begin
1963 6 redbear
                                        count_tx <= 2'd2;
1964 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[16:16];
1965
                                end
1966 6 redbear
                                else if(count_tx == 2'd3)
1967 2 redbear
                                begin
1968 6 redbear
                                        count_tx <= 2'd3;
1969 2 redbear
                                        SDA_OUT<=fifo_tx_data_out[24:24];
1970
                                end
1971
 
1972
 
1973
                        end
1974
                end
1975 20 redbear
                STOP:
1976 2 redbear
                begin
1977 7 redbear
 
1978
                        BR_CLK_O <= 1'b1;
1979
 
1980 2 redbear
                        if(count_send_data < DATA_CONFIG_REG[13:2])
1981
                        begin
1982 22 redbear
                                count_send_data <= count_send_data + 12'd1;
1983 2 redbear
 
1984
                                if(count_send_data < DATA_CONFIG_REG[13:2]/12'd2-12'd2)
1985
                                begin
1986
                                        SDA_OUT<=1'b0;
1987
                                end
1988
                                else if(count_send_data > DATA_CONFIG_REG[13:2]/12'd2-12'd1 && count_send_data < DATA_CONFIG_REG[13:2])
1989
                                begin
1990
                                        SDA_OUT<=1'b1;
1991
                                end
1992
                        end
1993
                        else
1994
                        begin
1995
                                count_send_data <= 12'd0;
1996
                        end
1997
                end
1998
                default:
1999
                begin
2000
                        fifo_tx_rd_en <= 1'b0;
2001
                        count_send_data <= 12'd4095;
2002
                end
2003
                endcase
2004
 
2005
        end
2006
 
2007
 
2008
end
2009
 
2010 20 redbear
 
2011
        //STATE CONTROL 
2012
        reg [5:0] state_rx;
2013
        reg [5:0] next_state_rx;
2014
 
2015
assign ENABLE_SDA = (state_rx ==  RESPONSE_CIN||
2016
                     state_rx ==  RESPONSE_ADDRESS||
2017
                     state_rx == RESPONSE_DATA0_1||
2018
                     state_rx == RESPONSE_DATA1_1)?1'b1:
2019
                    (state_tx ==  RESPONSE_CIN||
2020
                     state_tx ==  RESPONSE_ADDRESS||
2021
                     state_tx == RESPONSE_DATA0_1||
2022
                     state_tx == RESPONSE_DATA1_1)?1'b0:1'b1;
2023
 
2024
 
2025
assign ENABLE_SCL = (state_rx ==  RESPONSE_CIN||
2026
                     state_rx ==  RESPONSE_ADDRESS||
2027
                     state_rx == RESPONSE_DATA0_1||
2028
                     state_rx == RESPONSE_DATA1_1)?1'b1:
2029
                    (state_tx ==  RESPONSE_CIN||
2030
                     state_tx ==  RESPONSE_ADDRESS||
2031
                     state_tx == RESPONSE_DATA0_1||
2032
                     state_tx == RESPONSE_DATA1_1)?1'b1:1'b0;
2033
 
2034
 
2035
//COMBINATIONAL BLOCK TO RX
2036
always@(*)
2037
begin
2038
 
2039
        //THE FUN START HERE :-)
2040
        //COMBINATIONAL UPDATE STATE BE CAREFUL WITH WHAT YOU MAKE HERE
2041
        next_state_rx = state_rx;
2042
 
2043
        case(state_rx)//state_rx IS MORE SECURE CHANGE ONLY IF YOU KNOW WHAT ARE YOU DOING 
2044
        IDLE:
2045
        begin
2046
                //OBEYING SPEC
2047
                if(DATA_CONFIG_REG[0] == 1'b0 && DATA_CONFIG_REG[1] == 1'b0)
2048
                begin
2049
                        next_state_rx =   IDLE;
2050
                end
2051
                else if(DATA_CONFIG_REG[0] == 1'b1 && DATA_CONFIG_REG[1] == 1'b1)
2052
                begin
2053
                        next_state_rx =   IDLE;
2054
                end
2055
                else if(DATA_CONFIG_REG[0] == 1'b0 && DATA_CONFIG_REG[1] == 1'b1 && SDA_OUT_RX == 1'b0 && BR_CLK_O_RX == 1'b0)
2056
                begin
2057
                        next_state_rx =   START;
2058
                end
2059
 
2060
 
2061
        end
2062
        START://THIS IS USED TOO ALL STATE MACHINES THE COUNTER_SEND_DATA
2063
        begin
2064
 
2065
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2066
                begin
2067
                        next_state_rx =   START;
2068
                end
2069
                else if(fifo_rx_data_in[0] == 1'b0 && fifo_rx_data_in[1] == 1'b0)
2070
                begin
2071
                        next_state_rx =   CONTROLIN_1;
2072
                end
2073
                else
2074
                begin
2075
                        next_state_rx =   IDLE;
2076
                end
2077
 
2078
        end
2079
          CONTROLIN_1:
2080
        begin
2081
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2082
                begin
2083
                        next_state_rx =   CONTROLIN_1;
2084
                end
2085
                else
2086
                begin
2087
                        next_state_rx =   CONTROLIN_2;
2088
                end
2089
 
2090
        end
2091
          CONTROLIN_2:
2092
        begin
2093
 
2094
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2095
                begin
2096
                        next_state_rx =   CONTROLIN_2;
2097
                end
2098
                else
2099
                begin
2100
                        next_state_rx =   CONTROLIN_3;
2101
                end
2102
 
2103
        end
2104
          CONTROLIN_3:
2105
        begin
2106
 
2107
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2108
                begin
2109
                        next_state_rx =   CONTROLIN_3;
2110
                end
2111
                else
2112
                begin
2113
                        next_state_rx =   CONTROLIN_4;
2114
                end
2115
        end
2116
          CONTROLIN_4:
2117
        begin
2118
 
2119
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2120
                begin
2121
                        next_state_rx =   CONTROLIN_4;
2122
                end
2123
                else
2124
                begin
2125
                        next_state_rx =   CONTROLIN_5;
2126
                end
2127
        end
2128
          CONTROLIN_5:
2129
        begin
2130
 
2131
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2132
                begin
2133
                        next_state_rx =   CONTROLIN_5;
2134
                end
2135
                else
2136
                begin
2137
                        next_state_rx =   CONTROLIN_6;
2138
                end
2139
        end
2140
          CONTROLIN_6:
2141
        begin
2142
 
2143
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2144
                begin
2145
                        next_state_rx =   CONTROLIN_6;
2146
                end
2147
                else
2148
                begin
2149
                        next_state_rx =   CONTROLIN_7;
2150
                end
2151
        end
2152
          CONTROLIN_7:
2153
        begin
2154
 
2155
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2156
                begin
2157
                        next_state_rx =   CONTROLIN_7;
2158
                end
2159
                else
2160
                begin
2161
                        next_state_rx =   CONTROLIN_8;
2162
                end
2163
        end
2164
          CONTROLIN_8:
2165
        begin
2166
 
2167
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2168
                begin
2169
                        next_state_rx =   CONTROLIN_8;
2170
                end
2171
                else
2172
                begin
2173
                        next_state_rx =   RESPONSE_CIN;
2174
                end
2175
        end
2176 22 redbear
        RESPONSE_CIN:
2177 20 redbear
        begin
2178
 
2179 22 redbear
                if(count_receive_data != DATA_CONFIG_REG[13:2])
2180 20 redbear
                begin
2181
                        next_state_rx =   RESPONSE_CIN;
2182
                end
2183 22 redbear
                else if(RESPONSE == 1'b0)//ACK
2184
                begin
2185
                        next_state_rx  =   DELAY_BYTES;
2186
                end
2187
                else if(RESPONSE == 1'b1)//NACK
2188 20 redbear
                begin
2189 22 redbear
                        next_state_rx  =   NACK;
2190
                end
2191 20 redbear
 
2192
        end
2193
        //NOW SENDING ADDRESS
2194 22 redbear
        ADDRESS_1:
2195 20 redbear
        begin
2196
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2197
                begin
2198
                        next_state_rx =   ADDRESS_1;
2199
                end
2200
                else
2201
                begin
2202
                        next_state_rx =   ADDRESS_2;
2203
                end
2204
        end
2205 22 redbear
        ADDRESS_2:
2206 20 redbear
        begin
2207
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2208
                begin
2209
                        next_state_rx =   ADDRESS_2;
2210
                end
2211
                else
2212
                begin
2213
                        next_state_rx =   ADDRESS_3;
2214
                end
2215
        end
2216 22 redbear
        ADDRESS_3:
2217 20 redbear
        begin
2218
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2219
                begin
2220
                        next_state_rx =   ADDRESS_3;
2221
                end
2222
                else
2223
                begin
2224
                        next_state_rx =   ADDRESS_4;
2225
                end
2226
        end
2227 22 redbear
        ADDRESS_4:
2228 20 redbear
        begin
2229
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2230
                begin
2231
                        next_state_rx =   ADDRESS_4;
2232
                end
2233
                else
2234
                begin
2235
                        next_state_rx =   ADDRESS_5;
2236
                end
2237
        end
2238 22 redbear
        ADDRESS_5:
2239 20 redbear
        begin
2240
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2241
                begin
2242
                        next_state_rx =   ADDRESS_5;
2243
                end
2244
                else
2245
                begin
2246
                        next_state_rx =   ADDRESS_6;
2247
                end
2248
        end
2249 22 redbear
        ADDRESS_6:
2250 20 redbear
        begin
2251
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2252
                begin
2253
                        next_state_rx =   ADDRESS_6;
2254
                end
2255
                else
2256
                begin
2257
                        next_state_rx =   ADDRESS_7;
2258
                end
2259
        end
2260 22 redbear
        ADDRESS_7:
2261 20 redbear
        begin
2262
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2263
                begin
2264
                        next_state_rx =   ADDRESS_7;
2265
                end
2266
                else
2267
                begin
2268
                        next_state_rx =   ADDRESS_8;
2269
                end
2270
        end
2271 22 redbear
        ADDRESS_8:
2272 20 redbear
        begin
2273
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2274
                begin
2275
                        next_state_rx =   ADDRESS_8;
2276
                end
2277
                else
2278
                begin
2279
                        next_state_rx =   RESPONSE_ADDRESS;
2280
                end
2281
        end
2282 22 redbear
        RESPONSE_ADDRESS:
2283 20 redbear
        begin
2284 22 redbear
                if(count_receive_data != DATA_CONFIG_REG[13:2])
2285 20 redbear
                begin
2286
                        next_state_rx =   RESPONSE_ADDRESS;
2287
                end
2288 22 redbear
                else if(RESPONSE == 1'b0)//ACK
2289 20 redbear
                begin
2290 22 redbear
                        next_state_rx  =   DELAY_BYTES;
2291 20 redbear
                end
2292 22 redbear
                else if(RESPONSE == 1'b1)//NACK
2293
                begin
2294
                        next_state_rx  =   NACK;
2295
                end
2296 20 redbear
        end
2297
        //data in
2298 22 redbear
        DATA0_1:
2299 20 redbear
        begin
2300
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2301
                begin
2302
                        next_state_rx =   DATA0_1;
2303
                end
2304
                else
2305
                begin
2306
                        next_state_rx =   DATA0_2;
2307
                end
2308
        end
2309
          DATA0_2:
2310
        begin
2311
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2312
                begin
2313
                        next_state_rx =   DATA0_2;
2314
                end
2315
                else
2316
                begin
2317
                        next_state_rx =   DATA0_3;
2318
                end
2319
        end
2320
          DATA0_3:
2321
        begin
2322
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2323
                begin
2324
                        next_state_rx =   DATA0_3;
2325
                end
2326
                else
2327
                begin
2328
                        next_state_rx =   DATA0_4;
2329
                end
2330
        end
2331
          DATA0_4:
2332
        begin
2333
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2334
                begin
2335
                        next_state_rx =   DATA0_4;
2336
                end
2337
                else
2338
                begin
2339
                        next_state_rx =   DATA0_5;
2340
                end
2341
        end
2342
          DATA0_5:
2343
        begin
2344
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2345
                begin
2346
                        next_state_rx =   DATA0_5;
2347
                end
2348
                else
2349
                begin
2350
                        next_state_rx =   DATA0_6;
2351
                end
2352
        end
2353
          DATA0_6:
2354
        begin
2355
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2356
                begin
2357
                        next_state_rx =   DATA0_6;
2358
                end
2359
                else
2360
                begin
2361
                        next_state_rx =   DATA0_7;
2362
                end
2363
        end
2364
          DATA0_7:
2365
        begin
2366
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2367
                begin
2368
                        next_state_rx =   DATA0_7;
2369
                end
2370
                else
2371
                begin
2372
                        next_state_rx =   DATA0_8;
2373
                end
2374
        end
2375
          DATA0_8:
2376
        begin
2377
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2378
                begin
2379
                        next_state_rx =   DATA0_8;
2380
                end
2381
                else
2382
                begin
2383
                        next_state_rx =   RESPONSE_DATA0_1;
2384
                end
2385
        end
2386 22 redbear
        RESPONSE_DATA0_1:
2387 20 redbear
        begin
2388 22 redbear
 
2389
                if(count_receive_data != DATA_CONFIG_REG[13:2])
2390 20 redbear
                begin
2391
                        next_state_rx =   RESPONSE_DATA0_1;
2392
                end
2393 22 redbear
                else if(RESPONSE == 1'b0)//ACK
2394 20 redbear
                begin
2395 22 redbear
                        next_state_rx  =   DELAY_BYTES;
2396 20 redbear
                end
2397 22 redbear
                else if(RESPONSE == 1'b1)//NACK
2398
                begin
2399
                        next_state_rx  =   NACK;
2400
                end
2401 20 redbear
        end
2402
        //second byte
2403 22 redbear
        DATA1_1:
2404 20 redbear
        begin
2405
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2406
                begin
2407
                        next_state_rx =   DATA1_1;
2408
                end
2409
                else
2410
                begin
2411
                        next_state_rx =   DATA1_2;
2412
                end
2413
        end
2414 22 redbear
        DATA1_2:
2415 20 redbear
        begin
2416
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2417
                begin
2418
                        next_state_rx =   DATA1_2;
2419
                end
2420
                else
2421
                begin
2422
                        next_state_rx =   DATA1_3;
2423
                end
2424
        end
2425 22 redbear
        DATA1_3:
2426 20 redbear
        begin
2427
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2428
                begin
2429
                        next_state_rx =   DATA1_3;
2430
                end
2431
                else
2432
                begin
2433
                        next_state_rx =   DATA1_4;
2434
                end
2435
        end
2436
          DATA1_4:
2437
        begin
2438
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2439
                begin
2440
                        next_state_rx =   DATA1_4;
2441
                end
2442
                else
2443
                begin
2444
                        next_state_rx =   DATA1_5;
2445
                end
2446
        end
2447
          DATA1_5:
2448
        begin
2449
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2450
                begin
2451
                        next_state_rx =   DATA1_5;
2452
                end
2453
                else
2454
                begin
2455
                        next_state_rx =   DATA1_6;
2456
                end
2457
        end
2458
          DATA1_6:
2459
        begin
2460
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2461
                begin
2462
                        next_state_rx =   DATA1_6;
2463
                end
2464
                else
2465
                begin
2466
                        next_state_rx =   DATA1_7;
2467
                end
2468
        end
2469
          DATA1_7:
2470
        begin
2471
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2472
                begin
2473
                        next_state_rx =   DATA1_7;
2474
                end
2475
                else
2476
                begin
2477
                        next_state_rx =   DATA1_8;
2478
                end
2479
        end
2480
          DATA1_8:
2481
        begin
2482
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2483
                begin
2484
                        next_state_rx =   DATA1_8;
2485
                end
2486
                else
2487
                begin
2488
                        next_state_rx =   RESPONSE_DATA1_1;
2489
                end
2490
        end
2491 22 redbear
        RESPONSE_DATA1_1:
2492 20 redbear
        begin
2493 22 redbear
                if(count_receive_data != DATA_CONFIG_REG[13:2])
2494 20 redbear
                begin
2495 22 redbear
                        next_state_rx =   RESPONSE_DATA0_1;
2496 20 redbear
                end
2497 22 redbear
                else if(RESPONSE == 1'b0)//ACK
2498 20 redbear
                begin
2499 22 redbear
                        next_state_rx  =   DELAY_BYTES;
2500 20 redbear
                end
2501 22 redbear
                else if(RESPONSE == 1'b1)//NACK
2502
                begin
2503
                        next_state_rx  =   NACK;
2504
                end
2505 20 redbear
 
2506
        end
2507 22 redbear
        DELAY_BYTES://THIS FORM WORKS 
2508 20 redbear
        begin
2509
 
2510
 
2511
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2512
                begin
2513
                        next_state_rx =   DELAY_BYTES;
2514
                end
2515
                else
2516
                begin
2517
 
2518
                        if(count_rx == 2'd0)
2519
                        begin
2520
                                next_state_rx =   ADDRESS_1;
2521
                        end
2522
                        else if(count_rx == 2'd1)
2523
                        begin
2524
                                next_state_rx =   DATA0_1;
2525
                        end
2526
                        else if(count_rx == 2'd2)
2527
                        begin
2528
                                next_state_rx =   DATA1_1;
2529
                        end
2530
                        else if(count_rx == 2'd3)
2531
                        begin
2532
                                next_state_rx =   STOP;
2533
                        end
2534
 
2535
                end
2536
 
2537
        end
2538
          STOP://THIS WORK
2539
        begin
2540
                if(  count_receive_data != DATA_CONFIG_REG[13:2])
2541
                begin
2542
                        next_state_rx =   STOP;
2543
                end
2544
                else
2545
                begin
2546
                        next_state_rx =   IDLE;
2547
                end
2548
        end
2549
        default:
2550
        begin
2551
                        next_state_rx =   IDLE;
2552
        end
2553
        endcase
2554
 
2555
 
2556
end
2557
 
2558
 
2559
 
2560
//SEQUENTIAL   
2561
always@(posedge PCLK)
2562
begin
2563
 
2564
        //RESET SYNC
2565
        if(!PRESETn)
2566
        begin
2567
                //SIGNALS MUST BE RESETED
2568
                  count_receive_data <= 12'd0;
2569
                state_rx <=   IDLE;
2570
                SDA_OUT_RX<= 1'b0;
2571
                fifo_rx_wr_en <= 1'b0;
2572
                count_rx <= 2'd0;
2573
                BR_CLK_O_RX <= 1'b0;
2574
        end
2575
        else
2576
        begin
2577
 
2578
                // SEQUENTIAL FUN START
2579
                state_rx <= next_state_rx;
2580
 
2581
                case(state_rx)
2582
                  IDLE:
2583
                begin
2584
 
2585
 
2586 23 redbear
 
2587 20 redbear
                        if(((fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b0) || (fifo_rx_f_full == 1'b0 && fifo_rx_f_empty == 1'b1)) && DATA_CONFIG_REG[1] == 1'b1)
2588
                        begin
2589
 
2590 23 redbear
                                  SDA_OUT_RX<= SDA;
2591
                                  BR_CLK_O_RX<=SCL;
2592 20 redbear
                                  count_receive_data <=   count_receive_data + 12'd1;
2593
                        end
2594
                        else
2595
                        begin
2596 23 redbear
                                  SDA_OUT_RX<= SDA_OUT_RX;
2597
                                  BR_CLK_O_RX<=BR_CLK_O_RX;
2598 20 redbear
                                  count_receive_data <=   count_receive_data;
2599
                        end
2600
 
2601
                end
2602
                  START:
2603
                begin
2604
 
2605
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2606
                        begin
2607
                                  count_receive_data <=   count_receive_data + 12'd1;
2608
                        end
2609
                        else
2610
                        begin
2611
                                  count_receive_data <= 12'd0;
2612
                        end
2613
 
2614
                        if(  count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2615
                        begin
2616
                                fifo_rx_data_in[0]<= SDA;
2617
                                fifo_rx_data_in[1]<= SCL;
2618
                        end
2619
 
2620
                end
2621
                  CONTROLIN_1:
2622
                begin
2623
 
2624
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2625
                        begin
2626
                                  count_receive_data <=   count_receive_data + 12'd1;
2627
                        end
2628
                        else
2629
                        begin
2630
                                  count_receive_data <= 12'd0;
2631
                        end
2632
 
2633
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2634
                        begin
2635
                                fifo_rx_data_in[0]<= SDA;
2636
                        end
2637
 
2638
                end
2639
                  CONTROLIN_2:
2640
                begin
2641
 
2642
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2643
                        begin
2644
                                  count_receive_data <=   count_receive_data + 12'd1;
2645
                        end
2646
                        else
2647
                        begin
2648
                                  count_receive_data <= 12'd0;
2649
                        end
2650
 
2651
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2652
                        begin
2653
                                fifo_rx_data_in[1]<= SDA;
2654
                        end
2655
 
2656
                end
2657
                  CONTROLIN_3:
2658
                begin
2659
 
2660
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2661
                        begin
2662
                                  count_receive_data <=   count_receive_data + 12'd1;
2663
                        end
2664
                        else
2665
                        begin
2666
                                  count_receive_data <= 12'd0;
2667
                        end
2668
 
2669
 
2670
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2671
                        begin
2672
                                fifo_rx_data_in[2]<= SDA;
2673
                        end
2674
 
2675
 
2676
                end
2677
                  CONTROLIN_4:
2678
                begin
2679
 
2680
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2681
                        begin
2682
                                  count_receive_data <=   count_receive_data + 12'd1;
2683
                        end
2684
                        else
2685
                        begin
2686
                                  count_receive_data <= 12'd0;
2687
                        end
2688
 
2689
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2690
                        begin
2691
                                fifo_rx_data_in[3]<= SDA;
2692
                        end
2693
 
2694
                end
2695
                  CONTROLIN_5:
2696
                begin
2697
 
2698
 
2699
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2700
                        begin
2701
                                  count_receive_data <=   count_receive_data + 12'd1;
2702
                        end
2703
                        else
2704
                        begin
2705
                                  count_receive_data <= 12'd0;
2706
                        end
2707
 
2708
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2709
                        begin
2710
                                        fifo_rx_data_in[4]<= SDA;
2711
                        end
2712
 
2713
 
2714
                end
2715
                  CONTROLIN_6:
2716
                begin
2717
                                if(  count_receive_data < DATA_CONFIG_REG[13:2])
2718
                                begin
2719
                                          count_receive_data <=   count_receive_data + 12'd1;
2720
                                end
2721
                                else
2722
                                begin
2723
                                          count_receive_data <= 12'd0;
2724
                                end
2725
 
2726
                                if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2727
                                begin
2728
                                        fifo_rx_data_in[5]<= SDA;
2729
                                end
2730
                end
2731
 
2732
                  CONTROLIN_7:
2733
                begin
2734
 
2735
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2736
                        begin
2737
                                  count_receive_data <=   count_receive_data + 12'd1;
2738
                        end
2739
                        else
2740
                        begin
2741
                                  count_receive_data <= 12'd0;
2742
                        end
2743
 
2744
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2745
                        begin
2746
                                fifo_rx_data_in[6]<= SDA;
2747
                        end
2748
                end
2749
                  CONTROLIN_8:
2750
                begin
2751
 
2752
 
2753
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2754
                        begin
2755
                                  count_receive_data <=   count_receive_data + 12'd1;
2756
                        end
2757
                        else
2758
                        begin
2759
                                  count_receive_data <= 12'd0;
2760
                        end
2761
 
2762
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2763
                        begin
2764
                                fifo_rx_data_in[7]<= SDA;
2765
                        end
2766
 
2767
 
2768
 
2769
                end
2770
                  RESPONSE_CIN:
2771
                begin
2772
 
2773
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2774
                        begin
2775
                                  count_receive_data <=   count_receive_data + 12'd1;
2776
                        end
2777
                        else
2778
                        begin
2779
                                  count_receive_data <= 12'd0;
2780
                        end
2781
 
2782
                end
2783
                  ADDRESS_1:
2784
                begin
2785
 
2786
 
2787
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2788
                        begin
2789
                                  count_receive_data <=   count_receive_data + 12'd1;
2790
                        end
2791
                        else
2792
                        begin
2793
                                  count_receive_data <= 12'd0;
2794
                        end
2795
 
2796
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2797
                        begin
2798
                                fifo_rx_data_in[8]<= SDA;
2799
                        end
2800
 
2801
 
2802
                end
2803
                  ADDRESS_2:
2804
                begin
2805
 
2806
 
2807
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2808
                        begin
2809
                                  count_receive_data <=   count_receive_data + 12'd1;
2810
                        end
2811
                        else
2812
                        begin
2813
                                  count_receive_data <= 12'd0;
2814
                        end
2815
 
2816
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2817
                        begin
2818
                                fifo_rx_data_in[9]<= SDA;
2819
                        end
2820
 
2821
 
2822
                end
2823
                  ADDRESS_3:
2824
                begin
2825
 
2826
 
2827
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2828
                        begin
2829
                                  count_receive_data <=   count_receive_data + 12'd1;
2830
                        end
2831
                        else
2832
                        begin
2833
                                  count_receive_data <= 12'd0;
2834
                        end
2835
 
2836
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2837
                        begin
2838
                                fifo_rx_data_in[10]<= SDA;
2839
                        end
2840
 
2841
 
2842
 
2843
                end
2844
                  ADDRESS_4:
2845
                begin
2846
 
2847
 
2848
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2849
                        begin
2850
                                  count_receive_data <=   count_receive_data + 12'd1;
2851
                        end
2852
                        else
2853
                        begin
2854
                                  count_receive_data <= 12'd0;
2855
                        end
2856
 
2857
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2858
                        begin
2859
                                fifo_rx_data_in[11]<= SDA;
2860
                        end
2861
 
2862
                end
2863
                  ADDRESS_5:
2864
                begin
2865
 
2866
 
2867
 
2868
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2869
                        begin
2870
                                  count_receive_data <=   count_receive_data + 12'd1;
2871
                        end
2872
                        else
2873
                        begin
2874
                                  count_receive_data <= 12'd0;
2875
                        end
2876
 
2877
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2878
                        begin
2879
                                fifo_rx_data_in[12]<= SDA;
2880
                        end
2881
 
2882
 
2883
                end
2884
                  ADDRESS_6:
2885
                begin
2886
 
2887
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2888
                        begin
2889
                                  count_receive_data <=   count_receive_data + 12'd1;
2890
                        end
2891
                        else
2892
                        begin
2893
                                  count_receive_data <= 12'd0;
2894
                        end
2895
 
2896
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2897
                        begin
2898
                                fifo_rx_data_in[13]<= SDA;
2899
                        end
2900
 
2901
                end
2902
                  ADDRESS_7:
2903
                begin
2904
 
2905
 
2906
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2907
                        begin
2908
                                  count_receive_data <=   count_receive_data + 12'd1;
2909
                        end
2910
                        else
2911
                        begin
2912
                                  count_receive_data <= 12'd0;
2913
                        end
2914
 
2915
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2916
                        begin
2917
                                fifo_rx_data_in[14]<= SDA;
2918
                        end
2919
 
2920
                end
2921
                  ADDRESS_8:
2922
                begin
2923
 
2924
 
2925
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2926
                        begin
2927
                                  count_receive_data <=   count_receive_data + 12'd1;
2928
                        end
2929
                        else
2930
                        begin
2931
                                  count_receive_data <= 12'd0;
2932
                        end
2933
 
2934
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2935
                        begin
2936
                                fifo_rx_data_in[15]<= SDA;
2937
                        end
2938
 
2939
 
2940
                end
2941
                  RESPONSE_ADDRESS:
2942
                begin
2943
 
2944
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2945
                        begin
2946
                                  count_receive_data <=   count_receive_data + 12'd1;
2947
                        end
2948
                        else
2949
                        begin
2950
                                  count_receive_data <= 12'd0;
2951
                        end
2952
 
2953
 
2954
                end
2955
                  DATA0_1:
2956
                begin
2957
 
2958
 
2959
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2960
                        begin
2961
                                  count_receive_data <=   count_receive_data + 12'd1;
2962
                        end
2963
                        else
2964
                        begin
2965
                                  count_receive_data <= 12'd0;
2966
                        end
2967
 
2968
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2969
                        begin
2970
                                fifo_rx_data_in[16]<= SDA;
2971
                        end
2972
 
2973
 
2974
 
2975
                end
2976
                  DATA0_2:
2977
                begin
2978
 
2979
 
2980
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
2981
                        begin
2982
                                  count_receive_data <=   count_receive_data + 12'd1;
2983
                        end
2984
                        else
2985
                        begin
2986
                                  count_receive_data <= 12'd0;
2987
                        end
2988
 
2989
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
2990
                        begin
2991
                                fifo_rx_data_in[17]<= SDA;
2992
                        end
2993
 
2994
 
2995
                end
2996
                  DATA0_3:
2997
                begin
2998
 
2999
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3000
                        begin
3001
                                  count_receive_data <=   count_receive_data + 12'd1;
3002
                        end
3003
                        else
3004
                        begin
3005
                                  count_receive_data <= 12'd0;
3006
                        end
3007
 
3008
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3009
                        begin
3010
                                fifo_rx_data_in[18]<= SDA;
3011
                        end
3012
 
3013
                end
3014
                  DATA0_4:
3015
                begin
3016
 
3017
 
3018
 
3019
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3020
                        begin
3021
                                  count_receive_data <=   count_receive_data + 12'd1;
3022
                        end
3023
                        else
3024
                        begin
3025
                                  count_receive_data <= 12'd0;
3026
                        end
3027
 
3028
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3029
                        begin
3030
                                fifo_rx_data_in[19]<= SDA;
3031
                        end
3032
 
3033
                end
3034
                  DATA0_5:
3035
                begin
3036
 
3037
 
3038
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3039
                        begin
3040
                                  count_receive_data <=   count_receive_data + 12'd1;
3041
                        end
3042
                        else
3043
                        begin
3044
                                  count_receive_data <= 12'd0;
3045
                        end
3046
 
3047
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3048
                        begin
3049
                                fifo_rx_data_in[20]<= SDA;
3050
                        end
3051
 
3052
 
3053
                end
3054
                  DATA0_6:
3055
                begin
3056
 
3057
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3058
                        begin
3059
                                  count_receive_data <=   count_receive_data + 12'd1;
3060
                        end
3061
                        else
3062
                        begin
3063
                                  count_receive_data <= 12'd0;
3064
                        end
3065
 
3066
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3067
                        begin
3068
                                fifo_rx_data_in[21]<= SDA;
3069
                        end
3070
 
3071
                end
3072
                  DATA0_7:
3073
                begin
3074
 
3075
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3076
                        begin
3077
                                  count_receive_data <=   count_receive_data + 12'd1;
3078
                        end
3079
                        else
3080
                        begin
3081
                                  count_receive_data <= 12'd0;
3082
                        end
3083
 
3084
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3085
                        begin
3086
                                fifo_rx_data_in[22]<= SDA;
3087
                        end
3088
 
3089
                end
3090
                  DATA0_8:
3091
                begin
3092
 
3093
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3094
                        begin
3095
                                  count_receive_data <=   count_receive_data + 12'd1;
3096
                        end
3097
                        else
3098
                        begin
3099
                                  count_receive_data <= 12'd0;
3100
                        end
3101
 
3102
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3103
                        begin
3104
                                fifo_rx_data_in[23]<= SDA;
3105
                        end
3106
 
3107
                end
3108
                  RESPONSE_DATA0_1:
3109
                begin
3110
 
3111
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3112
                        begin
3113
                                  count_receive_data <=   count_receive_data + 12'd1;
3114
                        end
3115
                        else
3116
                        begin
3117
                                  count_receive_data <= 12'd0;
3118
                        end
3119
 
3120
                end
3121
                  DATA1_1:
3122
                begin
3123
 
3124
 
3125
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3126
                        begin
3127
                                  count_receive_data <=   count_receive_data + 12'd1;
3128
                        end
3129
                        else
3130
                        begin
3131
                                  count_receive_data <= 12'd0;
3132
                        end
3133
 
3134
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3135
                        begin
3136
                                fifo_rx_data_in[24]<= SDA;
3137
                        end
3138
 
3139
                end
3140
                  DATA1_2:
3141
                begin
3142
 
3143
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3144
                        begin
3145
                                  count_receive_data <=   count_receive_data + 12'd1;
3146
                        end
3147
                        else
3148
                        begin
3149
                                  count_receive_data <= 12'd0;
3150
                        end
3151
 
3152
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3153
                        begin
3154
                                fifo_rx_data_in[25]<= SDA;
3155
                        end
3156
 
3157
 
3158
                end
3159
                  DATA1_3:
3160
                begin
3161
 
3162
 
3163
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3164
                        begin
3165
                                  count_receive_data <=   count_receive_data + 12'd1;
3166
                        end
3167
                        else
3168
                        begin
3169
                                  count_receive_data <= 12'd0;
3170
                        end
3171
 
3172
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3173
                        begin
3174
                                fifo_rx_data_in[26]<= SDA;
3175
                        end
3176
 
3177
 
3178
                end
3179
                  DATA1_4:
3180
                begin
3181
 
3182
 
3183
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3184
                        begin
3185
                                  count_receive_data <=   count_receive_data + 12'd1;
3186
                        end
3187
                        else
3188
                        begin
3189
                                  count_receive_data <= 12'd0;
3190
                        end
3191
 
3192
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3193
                        begin
3194
                                fifo_rx_data_in[27]<= SDA;
3195
                        end
3196
 
3197
 
3198
                end
3199
                  DATA1_5:
3200
                begin
3201
 
3202
 
3203
 
3204
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3205
                        begin
3206
                                  count_receive_data <=   count_receive_data + 12'd1;
3207
                        end
3208
                        else
3209
                        begin
3210
                                  count_receive_data <= 12'd0;
3211
                        end
3212
 
3213
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3214
                        begin
3215
                                fifo_rx_data_in[28]<= SDA;
3216
                        end
3217
 
3218
 
3219
                end
3220
                  DATA1_6:
3221
                begin
3222
 
3223
 
3224
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3225
                        begin
3226
                                  count_receive_data <=   count_receive_data + 12'd1;
3227
                        end
3228
                        else
3229
                        begin
3230
                                  count_receive_data <= 12'd0;
3231
                        end
3232
 
3233
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3234
                        begin
3235
                                fifo_rx_data_in[29]<= SDA;
3236
                        end
3237
 
3238
 
3239
 
3240
                end
3241
                  DATA1_7:
3242
                begin
3243
 
3244
 
3245
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3246
                        begin
3247
                                  count_receive_data <=   count_receive_data + 12'd1;
3248
                        end
3249
                        else
3250
                        begin
3251
                                  count_receive_data <= 12'd0;
3252
                        end
3253
 
3254
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3255
                        begin
3256
                                fifo_rx_data_in[30]<= SDA;
3257
                        end
3258
 
3259
 
3260
 
3261
                end
3262
                  DATA1_8:
3263
                begin
3264
 
3265
 
3266
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3267
                        begin
3268
                                  count_receive_data <=   count_receive_data + 12'd1;
3269
                        end
3270
                        else
3271
                        begin
3272
                                  count_receive_data <= 12'd0;
3273
                        end
3274
 
3275
                        if(SCL == 1'b1 &&   count_receive_data >= DATA_CONFIG_REG[13:2]/12'd4 &&   count_receive_data < (DATA_CONFIG_REG[13:2]-(DATA_CONFIG_REG[13:2]/12'd4))-12'd1)
3276
                        begin
3277
                                fifo_rx_data_in[31]<= SDA;
3278
                        end
3279
 
3280
                end
3281 22 redbear
                RESPONSE_DATA1_1:
3282 20 redbear
                begin
3283
 
3284
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3285
                        begin
3286
                                  count_receive_data <=   count_receive_data + 12'd1;
3287
                        end
3288
                        else
3289
                        begin
3290
                                  count_receive_data <= 12'd0;
3291
                        end
3292
                        //fifo_  _rd_en <= 1'b1;
3293
 
3294
                end
3295 22 redbear
                DELAY_BYTES:
3296 20 redbear
                begin
3297
 
3298
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3299
                        begin
3300
                                  count_receive_data <=   count_receive_data + 12'd1;
3301
                        end
3302
                        else
3303
                        begin
3304 22 redbear
 
3305
 
3306
                                if(count_rx == 2'd0)
3307
                                begin
3308
                                        count_rx <= count_rx + 2'd1;
3309
                                        //SDA_OUT<=fifo_tx_data_out[8:8];
3310
                                end
3311
                                else if(count_rx   == 2'd1)
3312
                                begin
3313
                                        count_rx <= count_tx + 2'd1;
3314
                                        //SDA_OUT<=fifo_tx_data_out[16:16];
3315
                                end
3316
                                else if(count_rx == 2'd2)
3317
                                begin
3318
                                        count_rx <= count_rx + 2'd1;
3319
                                        //SDA_OUT<=fifo_tx_data_out[24:24];
3320
                                end
3321
                                else if(count_rx == 2'd3)
3322
                                begin
3323
                                        count_rx <= 2'd0;
3324
                                end
3325
 
3326
                                count_receive_data <= 12'd0;
3327
 
3328 20 redbear
                        end
3329
 
3330
 
3331
                end
3332 22 redbear
                STOP:
3333 20 redbear
                begin
3334
                        if(  count_receive_data < DATA_CONFIG_REG[13:2])
3335
                        begin
3336
                                  count_receive_data <=   count_receive_data + 12'd1;
3337
                        end
3338
                        else
3339
                        begin
3340
                                  count_receive_data <= 12'd0;
3341
                        end
3342
                        fifo_rx_wr_en <= 1'b0;
3343
                end
3344
                default:
3345
                begin
3346
                        fifo_rx_wr_en <= 1'b0;
3347
                          count_receive_data <= 12'd4095;
3348
                end
3349
                endcase
3350
 
3351
        end
3352
 
3353
 
3354
end
3355
 
3356
//USED ONLY TO COUNTER TIME
3357
always@(posedge PCLK)
3358
begin
3359
 
3360
        //RESET SYNC
3361
        if(!PRESETn)
3362
        begin
3363
                count_timeout <= 12'd0;
3364
        end
3365
        else
3366
        begin
3367 23 redbear
                if(count_timeout <= TIMEOUT_TX && state_tx == IDLE)
3368 20 redbear
                begin
3369
                        if(SDA == 1'b0 && SCL == 1'b0)
3370
                        count_timeout <= count_timeout + 12'd1;
3371
                end
3372
                else
3373
                begin
3374
                        count_timeout <= 12'd0;
3375
                end
3376
 
3377
        end
3378
 
3379
end
3380
 
3381
 
3382 19 redbear
endmodule
3383 2 redbear
 

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