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[/] [apbtoaes128/] [trunk/] [pli/] [aes_bfm_wr.h] - Blame information for rev 7

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//////////////////////////////////////////////////////////////////
////
////
////    AES CORE BLOCK
////
////
////
//// This file is part of the APB to AES128 project
////
//// http://www.opencores.org/cores/apbtoaes128/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
static int aes_bfm_wr_calltf(char*user_data)
{
 
        vpiHandle PRESETn = vpi_handle_by_name("AES_GLADIC_tb.PRESETn", NULL);
        vpiHandle PWDATA = vpi_handle_by_name("AES_GLADIC_tb.PWDATA", NULL);
        vpiHandle PENABLE = vpi_handle_by_name("AES_GLADIC_tb.PENABLE", NULL);
        vpiHandle PSEL = vpi_handle_by_name("AES_GLADIC_tb.PSEL", NULL);
        vpiHandle PWRITE = vpi_handle_by_name("AES_GLADIC_tb.PWRITE", NULL);
        vpiHandle PADDR = vpi_handle_by_name("AES_GLADIC_tb.PADDR", NULL);
        vpiHandle PRDATA = vpi_handle_by_name("AES_GLADIC_tb.PRDATA", NULL);
        vpiHandle PREADY = vpi_handle_by_name("AES_GLADIC_tb.PREADY", NULL);
        vpiHandle PSLVERR = vpi_handle_by_name("AES_GLADIC_tb.PSLVERR", NULL);
        vpiHandle int_ccf = vpi_handle_by_name("AES_GLADIC_tb.int_ccf", NULL);
        vpiHandle int_err = vpi_handle_by_name("AES_GLADIC_tb.int_err", NULL);
        vpiHandle dma_req_wr = vpi_handle_by_name("AES_GLADIC_tb.dma_req_wr", NULL);
        vpiHandle dma_req_rd = vpi_handle_by_name("AES_GLADIC_tb.dma_req_rd", NULL);
 
        v_wr.format=vpiIntVal;
 
 
        std::random_device rd;
        std::uniform_int_distribution<long int> data_in(0,4294967295);
 
 
        v_wr.format=vpiIntVal;
        vpi_get_value(PRESETn, &v_wr);
 
 
        if(type_bfm == AES_WR_ONLY && v_wr.value.integer == 1)
        {
 
                //printf("%i\n",STATE);
 
                switch(STATE)
                {
 
                        case IDLE:
 
 
                                if(PACKETS_GENERATED >= MAX_ITERATIONS)
                                {
                                        STATE = IDLE;
                                        type_bfm = 0;
 
                                }else
                                {
                                        STATE = WRITE;
 
                                        counter = 0;
 
                                        v_wr.value.integer = vector_address[0];
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 4094;
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
                                }
 
 
 
                        break;
 
                        case WRITE:
 
                                if(counter == 0)
                                {
 
                                        counter_write++;
                                        counter++;
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
 
                                }else if(counter == 1)
                                {
 
                                        v_wr.value.integer = vector_address[counter_write];
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        t_wr.type = vpiScaledRealTime;
                                        t_wr.real = 0;
                                        v_wr.format=vpiIntVal;
 
                                        if(FIPS_ENABLE == FIPS)
                                        {
 
                                                if(vector_address[counter_write] == ADDR_AES_KEYR3 || vector_address[counter_write] == ADDR_AES_IVR3)
                                                {
                                                        a = a | KEY_FIPS_NOT_DERIVATED[0];
                                                        a = a << 8;
                                                        a = a | KEY_FIPS_NOT_DERIVATED[1];
                                                        a = a << 8;
                                                        a = a | KEY_FIPS_NOT_DERIVATED[2];
                                                        a = a << 8;
                                                        a = a | KEY_FIPS_NOT_DERIVATED[3];
                                                        v_wr.value.integer = a;
                                                }
 
 
                                                if(vector_address[counter_write] == ADDR_AES_KEYR2 || vector_address[counter_write] == ADDR_AES_IVR2)
                                                {
                                                        b = b | KEY_FIPS_NOT_DERIVATED[4];
                                                        b = b << 8;
                                                        b = b | KEY_FIPS_NOT_DERIVATED[5];
                                                        b = b << 8;
                                                        b = b | KEY_FIPS_NOT_DERIVATED[6];
                                                        b = b << 8;
                                                        b = b | KEY_FIPS_NOT_DERIVATED[7];
                                                        v_wr.value.integer = b;
                                                }
 
                                                if(vector_address[counter_write] == ADDR_AES_KEYR1 || vector_address[counter_write] == ADDR_AES_IVR1)
                                                {
 
                                                        c = c | KEY_FIPS_NOT_DERIVATED[8];
                                                        c = c << 8;
                                                        c = c | KEY_FIPS_NOT_DERIVATED[9];
                                                        c = c << 8;
                                                        c = c | KEY_FIPS_NOT_DERIVATED[10];
                                                        c = c << 8;
                                                        c = c | KEY_FIPS_NOT_DERIVATED[11];
                                                        v_wr.value.integer = c;
 
                                                }
 
                                                if(vector_address[counter_write] == ADDR_AES_KEYR0 || vector_address[counter_write] == ADDR_AES_IVR0)
                                                {
                                                        d = d | KEY_FIPS_NOT_DERIVATED[12];
                                                        d = d << 8;
                                                        d = d | KEY_FIPS_NOT_DERIVATED[13];
                                                        d = d << 8;
                                                        d = d | KEY_FIPS_NOT_DERIVATED[14];
                                                        d = d << 8;
                                                        d = d | KEY_FIPS_NOT_DERIVATED[15];
                                                        v_wr.value.integer = d;
                                                }
 
 
 
                                        }else if(FIPS_ENABLE == RANDOM_DATA)
                                        {
                                                v_wr.value.integer = data_in(rd);
                                        }
                                        vpi_put_value(PWDATA, &v_wr, &t_wr, vpiTransportDelay);
 
                                        a = 0;
                                        b = 0;
                                        c = 0;
                                        d = 0;
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
 
                                        counter=0;
                                }
 
                                if(counter_write == 12)
                                {
                                        STATE =WAIT;
                                        counter_write = 0;
 
                                }
 
 
                        break;
 
                        case WAIT:
 
                                v_wr.value.integer = 0;
                                vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                vpi_put_value(PWDATA, &v_wr, &t_wr, vpiTransportDelay);
 
                                if(counter_wait == 5)
                                {
 
                                        STATE = READ_RESULTS;
                                        counter_wait=0;
                                        v_wr.value.integer = vector_address[0];
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
 
                                }else
                                {
 
                                        counter_wait++;
 
                                }
                        break;
 
                        case READ_RESULTS:
 
 
 
                                if(counter == 0)
                                {
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        counter_read++;
                                        counter++;
 
                                }else if(counter == 1)
                                {
                                        counter++;
 
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = vector_address[counter_read];
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
 
                                        counter=0;
 
                                }
 
                                if(counter_read == 12)
                                {
                                        STATE = IDLE;
                                        counter_read = 0;
                                        PACKETS_GENERATED = PACKETS_GENERATED + 1;
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                }
 
                        break;
                }
 
 
 
        }
 
 
        return 0;
}

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Subversion Repositories apbtoaes128

[/] [apbtoaes128/] [trunk/] [pli/] [aes_bfm_wr.h] - Blame information for rev 7

Line No.	Rev	Author	Line
1	4	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// AES CORE BLOCK`
5			`////`
6			`////`
7			`////`
8			`//// This file is part of the APB to AES128 project`
9			`////`
10			`//// http://www.opencores.org/cores/apbtoaes128/`
11			`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// aes128_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: Things are right here but always all block can suffer changes`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29			`////`
30			`/////////////////////////////////////////////////////////////////`
31			`////`
32			`////`
33			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
34			`////`
35			`////`
36			`////`
37			`//// This source file may be used and distributed without`
38			`////`
39			`//// restriction provided that this copyright statement is not`
40			`////`
41			`//// removed from the file and that any derivative work contains`
42			`//// the original copyright notice and the associated disclaimer.`
43			`////`
44			`////`
45			`//// This source file is free software; you can redistribute it`
46			`////`
47			`//// and/or modify it under the terms of the GNU Lesser General`
48			`////`
49			`//// Public License as published by the Free Software Foundation;`
50			`//// either version 2.1 of the License, or (at your option) any`
51			`////`
52			`//// later version.`
53			`////`
54			`////`
55			`////`
56			`//// This source is distributed in the hope that it will be`
57			`////`
58			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
59			`////`
60			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
61			`////`
62			`//// PURPOSE. See the GNU Lesser General Public License for more`
63			`//// details.`
64			`////`
65			`////`
66			`////`
67			`//// You should have received a copy of the GNU Lesser General`
68			`////`
69			`//// Public License along with this source; if not, download it`
70			`////`
71			`//// from http://www.opencores.org/lgpl.shtml`
72			`////`
73			`////`
74			`///////////////////////////////////////////////////////////////////`
75			`static int aes_bfm_wr_calltf(char*user_data)`
76			`{`
77
78			`vpiHandle PRESETn = vpi_handle_by_name("AES_GLADIC_tb.PRESETn", NULL);`
79			`vpiHandle PWDATA = vpi_handle_by_name("AES_GLADIC_tb.PWDATA", NULL);`
80			`vpiHandle PENABLE = vpi_handle_by_name("AES_GLADIC_tb.PENABLE", NULL);`
81			`vpiHandle PSEL = vpi_handle_by_name("AES_GLADIC_tb.PSEL", NULL);`
82			`vpiHandle PWRITE = vpi_handle_by_name("AES_GLADIC_tb.PWRITE", NULL);`
83			`vpiHandle PADDR = vpi_handle_by_name("AES_GLADIC_tb.PADDR", NULL);`
84			`vpiHandle PRDATA = vpi_handle_by_name("AES_GLADIC_tb.PRDATA", NULL);`
85			`vpiHandle PREADY = vpi_handle_by_name("AES_GLADIC_tb.PREADY", NULL);`
86			`vpiHandle PSLVERR = vpi_handle_by_name("AES_GLADIC_tb.PSLVERR", NULL);`
87			`vpiHandle int_ccf = vpi_handle_by_name("AES_GLADIC_tb.int_ccf", NULL);`
88			`vpiHandle int_err = vpi_handle_by_name("AES_GLADIC_tb.int_err", NULL);`
89			`vpiHandle dma_req_wr = vpi_handle_by_name("AES_GLADIC_tb.dma_req_wr", NULL);`
90			`vpiHandle dma_req_rd = vpi_handle_by_name("AES_GLADIC_tb.dma_req_rd", NULL);`
91
92			`v_wr.format=vpiIntVal;`
93
94
95			`std::random_device rd;`
96			`std::uniform_int_distribution<long int> data_in(0,4294967295);`
97
98
99			`v_wr.format=vpiIntVal;`
100			`vpi_get_value(PRESETn, &v_wr);`
101
102
103			`if(type_bfm == AES_WR_ONLY && v_wr.value.integer == 1)`
104			`{`
105
106			`//printf("%i\n",STATE);`
107
108			`switch(STATE)`
109			`{`
110
111			`case IDLE:`
112
113
114			`if(PACKETS_GENERATED >= MAX_ITERATIONS)`
115			`{`
116			`STATE = IDLE;`
117			`type_bfm = 0;`
118
119			`}else`
120			`{`
121			`STATE = WRITE;`
122
123			`counter = 0;`
124
125			`v_wr.value.integer = vector_address[0];`
126			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
127
128			`v_wr.value.integer = 4094;`
129			`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
130
131			`v_wr.value.integer = 1;`
132			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
133
134			`v_wr.value.integer = 1;`
135			`vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);`
136			`}`
137
138
139
140			`break;`
141
142			`case WRITE:`
143
144			`if(counter == 0)`
145			`{`
146
147			`counter_write++;`
148			`counter++;`
149
150			`v_wr.value.integer = 1;`
151			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
152
153
154			`}else if(counter == 1)`
155			`{`
156
157			`v_wr.value.integer = vector_address[counter_write];`
158			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
159
160			`v_wr.value.integer = 0;`
161			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
162
163			`t_wr.type = vpiScaledRealTime;`
164			`t_wr.real = 0;`
165			`v_wr.format=vpiIntVal;`
166
167			`if(FIPS_ENABLE == FIPS)`
168			`{`
169
170			`if(vector_address[counter_write] == ADDR_AES_KEYR3 \|\| vector_address[counter_write] == ADDR_AES_IVR3)`
171			`{`
172			`a = a \| KEY_FIPS_NOT_DERIVATED[0];`
173			`a = a << 8;`
174			`a = a \| KEY_FIPS_NOT_DERIVATED[1];`
175			`a = a << 8;`
176			`a = a \| KEY_FIPS_NOT_DERIVATED[2];`
177			`a = a << 8;`
178			`a = a \| KEY_FIPS_NOT_DERIVATED[3];`
179			`v_wr.value.integer = a;`
180			`}`
181
182
183			`if(vector_address[counter_write] == ADDR_AES_KEYR2 \|\| vector_address[counter_write] == ADDR_AES_IVR2)`
184			`{`
185			`b = b \| KEY_FIPS_NOT_DERIVATED[4];`
186			`b = b << 8;`
187			`b = b \| KEY_FIPS_NOT_DERIVATED[5];`
188			`b = b << 8;`
189			`b = b \| KEY_FIPS_NOT_DERIVATED[6];`
190			`b = b << 8;`
191			`b = b \| KEY_FIPS_NOT_DERIVATED[7];`
192			`v_wr.value.integer = b;`
193			`}`
194
195			`if(vector_address[counter_write] == ADDR_AES_KEYR1 \|\| vector_address[counter_write] == ADDR_AES_IVR1)`
196			`{`
197
198			`c = c \| KEY_FIPS_NOT_DERIVATED[8];`
199			`c = c << 8;`
200			`c = c \| KEY_FIPS_NOT_DERIVATED[9];`
201			`c = c << 8;`
202			`c = c \| KEY_FIPS_NOT_DERIVATED[10];`
203			`c = c << 8;`
204			`c = c \| KEY_FIPS_NOT_DERIVATED[11];`
205			`v_wr.value.integer = c;`
206
207			`}`
208
209			`if(vector_address[counter_write] == ADDR_AES_KEYR0 \|\| vector_address[counter_write] == ADDR_AES_IVR0)`
210			`{`
211			`d = d \| KEY_FIPS_NOT_DERIVATED[12];`
212			`d = d << 8;`
213			`d = d \| KEY_FIPS_NOT_DERIVATED[13];`
214			`d = d << 8;`
215			`d = d \| KEY_FIPS_NOT_DERIVATED[14];`
216			`d = d << 8;`
217			`d = d \| KEY_FIPS_NOT_DERIVATED[15];`
218			`v_wr.value.integer = d;`
219			`}`
220
221
222
223			`}else if(FIPS_ENABLE == RANDOM_DATA)`
224			`{`
225			`v_wr.value.integer = data_in(rd);`
226			`}`
227			`vpi_put_value(PWDATA, &v_wr, &t_wr, vpiTransportDelay);`
228
229			`a = 0;`
230			`b = 0;`
231			`c = 0;`
232			`d = 0;`
233
234			`v_wr.value.integer = 1;`
235			`vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);`
236
237			`counter=0;`
238			`}`
239
240			`if(counter_write == 12)`
241			`{`
242			`STATE =WAIT;`
243			`counter_write = 0;`
244
245			`}`
246
247
248			`break;`
249
250			`case WAIT:`
251
252			`v_wr.value.integer = 0;`
253			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
254
255			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
256
257			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
258
259			`vpi_put_value(PWDATA, &v_wr, &t_wr, vpiTransportDelay);`
260
261			`if(counter_wait == 5)`
262			`{`
263
264			`STATE = READ_RESULTS;`
265			`counter_wait=0;`
266			`v_wr.value.integer = vector_address[0];`
267			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
268
269
270			`}else`
271			`{`
272
273			`counter_wait++;`
274
275			`}`
276			`break;`
277
278			`case READ_RESULTS:`
279
280
281
282			`if(counter == 0)`
283			`{`
284
285			`v_wr.value.integer = 1;`
286			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
287
288			`counter_read++;`
289			`counter++;`
290
291			`}else if(counter == 1)`
292			`{`
293			`counter++;`
294
295
296			`v_wr.value.integer = 0;`
297			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
298
299			`v_wr.value.integer = vector_address[counter_read];`
300			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
301
302			`v_wr.value.integer = 0;`
303			`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
304
305			`v_wr.value.integer = 1;`
306			`vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);`
307
308			`counter=0;`
309
310			`}`
311
312			`if(counter_read == 12)`
313			`{`
314			`STATE = IDLE;`
315			`counter_read = 0;`
316			`PACKETS_GENERATED = PACKETS_GENERATED + 1;`
317
318			`v_wr.value.integer = 0;`
319			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
320
321			`}`
322
323			`break;`
324			`}`
325
326
327
328			`}`
329
330
331			`return 0;`
332			`}`