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[/] [apbtoaes128/] [trunk/] [pli/] [bfm_error/] [aes_bfm_wr_error_dinr.h] - Blame information for rev 12

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//////////////////////////////////////////////////////////////////
////
////
////    AES CORE BLOCK
////
////
////
//// This file is part of the APB to AES128 project
////
//// http://www.opencores.org/cores/apbtoaes128/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
static int aes_bfm_wr_error_dinr_calltf(char*user_data)
{
 
        vpiHandle PRESETn = vpi_handle_by_name("AES_GLADIC_tb.PRESETn", NULL);
        vpiHandle PWDATA = vpi_handle_by_name("AES_GLADIC_tb.PWDATA", NULL);
        vpiHandle PENABLE = vpi_handle_by_name("AES_GLADIC_tb.PENABLE", NULL);
        vpiHandle PSEL = vpi_handle_by_name("AES_GLADIC_tb.PSEL", NULL);
        vpiHandle PWRITE = vpi_handle_by_name("AES_GLADIC_tb.PWRITE", NULL);
        vpiHandle PADDR = vpi_handle_by_name("AES_GLADIC_tb.PADDR", NULL);
        vpiHandle PRDATA = vpi_handle_by_name("AES_GLADIC_tb.PRDATA", NULL);
        vpiHandle PREADY = vpi_handle_by_name("AES_GLADIC_tb.PREADY", NULL);
        vpiHandle PSLVERR = vpi_handle_by_name("AES_GLADIC_tb.PSLVERR", NULL);
        vpiHandle int_ccf = vpi_handle_by_name("AES_GLADIC_tb.int_ccf", NULL);
        vpiHandle int_err = vpi_handle_by_name("AES_GLADIC_tb.int_err", NULL);
        vpiHandle dma_req_wr = vpi_handle_by_name("AES_GLADIC_tb.dma_req_wr", NULL);
        vpiHandle dma_req_rd = vpi_handle_by_name("AES_GLADIC_tb.dma_req_rd", NULL);
 
        v_wr.format=vpiIntVal;
 
 
        std::random_device rd;
        std::uniform_int_distribution<long int> data_in(0,4294967295);
 
 
        v_wr.format=vpiIntVal;
        vpi_get_value(PRESETn, &v_wr);
 
 
        if(type_bfm == AES_WR_ERROR_DINR_ONLY && v_wr.value.integer == 1)
        {
 
                //printf("%i\n",STATE);
 
                switch(STATE)
                {
 
                        case IDLE:
 
 
                                if(PACKETS_GENERATED >= MAX_ITERATIONS)
                                {
                                        STATE = IDLE;
                                        type_bfm = 0;
 
                                }else
                                {
                                        STATE = WRITE;
 
                                        counter = 0;
 
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
 
                                }
 
 
 
                        break;
 
                        case WRITE:
 
 
 
 
 
                                if(counter == 0)
                                {
 
                                        counter++;
                                        counter_write++;
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
 
                                }else if( counter == 1 )
                                {
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        if(counter_write < 9)
                                        {
 
                                                v_wr.value.integer = vector_address[counter_write];
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                        if(vector_address[counter_write] == ADDR_AES_KEYR3 || vector_address[counter_write] == ADDR_AES_IVR3)
                                        {
 
                                                a = a | KEY_FIPS_NOT_DERIVATED[0];
                                                a = a << 8;
                                                a = a | KEY_FIPS_NOT_DERIVATED[1];
                                                a = a << 8;
                                                a = a | KEY_FIPS_NOT_DERIVATED[2];
                                                a = a << 8;
                                                a = a | KEY_FIPS_NOT_DERIVATED[3];
                                                v_wr.value.integer = a;
                                        }
 
                                        if(vector_address[counter_write] == ADDR_AES_KEYR2 || vector_address[counter_write] == ADDR_AES_IVR2)
                                        {
 
                                                b = b | KEY_FIPS_NOT_DERIVATED[4];
                                                b = b << 8;
                                                b = b | KEY_FIPS_NOT_DERIVATED[5];
                                                b = b << 8;
                                                b = b | KEY_FIPS_NOT_DERIVATED[6];
                                                b = b << 8;
                                                b = b | KEY_FIPS_NOT_DERIVATED[7];
                                                v_wr.value.integer = b;
 
                                        }
 
                                        if(vector_address[counter_write] == ADDR_AES_KEYR1 || vector_address[counter_write] == ADDR_AES_IVR1)
                                        {
                                                c = c | KEY_FIPS_NOT_DERIVATED[8];
                                                c = c << 8;
                                                c = c | KEY_FIPS_NOT_DERIVATED[9];
                                                c = c << 8;
                                                c = c | KEY_FIPS_NOT_DERIVATED[10];
                                                c = c << 8;
                                                c = c | KEY_FIPS_NOT_DERIVATED[11];
                                                v_wr.value.integer = c;
                                        }
 
 
                                        if(vector_address[counter_write] == ADDR_AES_KEYR0 || vector_address[counter_write] == ADDR_AES_IVR0)
                                        {
 
                                                d = d | KEY_FIPS_NOT_DERIVATED[12];
                                                d = d << 8;
                                                d = d | KEY_FIPS_NOT_DERIVATED[13];
                                                d = d << 8;
                                                d = d | KEY_FIPS_NOT_DERIVATED[14];
                                                d = d << 8;
                                                d = d | KEY_FIPS_NOT_DERIVATED[15];
                                                v_wr.value.integer = d;
 
                                        }
 
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        a = 0;
                                        b = 0;
                                        c = 0;
                                        d = 0;
 
                                        }else if(counter_write == 9)//ENABLE CR
                                        {
                                                v_wr.value.integer = ADDR_AES_CR;
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                                v_wr.value.integer = vector_CR[PACKETS_GENERATED];
                                                vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        }else if(counter_write > 9  &&  counter_write < 14) //WRITE DINR
                                        {
 
                                                        v_wr.value.integer = ADDR_AES_DINR;
                                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                                        if(counter_write == 10)
                                                        {
                                                                a = a | TEXT_FIPS_NOT_DERIVATED[0];
                                                                a = a << 8;
                                                                a = a | TEXT_FIPS_NOT_DERIVATED[1];
                                                                a = a << 8;
                                                                a = a | TEXT_FIPS_NOT_DERIVATED[2];
                                                                a = a << 8;
                                                                a = a | TEXT_FIPS_NOT_DERIVATED[3];
                                                                v_wr.value.integer = a;
 
                                                        }else if(counter_write == 11)
                                                        {
                                                                b = b | TEXT_FIPS_NOT_DERIVATED[4];
                                                                b = b << 8;
                                                                b = b | TEXT_FIPS_NOT_DERIVATED[5];
                                                                b = b << 8;
                                                                b = b | TEXT_FIPS_NOT_DERIVATED[6];
                                                                b = b << 8;
                                                                b = b | TEXT_FIPS_NOT_DERIVATED[7];
                                                                v_wr.value.integer = b;
 
                                                        }else if(counter_write == 12 )
                                                        {
 
                                                                c = c | TEXT_FIPS_NOT_DERIVATED[8];
                                                                c = c << 8;
                                                                c = c | TEXT_FIPS_NOT_DERIVATED[9];
                                                                c = c << 8;
                                                                c = c | TEXT_FIPS_NOT_DERIVATED[10];
                                                                c = c << 8;
                                                                c = c | TEXT_FIPS_NOT_DERIVATED[11];
                                                                v_wr.value.integer = c;
 
                                                        }else if(counter_write == 13 )
                                                        {
                                                                d = d | TEXT_FIPS_NOT_DERIVATED[12];
                                                                d = d << 8;
                                                                d = d | TEXT_FIPS_NOT_DERIVATED[13];
                                                                d = d << 8;
                                                                d = d | TEXT_FIPS_NOT_DERIVATED[14];
                                                                d = d << 8;
                                                                d = d | TEXT_FIPS_NOT_DERIVATED[15];
                                                                v_wr.value.integer = d;
 
                                                        }
 
                                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
 
                                                        a = 0;
                                                        b = 0;
                                                        c = 0;
                                                        d = 0;
 
                                        }
 
                                        counter=0;
                                }
 
 
 
 
                                if(counter_write == 14)
                                {
                                        counter_write = 0;
                                        STATE = WAIT;
                                }
 
 
                        break;
 
                        case WAIT:
 
 
 
 
                                if(counter_wait == 1)
                                {
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                        STATE = WRITE_DINR;
                                        counter_wait=0;
                                        counter_write = 0;
                                        counter=1;
 
 
                                }else
                                {
 
                                        counter_wait++;
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                }
                        break;
 
                        case WRITE_DINR:
 
 
 
 
                                if(counter == 0)
                                {
 
                                        counter++;
                                        counter_write++;
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
 
                                }else if(counter == 1)
                                {
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        if(counter_write == 13)//ENABLE CR
                                        {
 
                                                v_wr.value.integer =1;
                                                vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                                v_wr.value.integer = ADDR_AES_CR;
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                                v_wr.value.integer = 0;
                                                vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        }else
                                        {
                                                v_wr.value.integer = ADDR_AES_DINR;
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
                                        }
 
 
                                        counter=0;
                                }
 
 
 
                                if(counter_write == 14)
                                {
                                        STATE = READ_RESULTS;
                                        counter_write = 0;
                                        counter_read  = 0;
                                        counter=1;
 
                                }
 
 
                        break;
 
                        case READ_RESULTS:
 
 
 
                                v_wr.value.integer = 0;
                                vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                v_wr.value.integer = 1;
                                vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
 
                                if(counter == 0)
                                {
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        counter_read++;
                                        counter++;
 
 
                                }else if(counter == 1)
                                {
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
 
                                        if(counter_read <= 9)
                                        {
                                                v_wr.value.integer = vector_address[counter_read];
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
                                        }
                                        else
                                        {
 
 
                                        }
 
 
 
                                        counter=0;
 
                                }
 
                                if(counter_read == 14)
                                {
                                        STATE = RESET_SR;
                                        counter_read = 0;
                                        PACKETS_GENERATED = PACKETS_GENERATED + 1;
 
                                        counter=1;
 
                                }
 
                        break;
 
                case RESET_SR:
 
 
 
 
                                if(counter == 0)
                                {
 
                                        counter_write++;
                                        counter++;
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                }else if(counter == 1)
                                {
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 1;
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
 
                                        v_wr.value.integer = 384;
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
 
                                        counter=0;
 
                                }
 
                                if(counter_write == 2)
                                {
                                        STATE =IDLE;
                                        counter_write = 0;
                                        counter=1;
                                        v_wr.value.integer = 0;
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
                                }
 
 
 
                break;
                }
 
 
 
        }
 
 
        return 0;
}

Line No.	Rev	Author	Line
1	4	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// AES CORE BLOCK`
5			`////`
6			`////`
7			`////`
8			`//// This file is part of the APB to AES128 project`
9			`////`
10			`//// http://www.opencores.org/cores/apbtoaes128/`
11			`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// aes128_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: Things are right here but always all block can suffer changes`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29			`////`
30			`/////////////////////////////////////////////////////////////////`
31			`////`
32			`////`
33			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
34			`////`
35			`////`
36			`////`
37			`//// This source file may be used and distributed without`
38			`////`
39			`//// restriction provided that this copyright statement is not`
40			`////`
41			`//// removed from the file and that any derivative work contains`
42			`//// the original copyright notice and the associated disclaimer.`
43			`////`
44			`////`
45			`//// This source file is free software; you can redistribute it`
46			`////`
47			`//// and/or modify it under the terms of the GNU Lesser General`
48			`////`
49			`//// Public License as published by the Free Software Foundation;`
50			`//// either version 2.1 of the License, or (at your option) any`
51			`////`
52			`//// later version.`
53			`////`
54			`////`
55			`////`
56			`//// This source is distributed in the hope that it will be`
57			`////`
58			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
59			`////`
60			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
61			`////`
62			`//// PURPOSE. See the GNU Lesser General Public License for more`
63			`//// details.`
64			`////`
65			`////`
66			`////`
67			`//// You should have received a copy of the GNU Lesser General`
68			`////`
69			`//// Public License along with this source; if not, download it`
70			`////`
71			`//// from http://www.opencores.org/lgpl.shtml`
72			`////`
73			`////`
74			`///////////////////////////////////////////////////////////////////`
75			`static int aes_bfm_wr_error_dinr_calltf(char*user_data)`
76			`{`
77
78			`vpiHandle PRESETn = vpi_handle_by_name("AES_GLADIC_tb.PRESETn", NULL);`
79			`vpiHandle PWDATA = vpi_handle_by_name("AES_GLADIC_tb.PWDATA", NULL);`
80			`vpiHandle PENABLE = vpi_handle_by_name("AES_GLADIC_tb.PENABLE", NULL);`
81			`vpiHandle PSEL = vpi_handle_by_name("AES_GLADIC_tb.PSEL", NULL);`
82			`vpiHandle PWRITE = vpi_handle_by_name("AES_GLADIC_tb.PWRITE", NULL);`
83			`vpiHandle PADDR = vpi_handle_by_name("AES_GLADIC_tb.PADDR", NULL);`
84			`vpiHandle PRDATA = vpi_handle_by_name("AES_GLADIC_tb.PRDATA", NULL);`
85			`vpiHandle PREADY = vpi_handle_by_name("AES_GLADIC_tb.PREADY", NULL);`
86			`vpiHandle PSLVERR = vpi_handle_by_name("AES_GLADIC_tb.PSLVERR", NULL);`
87			`vpiHandle int_ccf = vpi_handle_by_name("AES_GLADIC_tb.int_ccf", NULL);`
88			`vpiHandle int_err = vpi_handle_by_name("AES_GLADIC_tb.int_err", NULL);`
89			`vpiHandle dma_req_wr = vpi_handle_by_name("AES_GLADIC_tb.dma_req_wr", NULL);`
90			`vpiHandle dma_req_rd = vpi_handle_by_name("AES_GLADIC_tb.dma_req_rd", NULL);`
91
92			`v_wr.format=vpiIntVal;`
93
94
95			`std::random_device rd;`
96			`std::uniform_int_distribution<long int> data_in(0,4294967295);`
97
98
99			`v_wr.format=vpiIntVal;`
100			`vpi_get_value(PRESETn, &v_wr);`
101
102
103			`if(type_bfm == AES_WR_ERROR_DINR_ONLY && v_wr.value.integer == 1)`
104			`{`
105
106			`//printf("%i\n",STATE);`
107
108			`switch(STATE)`
109			`{`
110
111			`case IDLE:`
112
113
114			`if(PACKETS_GENERATED >= MAX_ITERATIONS)`
115			`{`
116			`STATE = IDLE;`
117			`type_bfm = 0;`
118
119			`}else`
120			`{`
121			`STATE = WRITE;`
122
123			`counter = 0;`
124
125	12	redbear
126			`v_wr.value.integer = 0;`
127	4	redbear	`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
128
129			`v_wr.value.integer = 0;`
130	12	redbear	`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
131
132			`v_wr.value.integer = 0;`
133	4	redbear	`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
134
135			`v_wr.value.integer = 1;`
136			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
137
138			`v_wr.value.integer = 1;`
139			`vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);`
140	12	redbear
141	4	redbear	`}`
142
143
144
145			`break;`
146
147			`case WRITE:`
148
149	12	redbear
150
151
152
153	4	redbear	`if(counter == 0)`
154			`{`
155
156	12	redbear	`counter++;`
157	4	redbear	`counter_write++;`
158
159			`v_wr.value.integer = 1;`
160			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
161
162
163	12	redbear	`}else if( counter == 1 )`
164			`{`
165	4	redbear
166			`v_wr.value.integer = 0;`
167			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
168
169			`if(counter_write < 9)`
170			`{`
171
172	12	redbear	`v_wr.value.integer = vector_address[counter_write];`
173			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
174	4	redbear
175	12	redbear	`if(vector_address[counter_write] == ADDR_AES_KEYR3 \|\| vector_address[counter_write] == ADDR_AES_IVR3)`
176			`{`
177	4	redbear
178	12	redbear	`a = a \| KEY_FIPS_NOT_DERIVATED[0];`
179			`a = a << 8;`
180			`a = a \| KEY_FIPS_NOT_DERIVATED[1];`
181			`a = a << 8;`
182			`a = a \| KEY_FIPS_NOT_DERIVATED[2];`
183			`a = a << 8;`
184			`a = a \| KEY_FIPS_NOT_DERIVATED[3];`
185			`v_wr.value.integer = a;`
186			`}`
187	4	redbear
188	12	redbear	`if(vector_address[counter_write] == ADDR_AES_KEYR2 \|\| vector_address[counter_write] == ADDR_AES_IVR2)`
189			`{`
190	4	redbear
191	12	redbear	`b = b \| KEY_FIPS_NOT_DERIVATED[4];`
192			`b = b << 8;`
193			`b = b \| KEY_FIPS_NOT_DERIVATED[5];`
194			`b = b << 8;`
195			`b = b \| KEY_FIPS_NOT_DERIVATED[6];`
196			`b = b << 8;`
197			`b = b \| KEY_FIPS_NOT_DERIVATED[7];`
198			`v_wr.value.integer = b;`
199	4	redbear
200	12	redbear	`}`
201
202			`if(vector_address[counter_write] == ADDR_AES_KEYR1 \|\| vector_address[counter_write] == ADDR_AES_IVR1)`
203			`{`
204			`c = c \| KEY_FIPS_NOT_DERIVATED[8];`
205			`c = c << 8;`
206			`c = c \| KEY_FIPS_NOT_DERIVATED[9];`
207			`c = c << 8;`
208			`c = c \| KEY_FIPS_NOT_DERIVATED[10];`
209			`c = c << 8;`
210			`c = c \| KEY_FIPS_NOT_DERIVATED[11];`
211			`v_wr.value.integer = c;`
212			`}`
213	4	redbear
214
215	12	redbear	`if(vector_address[counter_write] == ADDR_AES_KEYR0 \|\| vector_address[counter_write] == ADDR_AES_IVR0)`
216			`{`
217	4	redbear
218	12	redbear	`d = d \| KEY_FIPS_NOT_DERIVATED[12];`
219			`d = d << 8;`
220			`d = d \| KEY_FIPS_NOT_DERIVATED[13];`
221			`d = d << 8;`
222			`d = d \| KEY_FIPS_NOT_DERIVATED[14];`
223			`d = d << 8;`
224			`d = d \| KEY_FIPS_NOT_DERIVATED[15];`
225			`v_wr.value.integer = d;`
226	4	redbear
227	12	redbear	`}`
228	4	redbear
229	12	redbear	`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
230	4	redbear
231	12	redbear	`a = 0;`
232			`b = 0;`
233			`c = 0;`
234			`d = 0;`
235
236			`}else if(counter_write == 9)//ENABLE CR`
237	4	redbear	`{`
238	12	redbear	`v_wr.value.integer = ADDR_AES_CR;`
239	4	redbear	`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
240
241	12	redbear	`v_wr.value.integer = vector_CR[PACKETS_GENERATED];`
242	4	redbear	`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
243
244	12	redbear	`}else if(counter_write > 9 && counter_write < 14) //WRITE DINR`
245	4	redbear	`{`
246	12	redbear
247			`v_wr.value.integer = ADDR_AES_DINR;`
248			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
249
250	4	redbear	`if(counter_write == 10)`
251			`{`
252	12	redbear	`a = a \| TEXT_FIPS_NOT_DERIVATED[0];`
253	4	redbear	`a = a << 8;`
254	12	redbear	`a = a \| TEXT_FIPS_NOT_DERIVATED[1];`
255	4	redbear	`a = a << 8;`
256	12	redbear	`a = a \| TEXT_FIPS_NOT_DERIVATED[2];`
257	4	redbear	`a = a << 8;`
258	12	redbear	`a = a \| TEXT_FIPS_NOT_DERIVATED[3];`
259	4	redbear	`v_wr.value.integer = a;`
260
261			`}else if(counter_write == 11)`
262			`{`
263	12	redbear	`b = b \| TEXT_FIPS_NOT_DERIVATED[4];`
264	4	redbear	`b = b << 8;`
265	12	redbear	`b = b \| TEXT_FIPS_NOT_DERIVATED[5];`
266	4	redbear	`b = b << 8;`
267	12	redbear	`b = b \| TEXT_FIPS_NOT_DERIVATED[6];`
268	4	redbear	`b = b << 8;`
269	12	redbear	`b = b \| TEXT_FIPS_NOT_DERIVATED[7];`
270	4	redbear	`v_wr.value.integer = b;`
271
272			`}else if(counter_write == 12 )`
273			`{`
274
275	12	redbear	`c = c \| TEXT_FIPS_NOT_DERIVATED[8];`
276	4	redbear	`c = c << 8;`
277	12	redbear	`c = c \| TEXT_FIPS_NOT_DERIVATED[9];`
278	4	redbear	`c = c << 8;`
279	12	redbear	`c = c \| TEXT_FIPS_NOT_DERIVATED[10];`
280	4	redbear	`c = c << 8;`
281	12	redbear	`c = c \| TEXT_FIPS_NOT_DERIVATED[11];`
282	4	redbear	`v_wr.value.integer = c;`
283
284			`}else if(counter_write == 13 )`
285			`{`
286	12	redbear	`d = d \| TEXT_FIPS_NOT_DERIVATED[12];`
287	4	redbear	`d = d << 8;`
288	12	redbear	`d = d \| TEXT_FIPS_NOT_DERIVATED[13];`
289	4	redbear	`d = d << 8;`
290	12	redbear	`d = d \| TEXT_FIPS_NOT_DERIVATED[14];`
291	4	redbear	`d = d << 8;`
292	12	redbear	`d = d \| TEXT_FIPS_NOT_DERIVATED[15];`
293	4	redbear	`v_wr.value.integer = d;`
294
295			`}`
296
297	12	redbear	`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
298	4	redbear
299
300	12	redbear	`a = 0;`
301			`b = 0;`
302			`c = 0;`
303			`d = 0;`
304	4	redbear
305			`}`
306
307	12	redbear	`counter=0;`
308			`}`
309	4	redbear
310
311
312
313			`if(counter_write == 14)`
314			`{`
315			`counter_write = 0;`
316	12	redbear	`STATE = WAIT;`
317	4	redbear	`}`
318
319
320			`break;`
321
322			`case WAIT:`
323
324
325
326
327	12	redbear	`if(counter_wait == 1)`
328	4	redbear	`{`
329
330	12	redbear	`v_wr.value.integer = 1;`
331			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
332
333	4	redbear	`STATE = WRITE_DINR;`
334			`counter_wait=0;`
335	12	redbear	`counter_write = 0;`
336			`counter=1;`
337	4	redbear
338
339			`}else`
340			`{`
341
342			`counter_wait++;`
343
344	12	redbear	`v_wr.value.integer = 0;`
345			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
346
347			`v_wr.value.integer = 0;`
348			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
349
350	4	redbear	`}`
351			`break;`
352
353			`case WRITE_DINR:`
354
355
356	12	redbear
357
358	4	redbear	`if(counter == 0)`
359			`{`
360
361			`counter++;`
362			`counter_write++;`
363
364			`v_wr.value.integer = 1;`
365			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
366
367
368			`}else if(counter == 1)`
369			`{`
370
371			`v_wr.value.integer = 0;`
372			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
373
374	12	redbear	`if(counter_write == 13)//ENABLE CR`
375			`{`
376
377			`v_wr.value.integer =1;`
378			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
379
380			`v_wr.value.integer = ADDR_AES_CR;`
381			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
382
383			`v_wr.value.integer = 0;`
384			`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
385
386			`}else`
387			`{`
388			`v_wr.value.integer = ADDR_AES_DINR;`
389			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
390			`}`
391
392
393	4	redbear	`counter=0;`
394			`}`
395
396
397
398			`if(counter_write == 14)`
399			`{`
400			`STATE = READ_RESULTS;`
401			`counter_write = 0;`
402			`counter_read = 0;`
403	12	redbear	`counter=1;`
404	4	redbear
405			`}`
406
407
408			`break;`
409
410			`case READ_RESULTS:`
411
412
413
414	12	redbear	`v_wr.value.integer = 0;`
415			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
416
417			`v_wr.value.integer = 1;`
418			`vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);`
419
420	4	redbear	`if(counter == 0)`
421			`{`
422
423			`v_wr.value.integer = 1;`
424	12	redbear	`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
425
426	4	redbear	`counter_read++;`
427			`counter++;`
428
429	12	redbear
430	4	redbear	`}else if(counter == 1)`
431			`{`
432
433			`v_wr.value.integer = 0;`
434			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
435
436
437	12	redbear	`if(counter_read <= 9)`
438			`{`
439			`v_wr.value.integer = vector_address[counter_read];`
440			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
441			`}`
442			`else`
443			`{`
444	4	redbear
445
446	12	redbear	`}`
447	4	redbear
448	12	redbear
449
450	4	redbear	`counter=0;`
451
452			`}`
453
454	12	redbear	`if(counter_read == 14)`
455	4	redbear	`{`
456			`STATE = RESET_SR;`
457			`counter_read = 0;`
458			`PACKETS_GENERATED = PACKETS_GENERATED + 1;`
459
460	12	redbear	`counter=1;`
461	4	redbear
462			`}`
463
464			`break;`
465
466			`case RESET_SR:`
467
468
469
470
471			`if(counter == 0)`
472			`{`
473
474			`counter_write++;`
475			`counter++;`
476
477			`v_wr.value.integer = 1;`
478			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
479
480			`}else if(counter == 1)`
481			`{`
482
483			`v_wr.value.integer = 0;`
484			`vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);`
485	12	redbear
486			`v_wr.value.integer = 1;`
487			`vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);`
488
489			`v_wr.value.integer = 1;`
490			`vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);`
491
492			`v_wr.value.integer = 0;`
493			`vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);`
494
495			`v_wr.value.integer = 384;`
496			`vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);`
497
498	4	redbear	`counter=0;`
499
500			`}`

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[/] [apbtoaes128/] [trunk/] [pli/] [bfm_error/] [aes_bfm_wr_error_dinr.h] - Blame information for rev 12