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URL https://opencores.org/ocsvn/apbtoaes128/apbtoaes128/trunk

Subversion Repositories apbtoaes128

[/] [apbtoaes128/] [trunk/] [pli/] [bfm_error/] [aes_bfm_wr_error_doutr.h] - Blame information for rev 12

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1 4 redbear
//////////////////////////////////////////////////////////////////
2
////
3
////
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////    AES CORE BLOCK
5
////
6
////
7
////
8
//// This file is part of the APB to AES128 project
9
////
10
//// http://www.opencores.org/cores/apbtoaes128/
11
////
12
////
13
////
14
//// Description
15
////
16
//// Implementation of APB IP core according to
17
////
18
//// aes128_spec IP core specification document.
19
////
20
////
21
////
22
//// To Do: Things are right here but always all block can suffer changes
23
////
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////
25
////
26
////
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////
28
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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////
30
///////////////////////////////////////////////////////////////// 
31
////
32
////
33
//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
35
////
36
////
37
//// This source file may be used and distributed without
38
////
39
//// restriction provided that this copyright statement is not
40
////
41
//// removed from the file and that any derivative work contains
42
//// the original copyright notice and the associated disclaimer.
43
////
44
////
45
//// This source file is free software; you can redistribute it
46
////
47
//// and/or modify it under the terms of the GNU Lesser General
48
////
49
//// Public License as published by the Free Software Foundation;
50
//// either version 2.1 of the License, or (at your option) any
51
////
52
//// later version.
53
////
54
////
55
////
56
//// This source is distributed in the hope that it will be
57
////
58
//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
60
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
61
////
62
//// PURPOSE. See the GNU Lesser General Public License for more
63
//// details.
64
////
65
////
66
////
67
//// You should have received a copy of the GNU Lesser General
68
////
69
//// Public License along with this source; if not, download it
70
////
71
//// from http://www.opencores.org/lgpl.shtml
72
////
73
////
74
///////////////////////////////////////////////////////////////////
75
static int aes_bfm_wr_error_doutr_calltf(char*user_data)
76
{
77
 
78
        vpiHandle PRESETn = vpi_handle_by_name("AES_GLADIC_tb.PRESETn", NULL);
79
        vpiHandle PWDATA = vpi_handle_by_name("AES_GLADIC_tb.PWDATA", NULL);
80
        vpiHandle PENABLE = vpi_handle_by_name("AES_GLADIC_tb.PENABLE", NULL);
81
        vpiHandle PSEL = vpi_handle_by_name("AES_GLADIC_tb.PSEL", NULL);
82
        vpiHandle PWRITE = vpi_handle_by_name("AES_GLADIC_tb.PWRITE", NULL);
83
        vpiHandle PADDR = vpi_handle_by_name("AES_GLADIC_tb.PADDR", NULL);
84
        vpiHandle PRDATA = vpi_handle_by_name("AES_GLADIC_tb.PRDATA", NULL);
85
        vpiHandle PREADY = vpi_handle_by_name("AES_GLADIC_tb.PREADY", NULL);
86
        vpiHandle PSLVERR = vpi_handle_by_name("AES_GLADIC_tb.PSLVERR", NULL);
87
        vpiHandle int_ccf = vpi_handle_by_name("AES_GLADIC_tb.int_ccf", NULL);
88
        vpiHandle int_err = vpi_handle_by_name("AES_GLADIC_tb.int_err", NULL);
89
        vpiHandle dma_req_wr = vpi_handle_by_name("AES_GLADIC_tb.dma_req_wr", NULL);
90
        vpiHandle dma_req_rd = vpi_handle_by_name("AES_GLADIC_tb.dma_req_rd", NULL);
91
 
92
        v_wr.format=vpiIntVal;
93
 
94
 
95
        std::random_device rd;
96
        std::uniform_int_distribution<long int> data_in(0,4294967295);
97
 
98
 
99
        v_wr.format=vpiIntVal;
100
        vpi_get_value(PRESETn, &v_wr);
101
 
102
 
103
        if(type_bfm == AES_WR_ERROR_DOUTR_ONLY && v_wr.value.integer == 1)
104
        {
105
 
106
                //printf("%i\n",STATE);
107
 
108
                switch(STATE)
109
                {
110
 
111
                        case IDLE:
112
 
113
 
114
                                if(PACKETS_GENERATED >= MAX_ITERATIONS)
115
                                {
116
                                        STATE = IDLE;
117
                                        type_bfm = 0;
118
 
119
                                }else
120
                                {
121
                                        STATE = WRITE;
122
 
123
                                        counter = 0;
124
 
125 12 redbear
                                        v_wr.value.integer = 0;
126 4 redbear
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
127
 
128
                                        v_wr.value.integer = 0;
129
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
130
 
131
                                        v_wr.value.integer = 1;
132
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
133
 
134
                                        v_wr.value.integer = 1;
135
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
136
                                }
137
 
138
 
139
 
140
                        break;
141
 
142
                        case WRITE:
143
 
144
                                if(counter == 0)
145
                                {
146
 
147
                                        counter_write++;
148
                                        counter++;
149
 
150
                                        v_wr.value.integer = 1;
151
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
152
 
153
 
154
                                }else if(counter == 1)
155
                                {
156
 
157
                                        v_wr.value.integer = 0;
158
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
159
 
160
                                        t_wr.type = vpiScaledRealTime;
161
                                        t_wr.real = 0;
162
                                        v_wr.format=vpiIntVal;
163
 
164
                                        if(counter_write < 9)
165
                                        {
166
 
167
                                        v_wr.value.integer = vector_address[counter_write];
168
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
169
 
170
                                                if(FIPS_ENABLE == FIPS)
171
                                                {
172
 
173
                                                        if(vector_address[counter_write] == ADDR_AES_KEYR3 || vector_address[counter_write] == ADDR_AES_IVR3)
174
                                                        {
175
                                                                a = a | KEY_FIPS_NOT_DERIVATED[0];
176
                                                                a = a << 8;
177
                                                                a = a | KEY_FIPS_NOT_DERIVATED[1];
178
                                                                a = a << 8;
179
                                                                a = a | KEY_FIPS_NOT_DERIVATED[2];
180
                                                                a = a << 8;
181
                                                                a = a | KEY_FIPS_NOT_DERIVATED[3];
182
                                                                v_wr.value.integer = a;
183
                                                        }
184
 
185
 
186
                                                        if(vector_address[counter_write] == ADDR_AES_KEYR2 || vector_address[counter_write] == ADDR_AES_IVR2)
187
                                                        {
188
                                                                b = b | KEY_FIPS_NOT_DERIVATED[4];
189
                                                                b = b << 8;
190
                                                                b = b | KEY_FIPS_NOT_DERIVATED[5];
191
                                                                b = b << 8;
192
                                                                b = b | KEY_FIPS_NOT_DERIVATED[6];
193
                                                                b = b << 8;
194
                                                                b = b | KEY_FIPS_NOT_DERIVATED[7];
195
                                                                v_wr.value.integer = b;
196
                                                        }
197
 
198
                                                        if(vector_address[counter_write] == ADDR_AES_KEYR1 || vector_address[counter_write] == ADDR_AES_IVR1)
199
                                                        {
200
 
201
                                                                c = c | KEY_FIPS_NOT_DERIVATED[8];
202
                                                                c = c << 8;
203
                                                                c = c | KEY_FIPS_NOT_DERIVATED[9];
204
                                                                c = c << 8;
205
                                                                c = c | KEY_FIPS_NOT_DERIVATED[10];
206
                                                                c = c << 8;
207
                                                                c = c | KEY_FIPS_NOT_DERIVATED[11];
208
                                                                v_wr.value.integer = c;
209
 
210
                                                        }
211
 
212
                                                        if(vector_address[counter_write] == ADDR_AES_KEYR0 || vector_address[counter_write] == ADDR_AES_IVR0)
213
                                                        {
214
                                                                d = d | KEY_FIPS_NOT_DERIVATED[12];
215
                                                                d = d << 8;
216
                                                                d = d | KEY_FIPS_NOT_DERIVATED[13];
217
                                                                d = d << 8;
218
                                                                d = d | KEY_FIPS_NOT_DERIVATED[14];
219
                                                                d = d << 8;
220
                                                                d = d | KEY_FIPS_NOT_DERIVATED[15];
221
                                                                v_wr.value.integer = d;
222
                                                        }
223
 
224
 
225
 
226
                                                }else if(FIPS_ENABLE == RANDOM_DATA)
227
                                                {
228
                                                        v_wr.value.integer = data_in(rd);
229
                                                }
230
                                                vpi_put_value(PWDATA, &v_wr, &t_wr, vpiTransportDelay);
231
 
232
                                                a = 0;
233
                                                b = 0;
234
                                                c = 0;
235
                                                d = 0;
236
 
237
                                                v_wr.value.integer = 1;
238
                                                vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
239
 
240
 
241
                                        }else if(counter_write == 9)
242
                                        {
243
 
244 12 redbear
                                                v_wr.value.integer = ADDR_AES_CR;
245 4 redbear
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
246
 
247 12 redbear
                                                v_wr.value.integer = vector_CR[PACKETS_GENERATED];
248 4 redbear
                                                vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
249
 
250
                                        }if(counter_write > 9  &&  counter_write < 14) //WRITE DINR
251
                                        {
252
 
253
                                                v_wr.value.integer = ADDR_AES_DINR;
254
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
255
 
256
 
257
                                                if(FIPS_ENABLE == FIPS)
258
                                                {
259
 
260
                                                        if(counter_write == 10)
261
                                                        {
262
                                                                a = a | TEXT_FIPS_DERIVATED[0];
263
                                                                a = a << 8;
264
                                                                a = a | TEXT_FIPS_DERIVATED[1];
265
                                                                a = a << 8;
266
                                                                a = a | TEXT_FIPS_DERIVATED[2];
267
                                                                a = a << 8;
268
                                                                a = a | TEXT_FIPS_DERIVATED[3];
269
                                                                v_wr.value.integer = a;
270
 
271
                                                        }else if(counter_write == 11)
272
                                                        {
273
                                                                b = b | TEXT_FIPS_DERIVATED[4];
274
                                                                b = b << 8;
275
                                                                b = b | TEXT_FIPS_DERIVATED[5];
276
                                                                b = b << 8;
277
                                                                b = b | TEXT_FIPS_DERIVATED[6];
278
                                                                b = b << 8;
279
                                                                b = b | TEXT_FIPS_DERIVATED[7];
280
                                                                v_wr.value.integer = b;
281
 
282
                                                        }else if(counter_write == 12 )
283
                                                        {
284
 
285
                                                                c = c | TEXT_FIPS_DERIVATED[8];
286
                                                                c = c << 8;
287
                                                                c = c | TEXT_FIPS_DERIVATED[9];
288
                                                                c = c << 8;
289
                                                                c = c | TEXT_FIPS_DERIVATED[10];
290
                                                                c = c << 8;
291
                                                                c = c | TEXT_FIPS_DERIVATED[11];
292
                                                                v_wr.value.integer = c;
293
 
294
                                                        }else if(counter_write == 13 )
295
                                                        {
296
                                                                d = d | TEXT_FIPS_DERIVATED[12];
297
                                                                d = d << 8;
298
                                                                d = d | TEXT_FIPS_DERIVATED[13];
299
                                                                d = d << 8;
300
                                                                d = d | TEXT_FIPS_DERIVATED[14];
301
                                                                d = d << 8;
302
                                                                d = d | TEXT_FIPS_DERIVATED[15];
303
                                                                v_wr.value.integer = d;
304
 
305
                                                        }
306
 
307
 
308
                                                }else if(FIPS_ENABLE == RANDOM_DATA)
309
                                                {
310
                                                        v_wr.value.integer = data_in(rd);
311
                                                }
312
 
313
                                                vpi_put_value(PWDATA, &v_wr, &t_wr, vpiTransportDelay);
314
 
315
                                                a = 0;
316
                                                b = 0;
317
                                                c = 0;
318
                                                d = 0;
319
 
320
 
321
                                        }
322
 
323
                                        counter=0;
324
 
325
                                }//ELSE COUNTER
326
 
327
 
328
 
329
                                if(counter_write == 14)
330
                                {
331
                                        STATE =WAIT;
332
                                        counter_write = 0;
333
                                        counter_read  = 0;
334
 
335
                                }
336
 
337
 
338
                        break;
339
 
340
                        case WAIT:
341
 
342
 
343
                                v_wr.value.integer = 0;
344
                                vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
345
 
346
                                v_wr.value.integer = 0;
347
                                vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
348
 
349 12 redbear
                                if(counter_wait == 3)
350 4 redbear
                                {
351
 
352
                                        STATE = READ_DOUTR;
353
                                        counter_wait=0;
354 12 redbear
                                        counter=1;
355 4 redbear
 
356
                                }else
357
                                {
358
 
359 12 redbear
                                        v_wr.value.integer = ADDR_AES_CR;
360
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
361
 
362 4 redbear
                                        counter_wait++;
363
 
364
                                }
365
                        break;
366
 
367
                        case READ_DOUTR:
368
 
369
 
370
                                if(counter == 0)
371
                                {
372
 
373
                                        counter++;
374 12 redbear
                                        counter_read++;
375 4 redbear
 
376
                                        v_wr.value.integer = 1;
377
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
378
 
379
 
380
                                }else if(counter == 1)
381
                                {
382
 
383
                                        v_wr.value.integer = 0;
384
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
385
 
386 12 redbear
 
387
                                        v_wr.value.integer = ADDR_AES_DOUTR;
388
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
389
 
390 4 redbear
                                        counter=0;
391
                                }
392
 
393
 
394
 
395 12 redbear
                                if(counter_read == 4)
396 4 redbear
                                {
397
                                        STATE = READ_RESULTS;
398
                                        counter_write = 0;
399
                                        counter_read  = 0;
400 12 redbear
                                        counter=1;
401 4 redbear
                                }
402
 
403
 
404
                        break;
405
 
406
                        case READ_RESULTS:
407
 
408
 
409
 
410
                                if(counter == 0)
411
                                {
412
 
413
                                        v_wr.value.integer = 1;
414
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
415
 
416
                                        counter_read++;
417
                                        counter++;
418
 
419
                                }else if(counter == 1)
420
                                {
421
 
422
 
423
                                        v_wr.value.integer = 0;
424
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
425
 
426 12 redbear
                                        if(counter_read == 0)
427
                                        {
428
                                                v_wr.value.integer = 1;
429
                                                vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
430 4 redbear
 
431 12 redbear
                                                v_wr.value.integer = ADDR_AES_CR;
432
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
433 4 redbear
 
434 12 redbear
                                                v_wr.value.integer = 0;
435
                                                vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
436 4 redbear
 
437 12 redbear
                                                v_wr.value.integer = 1;
438
                                                vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
439
                                        }else
440
                                        {
441
                                                v_wr.value.integer = 0;
442
                                                vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
443 4 redbear
 
444 12 redbear
                                                v_wr.value.integer = ADDR_AES_SR;
445
                                                vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
446
 
447
 
448
                                        }
449
 
450 4 redbear
                                        counter=0;
451
 
452
                                }
453
 
454 12 redbear
                                if(counter_read == 14)
455 4 redbear
                                {
456 12 redbear
                                        STATE = RESET_SR;
457
                                        counter_write = 0;
458
                                        counter_read  = 0;
459 4 redbear
                                        PACKETS_GENERATED = PACKETS_GENERATED + 1;
460 12 redbear
                                        counter=1;
461 4 redbear
 
462 12 redbear
                                }
463
 
464
                        break;
465
 
466
                        case RESET_SR:
467
 
468
 
469
 
470
 
471
                                if(counter == 0)
472
                                {
473
 
474
                                        counter_write++;
475
                                        counter++;
476
 
477
                                        v_wr.value.integer = 1;
478 4 redbear
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
479
 
480 12 redbear
                                }else if(counter == 1)
481
                                {
482
 
483
                                        v_wr.value.integer = 0;
484
                                        vpi_put_value(PENABLE, &v_wr, NULL, vpiNoDelay);
485
 
486
                                        v_wr.value.integer = 1;
487
                                        vpi_put_value(PWRITE, &v_wr, NULL, vpiNoDelay);
488
 
489
                                        v_wr.value.integer = 1;
490
                                        vpi_put_value(PSEL, &v_wr, NULL, vpiNoDelay);
491
 
492
                                        v_wr.value.integer = 0;
493
                                        vpi_put_value(PADDR, &v_wr, NULL, vpiNoDelay);
494
 
495
                                        v_wr.value.integer = 384;
496
                                        vpi_put_value(PWDATA, &v_wr, NULL, vpiNoDelay);
497
 
498
                                        counter=0;
499
 
500 4 redbear
                                }
501
 
502 12 redbear
                                if(counter_write == 2)
503
                                {
504
                                        STATE =IDLE;
505
                                        counter_write = 0;
506
                                        counter_read  = 0;
507
                                }
508
 
509
 
510
 
511 4 redbear
                        break;
512
                }
513
 
514
 
515
 
516
        }
517
 
518
 
519
        return 0;
520
}

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