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[/] [apbtoaes128/] [trunk/] [rtl/] [aes_ip.v] - Blame information for rev 15

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//////////////////////////////////////////////////////////////////
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////
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////
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////    AES CORE BLOCK
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////
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////
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////
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//// This file is part of the APB to I2C project
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////
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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//// Description
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////
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//// Implementation of APB IP core according to
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////
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//// aes128_spec IP core specification document.
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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////              Julio Cesar 
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////
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///////////////////////////////////////////////////////////////// 
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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//// This source file may be used and distributed without
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////
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//// restriction provided that this copyright statement is not
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////
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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////
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//// This source file is free software; you can redistribute it
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////
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//// and/or modify it under the terms of the GNU Lesser General
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////
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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////
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//// later version.
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////
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////
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////
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//// This source is distributed in the hope that it will be
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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////
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//// Public License along with this source; if not, download it
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////
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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///////////////////////////////////////////////////////////////////
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module aes_ip
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(
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        //OUTPUTS
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        output int_ccf,
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        output int_err,
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        output dma_req_wr,
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        output dma_req_rd,
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        output PREADY,
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        output PSLVERR,
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        output [31:0] PRDATA,
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        //INPUTS
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        input  [ 3:0] PADDR,
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        input  [31:0] PWDATA,
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        input PWRITE,
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        input PENABLE,
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        input PSEL,
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        input PCLK,
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        input PRESETn
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);
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wire [31:0] col_out;
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wire [31:0] key_out;
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wire [31:0] iv_out;
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wire end_aes;
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wire [ 3:0] iv_en;
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wire [ 3:0] iv_sel_rd;
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wire [ 3:0] key_en;
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wire [ 1:0] key_sel_rd;
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wire [ 1:0] data_type;
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wire [ 1:0] addr;
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wire [ 1:0] op_mode;
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wire [ 1:0] aes_mode;
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wire start;
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wire disable_core;
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wire write_en;
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wire read_en;
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wire first_block;
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//wire pwdata_host_interface;
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assign PREADY = 1'b1;
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assign PSLVERR = 1'b0;
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//assign pwdata_host_interface = PWDATA[12:0];
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host_interface HOST_INTERFACE
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(
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        .key_en       ( key_en       ),
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        .col_addr     ( addr         ),
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        .col_wr_en    ( write_en     ),
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        .col_rd_en    ( read_en      ),
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        .key_sel      ( key_sel_rd   ),
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        .iv_en        ( iv_en        ),
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        .iv_sel       ( iv_sel_rd    ),
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        .int_ccf      ( int_ccf      ),
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        .int_err      ( int_err      ),
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        .chmod        ( aes_mode     ),
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        .mode         ( op_mode      ),
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        .data_type    ( data_type    ),
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        .disable_core ( disable_core ),
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        .first_block  ( first_block  ),
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        .dma_req_wr   ( dma_req_wr   ),
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        .dma_req_rd   ( dma_req_rd   ),
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        .start_core   ( start        ),
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        .PRDATA       ( PRDATA       ),
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        .PADDR        ( PADDR        ),
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        .PWDATA       ( PWDATA[12:0] ),
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        .PWRITE       ( PWRITE       ),
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        .PENABLE      ( PENABLE      ),
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        .PSEL         ( PSEL         ),
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        .PCLK         ( PCLK         ),
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        .PRESETn      ( PRESETn      ),
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        .key_bus      ( key_out      ),
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        .col_bus      ( col_out      ),
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        .iv_bus       ( iv_out       ),
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        .ccf_set      ( end_aes      )
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);
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aes_core AES_CORE
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(
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        .col_out      ( col_out      ),
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        .key_out      ( key_out      ),
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        .iv_out       ( iv_out       ),
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        .end_aes      ( end_aes      ),
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        .bus_in       ( PWDATA       ),
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        .iv_en        ( iv_en        ),
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        .iv_sel_rd    ( iv_sel_rd    ),
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        .key_en       ( key_en       ),
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        .key_sel_rd   ( key_sel_rd   ),
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        .data_type    ( data_type    ),
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        .addr         ( addr         ),
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        .op_mode      ( op_mode      ),
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        .aes_mode     ( aes_mode     ),
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        .start        ( start        ),
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        .disable_core ( disable_core ),
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        .write_en     ( write_en     ),
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        .read_en      ( read_en      ),
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        .first_block  ( first_block  ),
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        .rst_n        ( PRESETn      ),
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        .clk          ( PCLK         )
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);
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endmodule

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