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[/] [apbtoaes128/] [trunk/] [rtl/] [control_unit.v] - Blame information for rev 9

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1 2 redbear
//////////////////////////////////////////////////////////////////
2
////
3
////
4
////    AES CORE BLOCK
5
////
6
////
7
////
8 7 redbear
//// This file is part of the APB to I2C project
9 2 redbear
////
10 7 redbear
//// http://www.opencores.org/cores/apbi2c/
11 2 redbear
////
12
////
13
////
14
//// Description
15
////
16
//// Implementation of APB IP core according to
17
////
18
//// aes128_spec IP core specification document.
19
////
20
////
21
////
22
//// To Do: Things are right here but always all block can suffer changes
23
////
24
////
25
////
26
////
27
////
28
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
29
////              Julio Cesar 
30
////
31
///////////////////////////////////////////////////////////////// 
32
////
33
////
34
//// Copyright (C) 2009 Authors and OPENCORES.ORG
35
////
36
////
37
////
38
//// This source file may be used and distributed without
39
////
40
//// restriction provided that this copyright statement is not
41
////
42
//// removed from the file and that any derivative work contains
43
//// the original copyright notice and the associated disclaimer.
44
////
45
////
46
//// This source file is free software; you can redistribute it
47
////
48
//// and/or modify it under the terms of the GNU Lesser General
49
////
50
//// Public License as published by the Free Software Foundation;
51
//// either version 2.1 of the License, or (at your option) any
52
////
53
//// later version.
54
////
55
////
56
////
57
//// This source is distributed in the hope that it will be
58
////
59
//// useful, but WITHOUT ANY WARRANTY; without even the implied
60
////
61
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
62
////
63
//// PURPOSE. See the GNU Lesser General Public License for more
64
//// details.
65
////
66
////
67
////
68
//// You should have received a copy of the GNU Lesser General
69
////
70
//// Public License along with this source; if not, download it
71
////
72
//// from http://www.opencores.org/lgpl.shtml
73
////
74
////
75
///////////////////////////////////////////////////////////////////
76
module control_unit
77
(
78
        output reg [ 2:0] sbox_sel,
79
        output reg [ 1:0] rk_sel,
80
        output reg [ 1:0] key_out_sel,
81
        output reg [ 1:0] col_sel,
82
        output reg [ 3:0] key_en,
83
        output reg [ 3:0] col_en,
84
        output     [ 3:0] round,
85
        output reg bypass_rk,
86
        output reg bypass_key_en,
87
        output reg key_sel,
88
        output reg iv_cnt_en,
89
        output reg iv_cnt_sel,
90
        output reg key_derivation_en,
91 7 redbear
        output end_comp,
92 2 redbear
        output key_init,
93
        output key_gen,
94
        output mode_ctr,
95
        output mode_cbc,
96
        output last_round,
97
  output encrypt_decrypt,
98
        input [1:0] operation_mode,
99
        input [1:0] aes_mode,
100
        input start,
101
        input disable_core,
102
        input clk,
103
        input rst_n
104
);
105
//`include "include/host_interface.vh"
106
//`include "include/control_unit_params.vh"
107
 
108
//=====================================================================================
109
// Memory Mapped Registers Address
110
//=====================================================================================
111
localparam AES_CR    = 4'd00;
112
localparam AES_SR    = 4'd01;
113
localparam AES_DINR  = 4'd02;
114
localparam AES_DOUTR = 4'd03;
115
localparam AES_KEYR0 = 4'd04;
116
localparam AES_KEYR1 = 4'd05;
117
localparam AES_KEYR2 = 4'd06;
118
localparam AES_KEYR3 = 4'd07;
119
localparam AES_IVR0  = 4'd08;
120
localparam AES_IVR1  = 4'd09;
121
localparam AES_IVR2  = 4'd10;
122
localparam AES_IVR3  = 4'd11;
123
 
124
//=============================================================================
125
// Operation Modes
126
//=============================================================================
127
localparam ENCRYPTION     = 2'b00;
128
localparam KEY_DERIVATION = 2'b01;
129
localparam DECRYPTION     = 2'b10;
130
localparam DECRYP_W_DERIV = 2'b11;
131
 
132
//=============================================================================
133
// AES Modes
134
//=============================================================================
135
localparam ECB = 2'b00;
136
localparam CBC = 2'b01;
137
localparam CTR = 2'b10;
138
 
139
//=============================================================================
140
// SBOX SEL
141
//=============================================================================
142
localparam COL_0 = 3'b000;
143
localparam COL_1 = 3'b001;
144
localparam COL_2 = 3'b010;
145
localparam COL_3 = 3'b011;
146
localparam G_FUNCTION = 3'b100;
147
 
148
//=============================================================================
149
// RK_SEL
150
//=============================================================================
151
localparam COL        = 2'b00;
152
localparam MIXCOL_IN  = 2'b01;
153
localparam MIXCOL_OUT = 2'b10;
154
 
155
//=============================================================================
156
// KEY_OUT_SEL
157
//=============================================================================
158
localparam KEY_0 = 2'b00;
159
localparam KEY_1 = 2'b01;
160
localparam KEY_2 = 2'b10;
161
localparam KEY_3 = 2'b11;
162
 
163
//=============================================================================
164
// COL_SEL
165
//=============================================================================
166
localparam SHIFT_ROWS = 2'b00;
167
localparam ADD_RK_OUT = 2'b01;
168
localparam INPUT      = 2'b10;
169
 
170
//=============================================================================
171
// KEY_SEL
172
//=============================================================================
173
localparam KEY_HOST = 1'b0;
174
localparam KEY_OUT  = 1'b1;
175
 
176
//=============================================================================
177
// KEY_EN
178
//=============================================================================
179
localparam KEY_DIS  = 4'b0000;
180
localparam EN_KEY_0 = 4'b0001;
181
localparam EN_KEY_1 = 4'b0010;
182
localparam EN_KEY_2 = 4'b0100;
183
localparam EN_KEY_3 = 4'b1000;
184
localparam KEY_ALL  = 4'b1111;
185
 
186
//=============================================================================
187
// COL_EN
188
//=============================================================================
189
localparam COL_DIS  = 4'b0000;
190
localparam EN_COL_0 = 4'b0001;
191
localparam EN_COL_1 = 4'b0010;
192
localparam EN_COL_2 = 4'b0100;
193
localparam EN_COL_3 = 4'b1000;
194
localparam COL_ALL  = 4'b1111;
195
 
196
//=============================================================================
197
// IV_CNT_SEL
198
//=============================================================================
199
localparam IV_CNT = 1'b1;
200
localparam IV_BUS = 1'b0;
201
 
202
//=============================================================================
203
// ENABLES
204
//=============================================================================
205
localparam ENABLE = 1'b1;
206
localparam DISABLE = 1'b0;
207
 
208
localparam NUMBER_ROUND      = 4'd10;
209
localparam NUMBER_ROUND_INC  = 4'd11;
210
localparam INITIAL_ROUND     = 4'd00;
211
 
212
//=============================================================================
213
// FSM STATES
214
//=============================================================================
215
localparam IDLE        = 4'd00;
216
localparam ROUND0_COL0 = 4'd01;
217
localparam ROUND0_COL1 = 4'd02;
218
localparam ROUND0_COL2 = 4'd03;
219
localparam ROUND0_COL3 = 4'd04;
220
localparam ROUND_KEY0  = 4'd05;
221
localparam ROUND_COL0  = 4'd06;
222
localparam ROUND_COL1  = 4'd07;
223
localparam ROUND_COL2  = 4'd08;
224
localparam ROUND_COL3  = 4'd09;
225
localparam READY       = 4'd10;
226
localparam GEN_KEY0    = 4'd11;
227
localparam GEN_KEY1    = 4'd12;
228
localparam GEN_KEY2    = 4'd13;
229
localparam GEN_KEY3    = 4'd14;
230
localparam NOP         = 4'd15;
231
 
232
reg [3:0] state, next_state;
233
reg [3:0] rd_count;
234
 
235
reg rd_count_en;
236 7 redbear
//reg end_aes_pp1, end_aes_pp2;
237 2 redbear
wire op_key_derivation;
238
wire first_round;
239
wire [1:0] op_mode;
240 7 redbear
wire enc_dec;
241 2 redbear
 
242
// State Flops Definition
243
always @(posedge clk, negedge rst_n)
244
        begin
245
                if(!rst_n)
246
                        state <= IDLE;
247
                else
248
                        if(disable_core)
249
                                state <= IDLE;
250
                        else
251
                                state <= next_state;
252
        end
253
 
254 9 redbear
assign encrypt_decrypt = (op_mode == ENCRYPTION || op_mode == KEY_DERIVATION || state == GEN_KEY0
255
                          ||   state == GEN_KEY1       ||state == GEN_KEY2   ||   state == GEN_KEY3       );
256 2 redbear
 
257
assign enc_dec = encrypt_decrypt | mode_ctr;
258
assign key_gen = (state == ROUND_KEY0);
259
 
260
assign op_key_derivation = (op_mode == KEY_DERIVATION);
261
 
262
assign mode_ctr = (aes_mode == CTR);
263
assign mode_cbc = (aes_mode == CBC);
264
 
265
assign key_init = start;
266
 
267
assign op_mode = (mode_ctr) ? ENCRYPTION : operation_mode;
268
 
269
// Next State Logic
270
always @(*)
271
        begin
272
                next_state = state;
273
                case(state)
274
                        IDLE:
275
                                begin
276
                                        if(!start)
277
                                                next_state = IDLE;
278
                                        else
279
                                                case(op_mode)
280
                                                        ENCRYPTION    : next_state = ROUND0_COL0;
281
                                                        DECRYPTION    : next_state = ROUND0_COL3;
282
                                                        KEY_DERIVATION: next_state = GEN_KEY0;
283
                                                        DECRYP_W_DERIV: next_state = GEN_KEY0;
284
                                                        default       : next_state = IDLE;
285
                                                endcase
286
                                end
287
                        ROUND0_COL0:
288
                                begin
289
                                        next_state = (enc_dec) ? ROUND0_COL1 : ROUND_KEY0;
290
                                end
291
                        ROUND0_COL1:
292
                                begin
293
                                        next_state = (enc_dec) ? ROUND0_COL2 : ROUND0_COL0;
294
                                end
295
                        ROUND0_COL2:
296
                                begin
297
                                        next_state = (enc_dec) ? ROUND0_COL3 : ROUND0_COL1;
298
                                end
299
                        ROUND0_COL3:
300
                                begin
301
                                        next_state = (enc_dec) ? ROUND_KEY0 : ROUND0_COL2;
302
                                end
303
                        ROUND_KEY0 :
304
                                begin
305
                                        if(!first_round)
306
                                                begin
307
                                                        next_state = (last_round) ? READY : NOP;
308
                                                end
309
                                        else
310
                                                begin
311
                                                        next_state = (enc_dec) ? ROUND_COL0 : ROUND_COL3;
312
                                                end
313
                                end
314
                        NOP        :
315
                                begin
316
                                        next_state = (enc_dec) ? ROUND_COL0 : ROUND_COL3;
317
                                end
318
                        ROUND_COL0 :
319
                                begin
320
                                        next_state = (enc_dec) ? ROUND_COL1 : ROUND_KEY0;
321
                                end
322
                        ROUND_COL1 :
323
                                begin
324
                                        next_state = (enc_dec) ? ROUND_COL2 : ROUND_COL0;
325
                                end
326
                        ROUND_COL2 :
327
                                begin
328
                                        next_state = (enc_dec) ? ROUND_COL3 : ROUND_COL1;
329
                                end
330
                        ROUND_COL3 :
331
                                begin
332
                                        if(last_round && enc_dec)
333
                                                next_state = READY;
334
                                        else
335
                                        next_state = (enc_dec) ? ROUND_KEY0 : ROUND_COL2;
336
                                end
337
                        GEN_KEY0   :
338
                                begin
339
                                        next_state = GEN_KEY1;
340
                                end
341
                        GEN_KEY1   :
342
                                begin
343
                                        next_state = GEN_KEY2;
344
                                end
345
                        GEN_KEY2   :
346
                                begin
347
                                        next_state = GEN_KEY3;
348
                                end
349
                        GEN_KEY3   :
350
                                begin
351
                                        if(last_round)
352
                                                next_state = (op_key_derivation) ? READY : ROUND0_COL3;
353
                                        else
354
                                                next_state = GEN_KEY0;
355
                                end
356
                        READY      :
357
                                begin
358
                                        next_state = IDLE;
359
                                end
360
                endcase
361
        end
362
 
363
 
364
// Output Logic
365 7 redbear
assign end_comp = (state == READY)?ENABLE:DISABLE;
366
 
367
/*
368
always @(posedge clk, negedge rst_n)
369
begin
370
                if(!rst_n)
371
                begin
372
                        end_aes_pp1 <= 1'b0;
373
                        end_aes_pp2 <= 1'b0;
374
                        end_comp <= 1'b0;
375
                end
376
                else
377
                        if(state == READY)
378
                        begin
379
                                end_aes_pp1 <= ENABLE;
380
                                //end_aes_pp2 <= end_aes_pp1;
381
                                end_comp <= end_aes_pp1 ;
382
                        end
383
                        else
384
                        begin
385
                                end_aes_pp1 <= DISABLE;
386
                                //end_aes_pp2 <= end_aes_pp1;
387
                                end_comp <= end_aes_pp1 ;
388
                        end
389
 
390
end
391
*/
392 2 redbear
always @(*)
393
        begin
394
                sbox_sel = COL_0;
395
                rk_sel = COL;
396
                bypass_rk = DISABLE;
397
                key_out_sel = KEY_0;
398
                col_sel = INPUT;
399
                key_sel = KEY_HOST;
400
                key_en = KEY_DIS;
401
                col_en = COL_DIS;
402
                rd_count_en = DISABLE;
403
                iv_cnt_en = DISABLE;
404
                iv_cnt_sel = IV_BUS;
405
                bypass_key_en = DISABLE;
406
                key_derivation_en = DISABLE;
407 7 redbear
                //end_comp = DISABLE;
408 2 redbear
                case(state)
409
                        ROUND0_COL0:
410
                                begin
411
                                        sbox_sel = COL_0;
412
                                        rk_sel   = COL;
413
                                        bypass_rk = ENABLE;
414
                                        bypass_key_en = ENABLE;
415
                                        key_out_sel = KEY_0;
416
                                        col_sel = (enc_dec) ? ADD_RK_OUT : SHIFT_ROWS;
417
                                        col_en =  (enc_dec) ? EN_COL_0 : COL_ALL;
418
                                end
419
                        ROUND0_COL1:
420
                                begin
421
                                        sbox_sel = COL_1;
422
                                        rk_sel   = COL;
423
                                        bypass_rk = ENABLE;
424
                                        bypass_key_en = ENABLE;
425
                                        key_out_sel = KEY_1;
426
                                        col_sel = ADD_RK_OUT;
427
                                        col_en = EN_COL_1;
428
                                        if(!enc_dec)
429
                                                begin
430
                                                        key_sel = KEY_OUT;
431
                                                        key_en =  EN_KEY_1;
432
                                                end
433
                                end
434
                        ROUND0_COL2:
435
                                begin
436
                                        sbox_sel = COL_2;
437
                                        rk_sel   = COL;
438
                                        bypass_rk = ENABLE;
439
                                        bypass_key_en = ENABLE;
440
                                        key_out_sel = KEY_2;
441
                                        col_sel = ADD_RK_OUT;
442
                                        col_en = EN_COL_2;
443
                                        if(!enc_dec)
444
                                                begin
445
                                                        key_sel = KEY_OUT;
446
                                                        key_en =  EN_KEY_2;
447
                                                end
448
                                end
449
                        ROUND0_COL3:
450
                                begin
451
                                        sbox_sel = COL_3;
452
                                        rk_sel   = COL;
453
                                        bypass_key_en = ENABLE;
454
                                        key_out_sel = KEY_3;
455
                                        col_sel = (enc_dec) ? SHIFT_ROWS : ADD_RK_OUT;
456
                                        col_en =  (enc_dec) ? COL_ALL : EN_COL_3;
457
                                        bypass_rk = ENABLE;
458
                                        if(!enc_dec)
459 9 redbear
                                        begin
460 2 redbear
                                                        key_sel = KEY_OUT;
461
                                                        key_en =  EN_KEY_3;
462 9 redbear
                                        end
463 2 redbear
                                end
464
                        ROUND_KEY0:
465
                                begin
466
                                        sbox_sel = G_FUNCTION;
467
                                        key_sel = KEY_OUT;
468
                                        key_en = EN_KEY_0;
469
                                        rd_count_en = ENABLE;
470
                                end
471
                        ROUND_COL0:
472
                                begin
473
                                        sbox_sel = COL_0;
474
                                        rk_sel = (last_round) ? MIXCOL_IN : MIXCOL_OUT;
475
                                        key_out_sel = KEY_0;
476
                                        key_sel = KEY_OUT;
477 9 redbear
 
478 2 redbear
                                        if(enc_dec)
479
                                                key_en = EN_KEY_1;
480
                                        if((mode_cbc && last_round && !enc_dec) || (mode_ctr && last_round))
481
                                                col_sel = INPUT;
482
                                        else
483
                                                begin
484
                                                        if(!enc_dec)
485
                                                                col_sel = (last_round) ? ADD_RK_OUT : SHIFT_ROWS;
486
                                                        else
487
                                                                col_sel = ADD_RK_OUT;
488
                                                end
489
                                        if(enc_dec)
490
                                                col_en = EN_COL_0;
491
                                        else
492
                                                col_en = (last_round) ? EN_COL_0 : COL_ALL;
493
                                end
494
                        ROUND_COL1:
495
                                begin
496
                                        sbox_sel = COL_1;
497
                                        rk_sel   = (last_round) ? MIXCOL_IN : MIXCOL_OUT;
498
                                        key_out_sel = KEY_1;
499
                                        key_sel = KEY_OUT;
500
                                        if(enc_dec)
501
                                                key_en = EN_KEY_2;
502
                                        else
503
                                                key_en = EN_KEY_1;
504
                                        if((mode_cbc && last_round && !enc_dec) || (mode_ctr && last_round))
505
                                                col_sel = INPUT;
506
                                        else
507
                                                col_sel = ADD_RK_OUT;
508
                                        col_en = EN_COL_1;
509
                                end
510
                        ROUND_COL2:
511
                                begin
512
                                        sbox_sel = COL_2;
513
                                        rk_sel   = (last_round) ? MIXCOL_IN : MIXCOL_OUT;
514
                                        key_out_sel = KEY_2;
515
                                        key_sel = KEY_OUT;
516
                                        if(enc_dec)
517
                                                key_en = EN_KEY_3;
518
                                        else
519
                                                key_en = EN_KEY_2;
520
                                        if((mode_cbc && last_round && !enc_dec) || (mode_ctr && last_round))
521
                                                col_sel = INPUT;
522
                                        else
523
                                                col_sel = ADD_RK_OUT;
524
                                        col_en = EN_COL_2;
525
                                end
526
                        ROUND_COL3:
527
                                begin
528
                                        sbox_sel = COL_3;
529
                                        rk_sel   = (last_round) ? MIXCOL_IN : MIXCOL_OUT;
530
                                        key_out_sel = KEY_3;
531
                                        key_sel = KEY_OUT;
532
                                        if(!enc_dec)
533
                                                key_en = EN_KEY_3;
534
                                        if((mode_cbc && last_round && !enc_dec) || (mode_ctr && last_round))
535
                                                col_sel = INPUT;
536
                                        else
537
                                                begin
538
                                                        if(enc_dec)
539
                                                                col_sel = (last_round) ? ADD_RK_OUT : SHIFT_ROWS;
540
                                                        else
541
                                                                col_sel = ADD_RK_OUT;
542
                                                end
543
                                        if(enc_dec)
544
                                                col_en = (last_round) ? EN_COL_3 : COL_ALL;
545
                                        else
546
                                                col_en = EN_COL_3;
547
                                        if(mode_ctr && last_round)
548
                                                begin
549
                                                        iv_cnt_en = ENABLE;
550
                                                        iv_cnt_sel = IV_CNT;
551
                                                end
552
                                end
553
                        GEN_KEY0:
554
                                begin
555
                                        sbox_sel = G_FUNCTION;
556
                                        rd_count_en = ENABLE;
557
                                end
558
                        GEN_KEY1:
559
                                begin
560
                                        key_en = EN_KEY_1 | EN_KEY_0; //Enable key 0 AND key 1
561
                                        key_sel = KEY_OUT;
562
                                        bypass_key_en = ENABLE;
563
                                end
564
                        GEN_KEY2:
565
                                begin
566
                                        key_en = EN_KEY_2;
567
                                        key_sel = KEY_OUT;
568
                                        bypass_key_en = ENABLE;
569
                                end
570
                        GEN_KEY3:
571
                                begin
572
                                        key_en = EN_KEY_3;
573
                                        key_sel = KEY_OUT;
574
                                        bypass_key_en = ENABLE;
575
                                end
576
                        READY:
577
                                begin
578 7 redbear
                                        //end_comp = ENABLE;
579 2 redbear
                                        if(op_mode == KEY_DERIVATION)
580
                                                key_derivation_en = ENABLE;
581
                                end
582
                endcase
583
        end
584
 
585
// Round Counter
586
always @(posedge clk, negedge rst_n)
587
        begin
588
                if(!rst_n)
589
                        rd_count <= INITIAL_ROUND;
590
                else
591
                        if(state == IDLE || (state == GEN_KEY3 && last_round))
592
                                rd_count <= INITIAL_ROUND;
593
                        else
594
                                if(rd_count_en)
595
                                        rd_count <= rd_count + 1'b1;
596
        end
597
 
598
assign round = rd_count;
599
assign first_round = (rd_count == INITIAL_ROUND);
600
assign last_round  = (rd_count == NUMBER_ROUND || rd_count == NUMBER_ROUND_INC);
601
 
602
endmodule

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