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[/] [apbtoaes128/] [trunk/] [rtl/] [host_interface.v] - Blame information for rev 12

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1 2 redbear
//////////////////////////////////////////////////////////////////
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////
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////
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////    AES CORE BLOCK
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////
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////
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////
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//// This file is part of the APB to I2C project
9 2 redbear
////
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//// http://www.opencores.org/cores/apbi2c/
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////
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////
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////
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//// Description
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////
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//// Implementation of APB IP core according to
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////
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//// aes128_spec IP core specification document.
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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////              Julio Cesar 
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////
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///////////////////////////////////////////////////////////////// 
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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//// This source file may be used and distributed without
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////
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//// restriction provided that this copyright statement is not
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////
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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////
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//// This source file is free software; you can redistribute it
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////
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//// and/or modify it under the terms of the GNU Lesser General
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////
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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////
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//// later version.
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////
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////
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////
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//// This source is distributed in the hope that it will be
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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////
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//// Public License along with this source; if not, download it
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////
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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///////////////////////////////////////////////////////////////////
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module host_interface
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(
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        // OUTPUTS
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        output [3:0] key_en,
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        output [1:0] col_addr,
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        output [1:0] chmod,
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        output [1:0] mode,
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        output [1:0] data_type,
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        output col_wr_en,
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        output col_rd_en,
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        output [1:0] key_sel,
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        output [3:0] iv_en,
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        output [3:0] iv_sel,
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        output int_ccf,
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        output int_err,
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        output disable_core,
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        output reg first_block,
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        output dma_req_wr,
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        output dma_req_rd,
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        output reg start_core,
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        output [31:0] PRDATA,
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        //INPUTS
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        input [3:0] PADDR,
99 7 redbear
        input [12:0] PWDATA,
100 2 redbear
        input PWRITE,
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        input PENABLE,
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        input PSEL,
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        input PCLK,
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        input PRESETn,
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        input [31:0] key_bus,
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        input [31:0] col_bus,
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        input [31:0] iv_bus,
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        input ccf_set
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);
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//`include "include/host_interface.vh"
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//=====================================================================================
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// Memory Mapped Registers Address
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//=====================================================================================
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localparam AES_CR    = 4'd00;
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localparam AES_SR    = 4'd01;
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localparam AES_DINR  = 4'd02;
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localparam AES_DOUTR = 4'd03;
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localparam AES_KEYR0 = 4'd04;
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localparam AES_KEYR1 = 4'd05;
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localparam AES_KEYR2 = 4'd06;
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localparam AES_KEYR3 = 4'd07;
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localparam AES_IVR0  = 4'd08;
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localparam AES_IVR1  = 4'd09;
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localparam AES_IVR2  = 4'd10;
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localparam AES_IVR3  = 4'd11;
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//=============================================================================
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// Operation Modes
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//=============================================================================
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localparam ENCRYPTION     = 2'b00;
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localparam KEY_DERIVATION = 2'b01;
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localparam DECRYPTION     = 2'b10;
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localparam DECRYP_W_DERIV = 2'b11;
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//=============================================================================
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// AES Modes
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//=============================================================================
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localparam ECB = 2'b00;
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localparam CBC = 2'b01;
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localparam CTR = 2'b10;
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144
//=============================================================================
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// Resets Values
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//=============================================================================
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localparam AES_CR_RESET = 13'd0;
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localparam AES_SR_RESET =  3'd0;
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150
//=============================================================================
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// Enable Value (Active High)
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//=============================================================================
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localparam ENABLE  = 1'b1;
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localparam DISABLE = 1'b0;
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//=============================================================================
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// FSM STATES
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//=============================================================================
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localparam IDLE   = 3'd0;
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localparam INPUT  = 3'd1;
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localparam START  = 3'd2;
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localparam WAIT   = 3'd3;
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localparam OUTPUT = 3'd4;
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wire [31:0] bus_out;
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reg [31:0] bus_out_mux;
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reg cnt_en;
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reg enable_clear;
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reg access_permission;
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reg first_block_set;
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reg first_block_clear;
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wire [1:0] mode_in;
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wire [1:0] chmod_in;
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wire write_en;
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wire read_en;
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wire dma_out_en;
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wire dma_in_en;
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wire err_ie;
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wire ccf_ie;
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wire errc;
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wire ccfc;
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wire aes_cr_wr_en;
183 7 redbear
//wire aes_sr_wr_en;
184 2 redbear
wire wr_err_en;
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wire rd_err_en;
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wire write_completed;
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wire read_completed;
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wire key_deriv;
189
 
190
 
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reg [10:0] aes_cr;
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reg wr_err;
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reg rd_err;
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reg ccf;
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reg [2:0] state, next_state;
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reg [1:0] cnt;
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reg dma_req;
198 7 redbear
wire enable;
199 2 redbear
 
200
// Write and read enable signals
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assign write_en = PSEL & PENABLE & PWRITE;
202 10 redbear
assign read_en  = (PSEL & ~PWRITE)?1'b1:1'b0;
203 2 redbear
 
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// Configuration Register Logic
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assign dma_out_en = aes_cr[10];
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assign dma_in_en  = aes_cr[9];
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assign err_ie     = aes_cr[8];
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assign ccf_ie     = aes_cr[7];
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assign errc       = PWDATA[8];
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assign ccfc       = PWDATA[7];
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assign chmod      = aes_cr[6:5];
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assign mode       = aes_cr[4:3];
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assign data_type  = aes_cr[2:1];
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assign enable     = aes_cr[0];
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216
assign aes_cr_wr_en = (PADDR == AES_CR) & write_en;
217
assign mode_in  = PWDATA[4:3];
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assign chmod_in = PWDATA[6:5];
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220
always @(posedge PCLK, negedge PRESETn)
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        begin
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                if(!PRESETn)
223 7 redbear
                        aes_cr <= AES_CR_RESET[10:0];
224 2 redbear
                else
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                        begin
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                                if(enable_clear)
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                                        aes_cr[0] <= 1'b0;
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                                else
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                                        if(aes_cr_wr_en)
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                                                aes_cr[0] <= PWDATA[0];
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232
                                if(aes_cr_wr_en && access_permission)
233
                                        begin
234
                                                aes_cr[2:1] <= PWDATA[2:1];
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                                                if(mode_in == DECRYP_W_DERIV && chmod_in == CTR)
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                                                        aes_cr[4:3] <= DECRYPTION;
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                                                else
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                                                        aes_cr[4:3] <= mode_in;
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                                                aes_cr[ 6:5] <= PWDATA[6:5];
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                                                aes_cr[10:7] <= PWDATA[12:9];
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                                        end
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                        end
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        end
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// Status Register Logic
246 7 redbear
//assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;
247 2 redbear
 
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always @(posedge PCLK, negedge PRESETn)
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        begin
250
                if(!PRESETn)
251 7 redbear
                begin
252 2 redbear
                        {wr_err, rd_err, ccf} <= AES_SR_RESET;
253 7 redbear
 
254
                end
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                else
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                        begin
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                                // Write Error Flag
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                                if(wr_err_en)
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                                        wr_err <= 1'b1;
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                                else
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                                        if(errc && aes_cr_wr_en && access_permission)
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                                                wr_err <= 1'b0;
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                                //Read Error Flag
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                                if(rd_err_en)
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                                        rd_err <= 1'b1;
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                                else
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                                        if(errc && aes_cr_wr_en && access_permission)
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                                                rd_err <= 1'b0;
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                                // Computation Complete Flag
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                                if(ccf_set)
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                                        ccf <= 1'b1;
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                                else
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                                        if(ccfc && aes_cr_wr_en )//&& access_permission)
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                                                ccf <= 1'b0;
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                        end
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        end
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// Interruption on erros Signals
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assign int_ccf = ccf_ie & ccf_set;
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assign int_err = (wr_err_en | rd_err_en) & err_ie;
282
 
283
// Key Signals Decoding
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assign key_en = (4'b1000 >> PADDR[1:0]) & {4{(~PADDR[3] & PADDR[2] & access_permission & write_en)}};
285
assign key_sel = ~PADDR[1:0] & {2{(PADDR[2] & access_permission)}};
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287
// IV Signals Decoding
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assign iv_sel = (4'b1000 >> PADDR[1:0]) & {4{(PADDR[3] & ~PADDR[2] & access_permission)}};
289
assign iv_en = iv_sel & {4{write_en}};
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// State Register
292
always @(posedge PCLK, negedge PRESETn)
293
        begin
294
                if(!PRESETn)
295
                        state <= IDLE;
296
                else
297
                        if(!enable)
298
                                state <= IDLE;
299
                        else
300
                                state <= next_state;
301
        end
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303
assign write_completed = (cnt == 2'b11);
304
assign read_completed  = (cnt == 2'b11);
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assign key_deriv = (mode == KEY_DERIVATION);
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// Next State Logic
308
always @(*)
309
        begin
310
                next_state = state;
311
                case(state)
312
                IDLE  :
313
                        begin
314
                                if(enable)
315
                                        next_state = (key_deriv) ? START : INPUT;
316
                        end
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                INPUT :
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                        next_state = (write_completed && cnt_en) ? START : INPUT;
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                START :
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                        next_state = WAIT;
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                WAIT  :
322
                        begin
323
                                if(ccf_set)
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                                        next_state = (key_deriv) ? IDLE : OUTPUT;
325
                        end
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                OUTPUT:
327
                        next_state = (read_completed && cnt_en) ? INPUT : OUTPUT;
328
                endcase
329
        end
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// Output Logic
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assign disable_core = ~enable;
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always @(*)
335
        begin
336
                access_permission = DISABLE;
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                start_core = DISABLE;
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                cnt_en = DISABLE;
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                enable_clear = DISABLE;
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                first_block_set = DISABLE;
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                first_block_clear = DISABLE;
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                case(state)
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                        IDLE:
344
                                begin
345
                                        access_permission = ENABLE;
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                                        first_block_set = ENABLE;
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                                        if(enable && !key_deriv)
348
                                                cnt_en = ENABLE;
349
                                end
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                        INPUT:
351
                                begin
352
                                        if(PADDR == AES_DINR && write_en)
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                                                cnt_en = ENABLE;
354
                                end
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                        START:
356
                                begin
357
                                        start_core = ENABLE;
358
                                end
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                        WAIT:
360
                                begin
361
                                        if(ccf_set)
362
                                                cnt_en = ENABLE;
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                                        if(ccf_set && key_deriv)
364
                                                enable_clear = ENABLE;
365
                                end
366
                        OUTPUT:
367
                                begin
368
                                        first_block_clear = ENABLE;
369
                                        if(PADDR == AES_DOUTR && read_en && PENABLE )//|| write_completed)
370
                                                cnt_en = ENABLE;
371
                                end
372
                endcase
373
        end
374
 
375
// First Block Signal indicates when IV register is used
376
always @(posedge PCLK, negedge PRESETn)
377
        begin
378
                if(!PRESETn)
379
                        first_block <= 1'b1;
380
                else
381
                        if(first_block_set)
382
                                first_block <= 1'b1;
383
                        else
384
                                if(first_block_clear)
385
                                        first_block <= 1'b0;
386
        end
387
 
388
always @(posedge PCLK, negedge PRESETn)
389
        begin
390
                if(!PRESETn)
391
                        cnt <= 2'b11;
392
                else
393
                        begin
394
                                if(!enable || state == START)
395
                                        cnt <= 2'b11;
396
                                else
397
                                        if(cnt_en)
398
                                                cnt <= cnt + 1'b1;
399
                        end
400
        end
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402
assign col_addr = cnt;
403
assign col_wr_en = (PADDR == AES_DINR  && write_en && state == INPUT);
404
assign col_rd_en = (PADDR == AES_DOUTR && read_en  && state == OUTPUT);
405 12 redbear
assign wr_err_en = (PADDR == AES_DINR  && write_en && (state != INPUT  && state != IDLE));
406
assign rd_err_en = (PADDR == AES_DOUTR && read_en  && (state != OUTPUT && state != IDLE));
407 2 redbear
 
408
// DMA Requests Logic
409
always @(posedge PCLK, negedge PRESETn)
410
        begin
411
                if(!PRESETn)
412 7 redbear
                        dma_req <= 1'b0;
413 2 redbear
                else
414
                        dma_req <= cnt[0];
415
        end
416
 
417
assign dma_req_wr = (dma_req ^ cnt[0]) & dma_in_en  & enable & (state == INPUT  || state == IDLE);
418
assign dma_req_rd = (dma_req ^ cnt[0]) & dma_out_en & enable & (state == OUTPUT);
419
 
420
// APB Read Signal
421
assign PRDATA = bus_out;
422
 
423
// Output Mux
424
always @(*)
425
        begin
426
                bus_out_mux = 32'd0;
427
                case(PADDR)
428
                        AES_CR:
429
                                bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
430
                        AES_SR:
431 10 redbear
                                bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf_set && ~PENABLE)? 1'b1:(ccfc && aes_cr_wr_en)?1'b0:ccf};
432 2 redbear
                        AES_DINR, AES_DOUTR:
433 10 redbear
                        begin
434
                                if(~PWRITE && PADDR == AES_DOUTR && (ccf_set || ccf ))
435
                                        bus_out_mux = col_bus;
436
                        end
437 2 redbear
                        AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
438 7 redbear
                                if(!enable)
439
                                        bus_out_mux = key_bus;
440 2 redbear
                        AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
441
                                if(!enable)
442
                                        bus_out_mux = iv_bus;
443 7 redbear
 
444 2 redbear
                endcase
445
        end
446
 
447
// The output Bus is registered
448 7 redbear
 
449
assign bus_out =(read_en)? bus_out_mux:32'd0;
450
 
451
/*
452 2 redbear
always @(posedge PCLK, negedge PRESETn)
453
        begin
454
                if(!PRESETn)
455
                        bus_out <= 32'd0;
456
                else
457
                        if(read_en)
458
                                bus_out <= bus_out_mux;
459
        end
460 7 redbear
*/
461 2 redbear
 
462
endmodule

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