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//////////////////////////////////////////////////////////////////
////
////
////    AES CORE BLOCK
////
////
////
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbi2c/
////
////
////
//// Description
////
//// Implementation of APB IP core according to
////
//// aes128_spec IP core specification document.
////
////
////
//// To Do: Things are right here but always all block can suffer changes
////
////
////
////
////
//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
////              Julio Cesar 
////
///////////////////////////////////////////////////////////////// 
////
////
//// Copyright (C) 2009 Authors and OPENCORES.ORG
////
////
////
//// This source file may be used and distributed without
////
//// restriction provided that this copyright statement is not
////
//// removed from the file and that any derivative work contains
//// the original copyright notice and the associated disclaimer.
////
////
//// This source file is free software; you can redistribute it
////
//// and/or modify it under the terms of the GNU Lesser General
////
//// Public License as published by the Free Software Foundation;
//// either version 2.1 of the License, or (at your option) any
////
//// later version.
////
////
////
//// This source is distributed in the hope that it will be
////
//// useful, but WITHOUT ANY WARRANTY; without even the implied
////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
////
//// PURPOSE. See the GNU Lesser General Public License for more
//// details.
////
////
////
//// You should have received a copy of the GNU Lesser General
////
//// Public License along with this source; if not, download it
////
//// from http://www.opencores.org/lgpl.shtml
////
////
///////////////////////////////////////////////////////////////////
module host_interface
(
        // OUTPUTS
        output [3:0] key_en,
        output [1:0] col_addr,
        output [1:0] chmod,
        output [1:0] mode,
        output [1:0] data_type,
        output col_wr_en,
        output col_rd_en,
        output [1:0] key_sel,
        output [3:0] iv_en,
        output [3:0] iv_sel,
        output int_ccf,
        output int_err,
        output disable_core,
        output reg first_block,
        output dma_req_wr,
        output dma_req_rd,
        output reg start_core,
        output [31:0] PRDATA,
        //INPUTS
        input [3:0] PADDR,
        input [12:0] PWDATA,
        input PWRITE,
        input PENABLE,
        input PSEL,
        input PCLK,
        input PRESETn,
        input [31:0] key_bus,
        input [31:0] col_bus,
        input [31:0] iv_bus,
        input ccf_set
);
 
//`include "include/host_interface.vh"
 
//=====================================================================================
// Memory Mapped Registers Address
//=====================================================================================
localparam AES_CR    = 4'd00;
localparam AES_SR    = 4'd01;
localparam AES_DINR  = 4'd02;
localparam AES_DOUTR = 4'd03;
localparam AES_KEYR0 = 4'd04;
localparam AES_KEYR1 = 4'd05;
localparam AES_KEYR2 = 4'd06;
localparam AES_KEYR3 = 4'd07;
localparam AES_IVR0  = 4'd08;
localparam AES_IVR1  = 4'd09;
localparam AES_IVR2  = 4'd10;
localparam AES_IVR3  = 4'd11;
 
//=============================================================================
// Operation Modes
//=============================================================================
localparam ENCRYPTION     = 2'b00;
localparam KEY_DERIVATION = 2'b01;
localparam DECRYPTION     = 2'b10;
localparam DECRYP_W_DERIV = 2'b11;
 
//=============================================================================
// AES Modes
//=============================================================================
localparam ECB = 2'b00;
localparam CBC = 2'b01;
localparam CTR = 2'b10;
 
//=============================================================================
// Resets Values
//=============================================================================
localparam AES_CR_RESET = 13'd0;
localparam AES_SR_RESET =  3'd0;
 
//=============================================================================
// Enable Value (Active High)
//=============================================================================
localparam ENABLE  = 1'b1;
localparam DISABLE = 1'b0;
 
//=============================================================================
// FSM STATES
//=============================================================================
localparam IDLE   = 3'd0;
localparam INPUT  = 3'd1;
localparam START  = 3'd2;
localparam WAIT   = 3'd3;
localparam OUTPUT = 3'd4;
 
wire [31:0] bus_out;
reg [31:0] bus_out_mux;
reg cnt_en;
reg enable_clear;
reg access_permission;
reg first_block_set;
reg first_block_clear;
wire [1:0] mode_in;
wire [1:0] chmod_in;
wire write_en;
wire read_en;
wire dma_out_en;
wire dma_in_en;
wire err_ie;
wire ccf_ie;
wire errc;
wire ccfc;
wire aes_cr_wr_en;
//wire aes_sr_wr_en;
wire wr_err_en;
wire rd_err_en;
wire write_completed;
wire read_completed;
wire key_deriv;
 
 
reg [10:0] aes_cr;
reg wr_err;
reg rd_err;
reg ccf;
reg [2:0] state, next_state;
reg [1:0] cnt;
reg dma_req;
wire enable;
 
// Write and read enable signals
assign write_en = PSEL & PENABLE & PWRITE;
assign read_en  = (PSEL & ~PWRITE & (ccf_set | ccf))?1'b1:
                  ((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3 ))?1'b1:1'b0;
 
// Configuration Register Logic
assign dma_out_en = aes_cr[10];
assign dma_in_en  = aes_cr[9];
assign err_ie     = aes_cr[8];
assign ccf_ie     = aes_cr[7];
assign errc       = PWDATA[8];
assign ccfc       = PWDATA[7];
assign chmod      = aes_cr[6:5];
assign mode       = aes_cr[4:3];
assign data_type  = aes_cr[2:1];
assign enable     = aes_cr[0];
 
assign aes_cr_wr_en = (PADDR == AES_CR) & write_en;
assign mode_in  = PWDATA[4:3];
assign chmod_in = PWDATA[6:5];
 
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                        aes_cr <= AES_CR_RESET[10:0];
                else
                        begin
                                if(enable_clear)
                                        aes_cr[0] <= 1'b0;
                                else
                                        if(aes_cr_wr_en)
                                                aes_cr[0] <= PWDATA[0];
 
                                if(aes_cr_wr_en && access_permission)
                                        begin
                                                aes_cr[2:1] <= PWDATA[2:1];
                                                if(mode_in == DECRYP_W_DERIV && chmod_in == CTR)
                                                        aes_cr[4:3] <= DECRYPTION;
                                                else
                                                        aes_cr[4:3] <= mode_in;
                                                aes_cr[ 6:5] <= PWDATA[6:5];
                                                aes_cr[10:7] <= PWDATA[12:9];
                                        end
                        end
        end
 
// Status Register Logic
//assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;
 
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                begin
                        {wr_err, rd_err, ccf} <= AES_SR_RESET;
 
                end
                else
                        begin
                                // Write Error Flag
                                if(wr_err_en)
                                        wr_err <= 1'b1;
                                else
                                        if(errc && aes_cr_wr_en && access_permission)
                                                wr_err <= 1'b0;
 
                                //Read Error Flag
                                if(rd_err_en)
                                        rd_err <= 1'b1;
                                else
                                        if(errc && aes_cr_wr_en && access_permission)
                                                rd_err <= 1'b0;
 
                                // Computation Complete Flag
                                if(ccf_set)
                                        ccf <= 1'b1;
                                else
                                        if(ccfc && aes_cr_wr_en)// && access_permission)
                                                ccf <= 1'b0;
                        end
        end
// Interruption on erros Signals
assign int_ccf = ccf_ie & ccf_set;
assign int_err = (wr_err_en | rd_err_en) & err_ie;
 
// Key Signals Decoding
assign key_en = (4'b1000 >> PADDR[1:0]) & {4{(~PADDR[3] & PADDR[2] & access_permission & write_en)}};
assign key_sel = ~PADDR[1:0] & {2{(PADDR[2] & access_permission)}};
 
// IV Signals Decoding
assign iv_sel = (4'b1000 >> PADDR[1:0]) & {4{(PADDR[3] & ~PADDR[2] & access_permission)}};
assign iv_en = iv_sel & {4{write_en}};
 
// State Register
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                        state <= IDLE;
                else
                        if(!enable)
                                state <= IDLE;
                        else
                                state <= next_state;
        end
 
assign write_completed = (cnt == 2'b11);
assign read_completed  = (cnt == 2'b11);
assign key_deriv = (mode == KEY_DERIVATION);
 
// Next State Logic
always @(*)
        begin
                next_state = state;
                case(state)
                IDLE  :
                        begin
                                if(enable)
                                        next_state = (key_deriv) ? START : INPUT;
                        end
                INPUT :
                        next_state = (write_completed && cnt_en) ? START : INPUT;
                START :
                        next_state = WAIT;
                WAIT  :
                        begin
                                if(ccf_set)
                                        next_state = (key_deriv) ? IDLE : OUTPUT;
                        end
                OUTPUT:
                        next_state = (read_completed && cnt_en) ? INPUT : OUTPUT;
                endcase
        end
 
// Output Logic
assign disable_core = ~enable;
 
always @(*)
        begin
                access_permission = DISABLE;
                start_core = DISABLE;
                cnt_en = DISABLE;
                enable_clear = DISABLE;
                first_block_set = DISABLE;
                first_block_clear = DISABLE;
                case(state)
                        IDLE:
                                begin
                                        access_permission = ENABLE;
                                        first_block_set = ENABLE;
                                        if(enable && !key_deriv)
                                                cnt_en = ENABLE;
                                end
                        INPUT:
                                begin
                                        if(PADDR == AES_DINR && write_en)
                                                cnt_en = ENABLE;
                                end
                        START:
                                begin
                                        start_core = ENABLE;
                                end
                        WAIT:
                                begin
                                        if(ccf_set)
                                                cnt_en = ENABLE;
                                        if(ccf_set && key_deriv)
                                                enable_clear = ENABLE;
                                end
                        OUTPUT:
                                begin
                                        first_block_clear = ENABLE;
                                        if(PADDR == AES_DOUTR && read_en && PENABLE )//|| write_completed)
                                                cnt_en = ENABLE;
                                end
                endcase
        end
 
// First Block Signal indicates when IV register is used
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                        first_block <= 1'b1;
                else
                        if(first_block_set)
                                first_block <= 1'b1;
                        else
                                if(first_block_clear)
                                        first_block <= 1'b0;
        end
 
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                        cnt <= 2'b11;
                else
                        begin
                                if(!enable || state == START)
                                        cnt <= 2'b11;
                                else
                                        if(cnt_en)
                                                cnt <= cnt + 1'b1;
                        end
        end
 
assign col_addr = cnt;
assign col_wr_en = (PADDR == AES_DINR  && write_en && state == INPUT);
assign col_rd_en = (PADDR == AES_DOUTR && read_en  && state == OUTPUT);
assign wr_err_en = (PADDR == AES_DINR  && write_en && (state != INPUT  && state != IDLE));
assign rd_err_en = (PADDR == AES_DOUTR && read_en  && (state != OUTPUT && state != IDLE));
 
// DMA Requests Logic
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                        dma_req <= 1'b0;
                else
                        dma_req <= cnt[0];
        end
 
assign dma_req_wr = (dma_req ^ cnt[0]) & dma_in_en  & enable & (state == INPUT  || state == IDLE);
assign dma_req_rd = (dma_req ^ cnt[0]) & dma_out_en & enable & (state == OUTPUT);
 
// APB Read Signal
assign PRDATA = bus_out;
 
// Output Mux
always @(*)
        begin
                bus_out_mux = 32'd0;
                case(PADDR)
                        AES_CR:
                                bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
                        AES_SR:
                        begin
 
                                bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
                                /*
                                if(~ccfc && ~aes_cr_wr_en)
                                begin
                                        bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
                                end
                                else
                                begin
                                        bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf_set | ccf)?1'b1:1'b0};
                                end
                                */
                        end
                        AES_DINR, AES_DOUTR:
                                bus_out_mux = col_bus;
                        AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
                                if(!enable)
                                        bus_out_mux = key_bus;
                        AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
                                if(!enable)
                                        bus_out_mux = iv_bus;
 
                endcase
        end
 
// The output Bus is registered
 
assign bus_out =(read_en)? bus_out_mux:32'd0;
 
/*
always @(posedge PCLK, negedge PRESETn)
        begin
                if(!PRESETn)
                        bus_out <= 32'd0;
                else
                        if(read_en)
                                bus_out <= bus_out_mux;
        end
*/
 
endmodule

Line No.	Rev	Author	Line
1	2	redbear	`//////////////////////////////////////////////////////////////////`
2			`////`
3			`////`
4			`//// AES CORE BLOCK`
5			`////`
6			`////`
7			`////`
8	7	redbear	`//// This file is part of the APB to I2C project`
9	2	redbear	`////`
10	7	redbear	`//// http://www.opencores.org/cores/apbi2c/`
11	2	redbear	`////`
12			`////`
13			`////`
14			`//// Description`
15			`////`
16			`//// Implementation of APB IP core according to`
17			`////`
18			`//// aes128_spec IP core specification document.`
19			`////`
20			`////`
21			`////`
22			`//// To Do: Things are right here but always all block can suffer changes`
23			`////`
24			`////`
25			`////`
26			`////`
27			`////`
28			`//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com`
29			`//// Julio Cesar`
30			`////`
31			`/////////////////////////////////////////////////////////////////`
32			`////`
33			`////`
34			`//// Copyright (C) 2009 Authors and OPENCORES.ORG`
35			`////`
36			`////`
37			`////`
38			`//// This source file may be used and distributed without`
39			`////`
40			`//// restriction provided that this copyright statement is not`
41			`////`
42			`//// removed from the file and that any derivative work contains`
43			`//// the original copyright notice and the associated disclaimer.`
44			`////`
45			`////`
46			`//// This source file is free software; you can redistribute it`
47			`////`
48			`//// and/or modify it under the terms of the GNU Lesser General`
49			`////`
50			`//// Public License as published by the Free Software Foundation;`
51			`//// either version 2.1 of the License, or (at your option) any`
52			`////`
53			`//// later version.`
54			`////`
55			`////`
56			`////`
57			`//// This source is distributed in the hope that it will be`
58			`////`
59			`//// useful, but WITHOUT ANY WARRANTY; without even the implied`
60			`////`
61			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR`
62			`////`
63			`//// PURPOSE. See the GNU Lesser General Public License for more`
64			`//// details.`
65			`////`
66			`////`
67			`////`
68			`//// You should have received a copy of the GNU Lesser General`
69			`////`
70			`//// Public License along with this source; if not, download it`
71			`////`
72			`//// from http://www.opencores.org/lgpl.shtml`
73			`////`
74			`////`
75			`///////////////////////////////////////////////////////////////////`
76			`module host_interface`
77			`(`
78			`// OUTPUTS`
79			`output [3:0] key_en,`
80			`output [1:0] col_addr,`
81			`output [1:0] chmod,`
82			`output [1:0] mode,`
83			`output [1:0] data_type,`
84			`output col_wr_en,`
85			`output col_rd_en,`
86			`output [1:0] key_sel,`
87			`output [3:0] iv_en,`
88			`output [3:0] iv_sel,`
89			`output int_ccf,`
90			`output int_err,`
91			`output disable_core,`
92			`output reg first_block,`
93			`output dma_req_wr,`
94			`output dma_req_rd,`
95			`output reg start_core,`
96			`output [31:0] PRDATA,`
97			`//INPUTS`
98			`input [3:0] PADDR,`
99	7	redbear	`input [12:0] PWDATA,`
100	2	redbear	`input PWRITE,`
101			`input PENABLE,`
102			`input PSEL,`
103			`input PCLK,`
104			`input PRESETn,`
105			`input [31:0] key_bus,`
106			`input [31:0] col_bus,`
107			`input [31:0] iv_bus,`
108			`input ccf_set`
109			`);`
110
111			//`include "include/host_interface.vh"
112
113			`//=====================================================================================`
114			`// Memory Mapped Registers Address`
115			`//=====================================================================================`
116			`localparam AES_CR = 4'd00;`
117			`localparam AES_SR = 4'd01;`
118			`localparam AES_DINR = 4'd02;`
119			`localparam AES_DOUTR = 4'd03;`
120			`localparam AES_KEYR0 = 4'd04;`
121			`localparam AES_KEYR1 = 4'd05;`
122			`localparam AES_KEYR2 = 4'd06;`
123			`localparam AES_KEYR3 = 4'd07;`
124			`localparam AES_IVR0 = 4'd08;`
125			`localparam AES_IVR1 = 4'd09;`
126			`localparam AES_IVR2 = 4'd10;`
127			`localparam AES_IVR3 = 4'd11;`
128
129			`//=============================================================================`
130			`// Operation Modes`
131			`//=============================================================================`
132			`localparam ENCRYPTION = 2'b00;`
133			`localparam KEY_DERIVATION = 2'b01;`
134			`localparam DECRYPTION = 2'b10;`
135			`localparam DECRYP_W_DERIV = 2'b11;`
136
137			`//=============================================================================`
138			`// AES Modes`
139			`//=============================================================================`
140			`localparam ECB = 2'b00;`
141			`localparam CBC = 2'b01;`
142			`localparam CTR = 2'b10;`
143
144			`//=============================================================================`
145			`// Resets Values`
146			`//=============================================================================`
147			`localparam AES_CR_RESET = 13'd0;`
148			`localparam AES_SR_RESET = 3'd0;`
149
150			`//=============================================================================`
151			`// Enable Value (Active High)`
152			`//=============================================================================`
153			`localparam ENABLE = 1'b1;`
154			`localparam DISABLE = 1'b0;`
155
156			`//=============================================================================`
157			`// FSM STATES`
158			`//=============================================================================`
159			`localparam IDLE = 3'd0;`
160			`localparam INPUT = 3'd1;`
161			`localparam START = 3'd2;`
162			`localparam WAIT = 3'd3;`
163			`localparam OUTPUT = 3'd4;`
164
165	7	redbear	`wire [31:0] bus_out;`
166	2	redbear	`reg [31:0] bus_out_mux;`
167			`reg cnt_en;`
168			`reg enable_clear;`
169			`reg access_permission;`
170			`reg first_block_set;`
171			`reg first_block_clear;`
172			`wire [1:0] mode_in;`
173			`wire [1:0] chmod_in;`
174			`wire write_en;`
175			`wire read_en;`
176			`wire dma_out_en;`
177			`wire dma_in_en;`
178			`wire err_ie;`
179			`wire ccf_ie;`
180			`wire errc;`
181			`wire ccfc;`
182			`wire aes_cr_wr_en;`
183	7	redbear	`//wire aes_sr_wr_en;`
184	2	redbear	`wire wr_err_en;`
185			`wire rd_err_en;`
186			`wire write_completed;`
187			`wire read_completed;`
188			`wire key_deriv;`
189
190
191			`reg [10:0] aes_cr;`
192			`reg wr_err;`
193			`reg rd_err;`
194			`reg ccf;`
195			`reg [2:0] state, next_state;`
196			`reg [1:0] cnt;`
197			`reg dma_req;`
198	7	redbear	`wire enable;`
199	2	redbear
200			`// Write and read enable signals`
201			`assign write_en = PSEL & PENABLE & PWRITE;`
202	7	redbear	`assign read_en = (PSEL & ~PWRITE & (ccf_set \| ccf))?1'b1:`
203			`((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3 ))?1'b1:1'b0;`
204	2	redbear
205			`// Configuration Register Logic`
206			`assign dma_out_en = aes_cr[10];`
207			`assign dma_in_en = aes_cr[9];`
208			`assign err_ie = aes_cr[8];`
209			`assign ccf_ie = aes_cr[7];`
210			`assign errc = PWDATA[8];`
211			`assign ccfc = PWDATA[7];`
212			`assign chmod = aes_cr[6:5];`
213			`assign mode = aes_cr[4:3];`
214			`assign data_type = aes_cr[2:1];`
215			`assign enable = aes_cr[0];`
216
217			`assign aes_cr_wr_en = (PADDR == AES_CR) & write_en;`
218			`assign mode_in = PWDATA[4:3];`
219			`assign chmod_in = PWDATA[6:5];`
220
221			`always @(posedge PCLK, negedge PRESETn)`
222			`begin`
223			`if(!PRESETn)`
224	7	redbear	`aes_cr <= AES_CR_RESET[10:0];`
225	2	redbear	`else`
226			`begin`
227			`if(enable_clear)`
228			`aes_cr[0] <= 1'b0;`
229			`else`
230			`if(aes_cr_wr_en)`
231			`aes_cr[0] <= PWDATA[0];`
232
233			`if(aes_cr_wr_en && access_permission)`
234			`begin`
235			`aes_cr[2:1] <= PWDATA[2:1];`
236			`if(mode_in == DECRYP_W_DERIV && chmod_in == CTR)`
237			`aes_cr[4:3] <= DECRYPTION;`
238			`else`
239			`aes_cr[4:3] <= mode_in;`
240			`aes_cr[ 6:5] <= PWDATA[6:5];`
241			`aes_cr[10:7] <= PWDATA[12:9];`
242			`end`
243			`end`
244			`end`
245
246			`// Status Register Logic`
247	7	redbear	`//assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;`
248	2	redbear
249			`always @(posedge PCLK, negedge PRESETn)`
250			`begin`
251			`if(!PRESETn)`
252	7	redbear	`begin`
253	2	redbear	`{wr_err, rd_err, ccf} <= AES_SR_RESET;`
254	7	redbear
255			`end`
256	2	redbear	`else`
257			`begin`
258			`// Write Error Flag`
259			`if(wr_err_en)`
260			`wr_err <= 1'b1;`
261			`else`
262			`if(errc && aes_cr_wr_en && access_permission)`
263			`wr_err <= 1'b0;`
264
265			`//Read Error Flag`
266			`if(rd_err_en)`
267			`rd_err <= 1'b1;`
268			`else`
269			`if(errc && aes_cr_wr_en && access_permission)`
270			`rd_err <= 1'b0;`
271
272			`// Computation Complete Flag`
273			`if(ccf_set)`
274	7	redbear	`ccf <= 1'b1;`
275	2	redbear	`else`
276			`if(ccfc && aes_cr_wr_en)// && access_permission)`
277			`ccf <= 1'b0;`
278			`end`
279			`end`
280			`// Interruption on erros Signals`
281			`assign int_ccf = ccf_ie & ccf_set;`
282			`assign int_err = (wr_err_en \| rd_err_en) & err_ie;`
283
284			`// Key Signals Decoding`
285			`assign key_en = (4'b1000 >> PADDR[1:0]) & {4{(~PADDR[3] & PADDR[2] & access_permission & write_en)}};`
286			`assign key_sel = ~PADDR[1:0] & {2{(PADDR[2] & access_permission)}};`
287
288			`// IV Signals Decoding`
289			`assign iv_sel = (4'b1000 >> PADDR[1:0]) & {4{(PADDR[3] & ~PADDR[2] & access_permission)}};`
290			`assign iv_en = iv_sel & {4{write_en}};`
291
292			`// State Register`
293			`always @(posedge PCLK, negedge PRESETn)`
294			`begin`
295			`if(!PRESETn)`
296			`state <= IDLE;`
297			`else`
298			`if(!enable)`
299			`state <= IDLE;`
300			`else`
301			`state <= next_state;`
302			`end`
303
304			`assign write_completed = (cnt == 2'b11);`
305			`assign read_completed = (cnt == 2'b11);`
306			`assign key_deriv = (mode == KEY_DERIVATION);`
307
308			`// Next State Logic`
309			`always @(*)`
310			`begin`
311			`next_state = state;`
312			`case(state)`
313			`IDLE :`
314			`begin`
315			`if(enable)`
316			`next_state = (key_deriv) ? START : INPUT;`
317			`end`
318			`INPUT :`
319			`next_state = (write_completed && cnt_en) ? START : INPUT;`
320			`START :`
321			`next_state = WAIT;`
322			`WAIT :`
323			`begin`
324			`if(ccf_set)`
325			`next_state = (key_deriv) ? IDLE : OUTPUT;`
326			`end`
327			`OUTPUT:`
328			`next_state = (read_completed && cnt_en) ? INPUT : OUTPUT;`
329			`endcase`
330			`end`
331
332			`// Output Logic`
333			`assign disable_core = ~enable;`
334
335			`always @(*)`
336			`begin`
337			`access_permission = DISABLE;`
338			`start_core = DISABLE;`
339			`cnt_en = DISABLE;`
340			`enable_clear = DISABLE;`
341			`first_block_set = DISABLE;`
342			`first_block_clear = DISABLE;`
343			`case(state)`
344			`IDLE:`
345			`begin`
346			`access_permission = ENABLE;`
347			`first_block_set = ENABLE;`
348			`if(enable && !key_deriv)`
349			`cnt_en = ENABLE;`
350			`end`
351			`INPUT:`
352			`begin`
353			`if(PADDR == AES_DINR && write_en)`
354			`cnt_en = ENABLE;`
355			`end`
356			`START:`
357			`begin`
358			`start_core = ENABLE;`
359			`end`
360			`WAIT:`
361			`begin`
362			`if(ccf_set)`
363			`cnt_en = ENABLE;`
364			`if(ccf_set && key_deriv)`
365			`enable_clear = ENABLE;`
366			`end`
367			`OUTPUT:`
368			`begin`
369			`first_block_clear = ENABLE;`
370			`if(PADDR == AES_DOUTR && read_en && PENABLE )//\|\| write_completed)`
371			`cnt_en = ENABLE;`
372			`end`
373			`endcase`
374			`end`
375
376			`// First Block Signal indicates when IV register is used`
377			`always @(posedge PCLK, negedge PRESETn)`
378			`begin`
379			`if(!PRESETn)`
380			`first_block <= 1'b1;`
381			`else`
382			`if(first_block_set)`
383			`first_block <= 1'b1;`
384			`else`
385			`if(first_block_clear)`
386			`first_block <= 1'b0;`
387			`end`
388
389			`always @(posedge PCLK, negedge PRESETn)`
390			`begin`
391			`if(!PRESETn)`
392			`cnt <= 2'b11;`
393			`else`
394			`begin`
395			`if(!enable \|\| state == START)`
396			`cnt <= 2'b11;`
397			`else`
398			`if(cnt_en)`
399			`cnt <= cnt + 1'b1;`
400			`end`
401			`end`
402
403			`assign col_addr = cnt;`
404			`assign col_wr_en = (PADDR == AES_DINR && write_en && state == INPUT);`
405			`assign col_rd_en = (PADDR == AES_DOUTR && read_en && state == OUTPUT);`
406			`assign wr_err_en = (PADDR == AES_DINR && write_en && (state != INPUT && state != IDLE));`
407			`assign rd_err_en = (PADDR == AES_DOUTR && read_en && (state != OUTPUT && state != IDLE));`
408
409			`// DMA Requests Logic`
410			`always @(posedge PCLK, negedge PRESETn)`
411			`begin`
412			`if(!PRESETn)`
413	7	redbear	`dma_req <= 1'b0;`
414	2	redbear	`else`
415			`dma_req <= cnt[0];`
416			`end`
417
418			`assign dma_req_wr = (dma_req ^ cnt[0]) & dma_in_en & enable & (state == INPUT \|\| state == IDLE);`
419			`assign dma_req_rd = (dma_req ^ cnt[0]) & dma_out_en & enable & (state == OUTPUT);`
420
421			`// APB Read Signal`
422			`assign PRDATA = bus_out;`
423
424			`// Output Mux`
425			`always @(*)`
426			`begin`
427			`bus_out_mux = 32'd0;`
428			`case(PADDR)`
429			`AES_CR:`
430			`bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};`
431			`AES_SR:`
432	7	redbear	`begin`
433
434			`bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};`
435			`/*`
436			`if(~ccfc && ~aes_cr_wr_en)`
437			`begin`
438			`bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};`
439			`end`
440			`else`
441			`begin`
442			`bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf_set \| ccf)?1'b1:1'b0};`
443			`end`
444			`*/`
445			`end`
446	2	redbear	`AES_DINR, AES_DOUTR:`
447			`bus_out_mux = col_bus;`
448			`AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:`
449	7	redbear	`if(!enable)`
450			`bus_out_mux = key_bus;`
451	2	redbear	`AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:`
452			`if(!enable)`
453			`bus_out_mux = iv_bus;`
454	7	redbear
455	2	redbear	`endcase`
456			`end`
457
458			`// The output Bus is registered`
459	7	redbear
460			`assign bus_out =(read_en)? bus_out_mux:32'd0;`
461
462			`/*`
463	2	redbear	`always @(posedge PCLK, negedge PRESETn)`
464			`begin`
465			`if(!PRESETn)`
466			`bus_out <= 32'd0;`
467			`else`
468			`if(read_en)`
469			`bus_out <= bus_out_mux;`
470			`end`
471	7	redbear	`*/`
472	2	redbear
473			`endmodule`

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