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[/] [apbtoaes128/] [trunk/] [testbench/] [aes_tb_vpi.v] - Blame information for rev 4

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1 4 redbear
//////////////////////////////////////////////////////////////////
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////
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////
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////    AES CORE BLOCK
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////
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////
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////
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//// This file is part of the APB to AES128 project
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////
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//// http://www.opencores.org/cores/apbtoaes128/
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////
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////
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////
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//// Description
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////
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//// Implementation of APB IP core according to
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////
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//// aes128_spec IP core specification document.
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////
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////
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////
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//// To Do: Things are right here but always all block can suffer changes
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////
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////
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////
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////
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////
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//// Author(s): - Felipe Fernandes Da Costa, fefe2560@gmail.com
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////
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///////////////////////////////////////////////////////////////// 
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////
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////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG
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////
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////
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////
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//// This source file may be used and distributed without
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////
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//// restriction provided that this copyright statement is not
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////
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//// removed from the file and that any derivative work contains
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//// the original copyright notice and the associated disclaimer.
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////
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////
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//// This source file is free software; you can redistribute it
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////
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//// and/or modify it under the terms of the GNU Lesser General
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////
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//// Public License as published by the Free Software Foundation;
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//// either version 2.1 of the License, or (at your option) any
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////
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//// later version.
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////
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////
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////
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//// This source is distributed in the hope that it will be
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////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied
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////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
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////
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//// PURPOSE. See the GNU Lesser General Public License for more
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//// details.
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////
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////
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////
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//// You should have received a copy of the GNU Lesser General
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////
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//// Public License along with this source; if not, download it
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////
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//// from http://www.opencores.org/lgpl.shtml
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////
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////
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///////////////////////////////////////////////////////////////////
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module AES_GLADIC_tb;
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        reg PCLK;
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        wire PRESETn;
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        wire PSEL;
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        wire PENABLE;
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        wire PWRITE;
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        wire [31:0] PWDATA;
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        wire [31:0] PADDR;
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        wire [31:0] PRDATA;
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        wire PREADY;
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        wire PSLVERR;
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        wire int_ccf;
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        wire int_err;
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        wire dma_req_wr;
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        wire dma_req_rd;
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        wire [3:0] core_addr;
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        assign core_addr = PADDR[5:2];
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        aes_ip  DUT (
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                .PCLK (PCLK),
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                .PRESETn (PRESETn),
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                .PENABLE (PENABLE),
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                .PSEL (PSEL),
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                .PWDATA (PWDATA),
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                .PADDR (core_addr),
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                .PWRITE(PWRITE),
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                .PRDATA (PRDATA),
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                .PREADY (PREADY),
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                .PSLVERR (PSLVERR),
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                .int_ccf(int_ccf),
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                .int_err(int_err),
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                .dma_req_wr(dma_req_wr),
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                .dma_req_rd(dma_req_rd)
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        );
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        integer i;
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        initial
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         begin
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            $dumpfile("AES_GLADIC_tb.vcd");
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            $dumpvars(0,AES_GLADIC_tb);
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            $init;
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            $init_reset;
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         end
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        initial PCLK = 1'b0;
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        always #(5) PCLK = ~PCLK;
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        //
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        always@(posedge PCLK)
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                $bfm_encryption_ecb_aes128;
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        always@(posedge PCLK)
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                $bfm_encryption_ecb_dma_aes128;
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        always@(posedge PCLK)
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                $bfm_encryption_ccfie_ecb_aes128;
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        //
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        always@(posedge PCLK)
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                $bfm_key_generation_ecb_aes128;
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        always@(posedge PCLK)
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                $bfm_key_generation_dma_ecb_aes128;
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        always@(posedge PCLK)
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                $bfm_key_generation_ccfie_ecb_aes128;
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        //
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        always@(posedge PCLK)
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                $bfm_decryption_ecb_aes128;
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        always@(posedge PCLK)
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                $bfm_decryption_ecb_dma_aes128;
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        always@(posedge PCLK)
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                $bfm_decryption_ccfie_ecb_aes128;
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        //
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        always@(posedge PCLK)
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                $bfm_derivation_decryption_ecb_aes128;
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        always@(posedge PCLK)
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                $bfm_derivation_decryption_dma_ecb_aes128;
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        always@(posedge PCLK)
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                $bfm_derivation_decryption_ccfie_ecb_aes128;
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        //
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        always@(posedge PCLK)
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                $bfm_wr_aes128;
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        always@(posedge PCLK)
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                $bfm_wr_error_dinr_aes128;
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        always@(posedge PCLK)
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                $bfm_wr_error_doutr_aes128;
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        //
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        always@(posedge PCLK)
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                $bfm_generate_type;
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        //
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        always@(posedge PCLK)
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                $reset_aes128;
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        //
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        always@(posedge PCLK)
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                $monitor_aes;
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        //
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        always@(negedge PRESETn)
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                $init;
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        always@(posedge PCLK)
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        begin
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                while( i != 1)
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                begin
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                        @(posedge PCLK);
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                end
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                $finish();
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        end
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endmodule

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