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Bregalad |
-- This file is part of ARM4U CPU
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--
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-- This is a creation of the Laboratory of Processor Architecture
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-- of Ecole Polytechnique Fédérale de Lausanne ( http://lap.epfl.ch )
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--
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-- alu.vhd -- Hadrware description of the ALU unit (inside Execute pipeline stage)
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--
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-- Written By - Jonathan Masur and Xavier Jimenez (2013)
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--
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2, or (at your option) any
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-- later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- In other words, you are welcome to use, share and improve this program.
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-- You are forbidden to forbid anyone else to use, share and improve
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-- what you give them. Help stamp out software-hoarding!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.arm_types.all;
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entity alu is
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port (
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exe_alu_operation : in ALU_OPERATION;
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alu_o : out unsigned(31 downto 0);
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alu_opb, alu_opa : in unsigned(31 downto 0);
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n, z, c, v, barrelshift_c : in std_logic;
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lowflags : in std_logic_vector(5 downto 0);
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next_n, next_z, next_c, next_v : out std_logic;
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next_lowflags : out std_logic_vector(5 downto 0)
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);
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end;
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architecture rtl of alu is
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signal alu_out : unsigned(31 downto 0);
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signal adder_a, adder_b, adder_out : unsigned(31 downto 0);
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signal adder_cout, adder_vout : std_logic;
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signal adder_cin : unsigned(0 downto 0);
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begin
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alu_o <= alu_out; -- annoying VHDL
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-- 32 bit adder with carry in and carry out
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adder : process(adder_a, adder_b, adder_cin, adder_out) is
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variable add33 :unsigned(32 downto 0);
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begin
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add33 := ('0' & adder_a) + ('0' & adder_b) + adder_cin;
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adder_out <= add33(31 downto 0);
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-- carry out is bit 32 of the result
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adder_cout <= add33(32);
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-- overflow true if both operands were the same sign and the result is not the same sign
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adder_vout <= (add33(31) and not adder_a(31) and not adder_b(31)) or (not adder_out(31) and adder_a(31) and adder_b(31));
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end process;
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-- 32-bit ALU
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alu : process(exe_alu_operation, alu_out, alu_opb, alu_opa, n, z, c, v, lowflags, barrelshift_c, adder_out, adder_cout, adder_vout) is
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variable carry : unsigned(0 downto 0);
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begin
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adder_a <= (others => '-');
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adder_b <= (others => '-');
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adder_cin <= "-";
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-- annoying VHDL
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if c = '1' then carry := "1"; else carry := "0"; end if;
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-- default values for nzvc and low flags (v and lowflags doesn't change by default)
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next_n <= alu_out(31);
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if alu_out = X"00000000"
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then
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next_z <= '1';
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else
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next_z <= '0';
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end if;
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next_v <= v;
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next_c <= barrelshift_c;
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next_lowflags <= lowflags;
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case exe_alu_operation is
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when ALU_NOP => -- no ALU operation
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alu_out <= alu_opb;
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when ALU_NOT => -- one's complement operation
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alu_out <= not alu_opb;
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when ALU_ORR =>
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alu_out <= alu_opa or alu_opb;
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when ALU_AND =>
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alu_out <= alu_opa and alu_opb;
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when ALU_EOR =>
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alu_out <= alu_opa xor alu_opb;
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when ALU_BIC => -- bit clear
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alu_out <= alu_opa and not alu_opb;
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when ALU_RWF => -- read/write flags
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next_n <= alu_opb(31);
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next_z <= alu_opb(30);
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next_c <= alu_opb(29);
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next_v <= alu_opb(28);
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-- I and F flags
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next_lowflags(5 downto 4) <= std_logic_vector(alu_opb(7 downto 6));
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-- mode flags
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next_lowflags(3 downto 0) <= std_logic_vector(alu_opb(3 downto 0));
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--read (old) flags
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alu_out <= unsigned( n & z & c & v & (27 downto 8 => '0') & lowflags(5 downto 4) & '0' & '1' & lowflags(3 downto 0) );
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when ALU_ADD => -- addition without carry
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adder_a <= alu_opa;
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adder_b <= alu_opb;
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adder_cin <= "0";
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next_v <= adder_vout;
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alu_out <= adder_out;
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next_c <= adder_cout;
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when ALU_ADC => -- addition with carry
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adder_a <= alu_opa;
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adder_b <= alu_opb;
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adder_cin <= carry;
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next_v <= adder_vout;
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alu_out <= adder_out;
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next_c <= adder_cout;
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when ALU_SUB => -- substraction without carry
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adder_a <= alu_opa;
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adder_b <= not alu_opb;
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adder_cin <= "1";
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next_v <= adder_vout;
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alu_out <= adder_out;
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next_c <= adder_cout;
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when ALU_SBC => -- substraction with carry
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adder_a <= alu_opa;
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adder_b <= not alu_opb;
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adder_cin <= carry;
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next_v <= adder_vout;
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alu_out <= adder_out;
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next_c <= adder_cout;
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when ALU_RSB => -- reverse substraction without carry
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adder_a <= not alu_opa;
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adder_b <= alu_opb;
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adder_cin <= "1";
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next_v <= adder_vout;
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alu_out <= adder_out;
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next_c <= adder_cout;
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when ALU_RSC => -- reverse substraction with carry
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adder_a <= not alu_opa;
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adder_b <= alu_opb;
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adder_cin <= carry;
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next_v <= adder_vout;
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alu_out <= adder_out;
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next_c <= adder_cout;
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end case;
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end process;
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end;
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