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Bregalad |
-- This file is part of ARM4U CPU
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--
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-- This is a creation of the Laboratory of Processor Architecture
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-- of Ecole Polytechnique Fédérale de Lausanne ( http://lap.epfl.ch )
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--
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-- arm_types.vhd -- Package containing types for the whole project
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--
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-- Written By - Jonathan Masur and Xavier Jimenez (2013)
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--
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2, or (at your option) any
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-- later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- In other words, you are welcome to use, share and improve this program.
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-- You are forbidden to forbid anyone else to use, share and improve
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-- what you give them. Help stamp out software-hoarding!
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library ieee;
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use ieee.std_logic_1164.all;
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package arm_types is
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-- Condition flags (top 4 bits of ARM instruction)
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constant COND_EQ : std_logic_vector(3 downto 0) := "0000";
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constant COND_NE : std_logic_vector(3 downto 0) := "0001";
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constant COND_CS : std_logic_vector(3 downto 0) := "0010";
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constant COND_CC : std_logic_vector(3 downto 0) := "0011";
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constant COND_MI : std_logic_vector(3 downto 0) := "0100";
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constant COND_PL : std_logic_vector(3 downto 0) := "0101";
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constant COND_VS : std_logic_vector(3 downto 0) := "0110";
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constant COND_VC : std_logic_vector(3 downto 0) := "0111";
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constant COND_HI : std_logic_vector(3 downto 0) := "1000";
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constant COND_LS : std_logic_vector(3 downto 0) := "1001";
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constant COND_GE : std_logic_vector(3 downto 0) := "1010";
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constant COND_LT : std_logic_vector(3 downto 0) := "1011";
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constant COND_GT : std_logic_vector(3 downto 0) := "1100";
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constant COND_LE : std_logic_vector(3 downto 0) := "1101";
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constant COND_AL : std_logic_vector(3 downto 0) := "1110";
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-- register re-mapping at decode stage
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constant r0 : std_logic_vector(4 downto 0) := "00000";
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constant r1 : std_logic_vector(4 downto 0) := "00001";
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constant r2 : std_logic_vector(4 downto 0) := "00010";
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constant r3 : std_logic_vector(4 downto 0) := "00011";
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constant r4 : std_logic_vector(4 downto 0) := "00100";
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constant r5 : std_logic_vector(4 downto 0) := "00101";
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constant r6 : std_logic_vector(4 downto 0) := "00110";
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constant r7 : std_logic_vector(4 downto 0) := "00111";
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constant r8 : std_logic_vector(4 downto 0) := "01000";
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constant r9 : std_logic_vector(4 downto 0) := "01001";
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constant r10 : std_logic_vector(4 downto 0) := "01010";
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constant r11 : std_logic_vector(4 downto 0) := "01011";
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constant r12 : std_logic_vector(4 downto 0) := "01100";
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constant r13 : std_logic_vector(4 downto 0) := "01101";
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constant r14 : std_logic_vector(4 downto 0) := "01110";
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constant fiq_r8 : std_logic_vector(4 downto 0) := "01111";
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constant fiq_r9 : std_logic_vector(4 downto 0) := "10000";
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constant fiq_r10 : std_logic_vector(4 downto 0) := "10001";
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constant fiq_r11 : std_logic_vector(4 downto 0) := "10010";
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constant fiq_r12 : std_logic_vector(4 downto 0) := "10011";
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constant fiq_r13 : std_logic_vector(4 downto 0) := "10100";
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constant sup_r13 : std_logic_vector(4 downto 0) := "10101";
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constant irq_r13 : std_logic_vector(4 downto 0) := "10110";
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constant und_r13 : std_logic_vector(4 downto 0) := "10111";
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constant fiq_r14 : std_logic_vector(4 downto 0) := "11000";
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constant sup_r14 : std_logic_vector(4 downto 0) := "11001";
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constant irq_r14 : std_logic_vector(4 downto 0) := "11010";
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constant und_r14 : std_logic_vector(4 downto 0) := "11011";
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constant fiq_spsr : std_logic_vector(4 downto 0) := "11100";
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constant sup_spsr : std_logic_vector(4 downto 0) := "11101";
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constant irq_spsr : std_logic_vector(4 downto 0) := "11110";
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constant und_spsr : std_logic_vector(4 downto 0) := "11111";
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-- Finite state machine inside the Decode pipeline stage
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type DECODE_FSM is (MAIN_STATE, RETURN_FROM_EXCEPTION, TWO_LATENCY_CYCLES, ONE_LATENCY_CYCLE, LOADSTORE_WRITEBACK,
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LDMSTM_TRANSFER, LDMSTM_RETURN_FROM_EXCEPTION, LDMSTM_WRITEBACK,
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RESET_CYCLE2, UNDEF_CYCLE2, SWI_CYCLE2, IRQ_CYCLE2, FIQ_CYCLE2);
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-- List of arithmetic and logical operations which can be performed in the execute pipeline stage
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type ALU_OPERATION is (ALU_NOP, ALU_NOT, ALU_ORR, ALU_AND, ALU_EOR, ALU_BIC, ALU_RWF, ALU_ADD, ALU_ADC, ALU_SUB, ALU_SBC, ALU_RSB, ALU_RSC);
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-- List of memory-related operation that can be perfored in the memory pipeline stage
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type MEM_OPERATION is (NO_MEM_OP, LOAD_WORD, LOAD_BYTE, LOAD_BURST, STORE_WORD, STORE_BYTE);
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end package;
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package body arm_types is
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end package body;
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