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Bregalad |
-- This file is part of ARM4U CPU
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--
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-- This is a creation of the Laboratory of Processor Architecture
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-- of Ecole Polytechnique Fédérale de Lausanne ( http://lap.epfl.ch )
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--
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-- writeback.vhd -- Description of the writeback pipeline stage
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--
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-- Written By - Jonathan Masur and Xavier Jimenez (2013)
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--
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-- This program is free software; you can redistribute it and/or modify it
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-- under the terms of the GNU General Public License as published by the
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-- Free Software Foundation; either version 2, or (at your option) any
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-- later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- In other words, you are welcome to use, share and improve this program.
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-- You are forbidden to forbid anyone else to use, share and improve
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-- what you give them. Help stamp out software-hoarding!
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.arm_types.all;
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entity writeback is
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port(
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clk : in std_logic;
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wb_stage_valid : in std_logic;
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wb_rdest_wren : in std_logic;
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wb_rdest_adr : in std_logic_vector(4 downto 0);
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wb_branch_en : in std_logic;
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wb_wb_sel : in std_logic;
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wb_exe_data : in std_logic_vector(31 downto 0);
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wb_mem_ctrl : in MEM_OPERATION;
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rfile_wr_enable : out std_logic;
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rfile_address : out std_logic_vector(4 downto 0);
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wb_data : out std_logic_vector(31 downto 0);
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fwd_wb2_enable : out std_logic;
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fwd_wb2_address : out std_logic_vector(4 downto 0);
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fwd_wb2_data : out std_logic_vector(31 downto 0);
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avm_data_readdatavalid : in std_logic;
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avm_data_readdata : in std_logic_vector(31 downto 0);
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wb_pc_wr : out std_logic;
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wb_blocked_n : out std_logic
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);
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end entity;
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architecture rtl of writeback is
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signal outdata : std_logic_vector(31 downto 0);
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signal avalon_data : std_logic_vector(31 downto 0);
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signal rd_ok : std_logic;
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begin
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-- 0 if the stage should stall because read data is not valid
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rd_ok <= avm_data_readdatavalid when wb_mem_ctrl = LOAD_WORD or wb_mem_ctrl = LOAD_BYTE or wb_mem_ctrl = LOAD_BURST else '1';
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wb_blocked_n <= rd_ok or not wb_stage_valid;
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-- write to PC on branches from avalon data
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wb_pc_wr <= wb_branch_en and wb_wb_sel and wb_stage_valid and rd_ok;
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-- output MUX between avalon data and execute data
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outdata <= wb_exe_data when wb_wb_sel = '0' else avalon_data;
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-- register file signals (also writeback 1 forwarding path)
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rfile_wr_enable <= wb_rdest_wren and wb_stage_valid;
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rfile_address <= wb_rdest_adr;
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wb_data <= outdata;
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avm : process(wb_exe_data, avm_data_readdata, wb_mem_ctrl) is
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begin
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-- convert byte->word if a load byte command
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if wb_mem_ctrl = LOAD_BYTE
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then
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case wb_exe_data(1 downto 0) is
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when "00" =>
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avalon_data <= (31 downto 8 => '0') & avm_data_readdata(7 downto 0);
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when "01" =>
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avalon_data <= (31 downto 8 => '0') & avm_data_readdata(15 downto 8);
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when "10" =>
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avalon_data <= (31 downto 8 => '0') & avm_data_readdata(23 downto 16);
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when others =>
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avalon_data <= (31 downto 8 => '0') & avm_data_readdata(31 downto 24);
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end case;
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else
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-- else data just goes through
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avalon_data <= avm_data_readdata;
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end if;
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end process;
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-- register for writeback2 forwarding path
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process(clk) is
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begin
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if rising_edge(clk)
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then
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fwd_wb2_enable <= wb_rdest_wren and wb_stage_valid;
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fwd_wb2_address <= wb_rdest_adr;
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fwd_wb2_data <= outdata;
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end if;
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end process;
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end architecture;
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