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library ieee;
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use ieee.std_logic_1164.all;
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use IEEE.std_logic_unsigned.all;
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use IEEE.std_logic_arith.all;
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entity serirq is
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port (
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clock : in std_logic;
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reset_n : in std_logic;
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slot_sel : in std_logic_vector(4 downto 0); --clk no of IRQ defined in Ser irq for PCI systems spec.
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serirq : inout std_logic;
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irq : in std_logic
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);
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end entity serirq;
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architecture RTL of serirq is
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type reg_type is
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record
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irq_idle : boolean; --idle mode only host can start irq cycles quiet mode is entered by 2 clock stop, 3 clock stop keeps or enters idle mode
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irq_frame : boolean; --currently in running irq frame
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serirq_oe : std_logic; --oe does pulldown
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low_count : std_logic_vector(3 downto 0);
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slot_count : std_logic_vector(7 downto 0);
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irq_count : std_logic_vector(3 downto 0); --wait before irq auto issue
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irq_sync : std_logic; --sync stage
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end record;
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signal reg, reg_in : reg_type;
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signal comb_oe : std_logic;
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begin
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serirq<='0' when comb_oe='1' else
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'Z';
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-- Design pattern process 1 Implementation
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comb : process (serirq,slot_sel,irq,reg)
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variable reg_v : reg_type;
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begin
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-- Design pattern
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reg_v:=reg; --pre set default var state
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------------------------------------
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--- <implementation> ---
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------------------------------------
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reg_v.irq_sync:=irq;
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--clear signel cycle oe
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reg_v.serirq_oe:='0'; --disable pulldown (this can never be longer than 1 cycle)
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--Frame start contition wait
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if reg_v.irq_idle and not reg_v.irq_frame then -- Idle mode wait for host to start
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if serirq='0' then -- count low cycles
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reg_v.low_count:=reg_v.low_count + 1;
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else -- see if the event is a start frame event
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if reg_v.low_count>"0011" then -- cycle start
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reg_v.irq_frame:=true;
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end if;
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reg_v.low_count:=(others=>'0');
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end if;
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elsif not reg_v.irq_idle and not reg_v.irq_frame and reg.irq_sync='1' then -- in active mode we can start the irq frame
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if reg_v.irq_count>"0010" then
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reg_v.serirq_oe:='1'; --enable pulldonw
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reg_v.irq_frame:=true; -- frame should start
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else
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reg_v.irq_count:=reg_v.irq_count + 1;
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end if;
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else -- in frame
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reg_v.irq_count:=(others=>'0'); --
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end if;
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--In IRQ frame
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if reg_v.irq_frame and reg_v.slot_count<x"FF" then --don't allow cnt overflow for slots
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reg_v.slot_count:=reg_v.slot_count + 1;
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else
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reg_v.slot_count:=(others=>'0'); --reset when out of frame
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end if;
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--Slot sel must use register value as it is incremented above in the variable for next cycle
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if reg_v.irq_frame and slot_sel/="00000" and reg.slot_count(7 downto 0)="000"&slot_sel and reg.irq_sync='1' then --when slot and irq active to pull on the serirq
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reg_v.serirq_oe:='1'; --enable pulldonw
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end if;
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-- End irq frame and enter idle or active mode
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if reg_v.irq_frame then
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if serirq='0' then -- count low cycles
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reg_v.low_count:=reg_v.low_count + 1;
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else -- see type of stop frame frame event
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if reg_v.low_count=x"2" then
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reg_v.irq_frame:=false;
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reg_v.irq_idle:=false; --enter active mode
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elsif reg_v.low_count>x"2" then
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reg_v.irq_idle:=true; --enter idle mode
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reg_v.irq_frame:=false;
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end if;
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reg_v.low_count:=(others=>'0');
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end if;
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end if;
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-- Design pattern
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-- drive register input signals
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reg_in<=reg_v;
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-- drive module outputs signals
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--port_comb_out<= reg_v.port_comb; --combinatorial output example
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--port_reg_out<= reg.port_reg; --registered output example
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comb_oe<=reg_v.serirq_oe; --cominatorial out
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end process;
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-- Pattern process 2, Registers
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regs : process (clock,reset_n)
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begin
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if reset_n='0' then
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reg.irq_idle<=true; -- start up in idle mode
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reg.irq_frame<=false; --start up out of irq frame
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reg.slot_count<=(others=>'0');
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reg.low_count<=(others=>'0');
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reg.irq_count<=(others=>'0');
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reg.irq_sync<='0';
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reg.serirq_oe<='0'; -- on reset all agents enter tristated mode
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elsif rising_edge(clock) then
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reg<=reg_in;
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end if;
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end process;
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end architecture RTL;
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