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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Usage:
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-- > as 10
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-- > run -all
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-- . Observe in_data_arr_p and the expected result and the result of the DUT in the Wave window
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-- . This TB verifies the DUT architecture that was compile last. Default after a fresh mk the (str)
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-- is compiled last, to simulate the (recursive) manually compile it and the simulate again.
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-- Within the recursive architecture it is not possible to explicitely configure it to recursively
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-- use the recursive architecture using FOR ALL : ENTITY because the instance label is within a
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-- generate block.
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-- . The p_verify makes the tb self checking and asserts when the results are not equal
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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ENTITY tb_common_adder_tree IS
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GENERIC (
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g_representation : STRING := "SIGNED";
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g_pipeline : NATURAL := 1; -- amount of pipelining per stage
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g_nof_inputs : NATURAL := 31; -- >= 1
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g_symbol_w : NATURAL := 8;
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g_sum_w : NATURAL := 8 -- worst case bit growth requires g_symbol_w + ceil_log2(g_nof_inputs);
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);
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END tb_common_adder_tree;
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ARCHITECTURE tb OF tb_common_adder_tree IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_data_vec_w : NATURAL := g_nof_inputs*g_symbol_w;
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CONSTANT c_nof_stages : NATURAL := ceil_log2(g_nof_inputs);
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CONSTANT c_pipeline_tree : NATURAL := g_pipeline*c_nof_stages;
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TYPE t_symbol_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_symbol_w-1 DOWNTO 0);
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-- Use the same symbol value g_nof_inputs time in the data_vec
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FUNCTION func_data_vec(symbol : INTEGER) RETURN STD_LOGIC_VECTOR IS
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VARIABLE v_data_vec : STD_LOGIC_VECTOR(c_data_vec_w-1 DOWNTO 0);
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BEGIN
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FOR I IN 0 TO g_nof_inputs-1 LOOP
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v_data_vec((I+1)*g_symbol_w-1 DOWNTO I*g_symbol_w) := TO_UVEC(symbol, g_symbol_w);
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END LOOP;
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RETURN v_data_vec;
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END;
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-- Calculate the expected result of the sum of the symbols in the data_vec
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FUNCTION func_result(data_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
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VARIABLE v_result : INTEGER;
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BEGIN
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v_result := 0;
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IF g_representation="SIGNED" THEN
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FOR I IN 0 TO g_nof_inputs-1 LOOP
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v_result := v_result + TO_SINT(data_vec((I+1)*g_symbol_w-1 DOWNTO I*g_symbol_w));
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END LOOP;
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v_result := RESIZE_SINT(v_result, g_sum_w);
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RETURN TO_SVEC(v_result, g_sum_w);
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ELSE
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FOR I IN 0 TO g_nof_inputs-1 LOOP
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v_result := v_result + TO_UINT(data_vec((I+1)*g_symbol_w-1 DOWNTO I*g_symbol_w));
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END LOOP;
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v_result := RESIZE_UINT(v_result, g_sum_w);
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RETURN TO_UVEC(v_result, g_sum_w);
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END IF;
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END;
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC := '1';
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL result_comb : STD_LOGIC_VECTOR(g_sum_w-1 DOWNTO 0); -- expected combinatorial sum
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SIGNAL in_data_vec : STD_LOGIC_VECTOR(c_data_vec_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL in_data_vec_p : STD_LOGIC_VECTOR(c_data_vec_w-1 DOWNTO 0);
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SIGNAL in_data_arr_p : t_symbol_arr(0 TO g_nof_inputs-1);
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SIGNAL result_expected : STD_LOGIC_VECTOR(g_sum_w-1 DOWNTO 0); -- expected pipelined sum
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SIGNAL result_dut : STD_LOGIC_VECTOR(g_sum_w-1 DOWNTO 0); -- DUT sum
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BEGIN
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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rst <= '1', '0' AFTER clk_period*3;
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p_stimuli : PROCESS
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BEGIN
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in_data_vec <= (OTHERS=>'0');
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proc_common_wait_until_low(clk, rst);
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proc_common_wait_some_cycles(clk, 5);
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-- Apply equal symbol value inputs
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FOR I IN 0 TO 2**g_symbol_w-1 LOOP
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in_data_vec <= func_data_vec(I);
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proc_common_wait_some_cycles(clk, 1);
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END LOOP;
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in_data_vec <= (OTHERS=>'0');
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proc_common_wait_some_cycles(clk, 50);
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tb_end <= '1';
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WAIT;
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END PROCESS;
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-- For easier manual analysis in the wave window:
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-- . Pipeline the in_data_vec to align with the result
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-- . Map the concatenated symbols in in_data_vec into an in_data_arr_p array
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u_data_vec_p : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => g_representation,
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g_pipeline => c_pipeline_tree,
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g_reset_value => 0,
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g_in_dat_w => c_data_vec_w,
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g_out_dat_w => c_data_vec_w
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_dat => in_data_vec,
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out_dat => in_data_vec_p
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);
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p_data_arr : PROCESS(in_data_vec_p)
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BEGIN
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FOR I IN 0 TO g_nof_inputs-1 LOOP
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in_data_arr_p(I) <= in_data_vec_p((I+1)*g_symbol_w-1 DOWNTO I*g_symbol_w);
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END LOOP;
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END PROCESS;
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result_comb <= func_result(in_data_vec);
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u_result : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => g_representation,
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g_pipeline => c_pipeline_tree,
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g_reset_value => 0,
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g_in_dat_w => g_sum_w,
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g_out_dat_w => g_sum_w
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_dat => result_comb,
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out_dat => result_expected
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);
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-- Using work.common_adder_tree(recursive) will only invoke the recursive architecture once, because the next recursive level will default to using the last compiled architecture
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-- Therefore only instatiatiate the DUT once in this tb and use compile order to influence which architecture is used.
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dut : ENTITY work.common_adder_tree -- uses last compile architecture
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GENERIC MAP (
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g_representation => g_representation,
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g_pipeline => g_pipeline,
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g_nof_inputs => g_nof_inputs,
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g_dat_w => g_symbol_w,
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g_sum_w => g_sum_w
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)
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PORT MAP (
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clk => clk,
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in_dat => in_data_vec,
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sum => result_dut
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);
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p_verify : PROCESS(rst, clk)
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BEGIN
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IF rst='0' THEN
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IF rising_edge(clk) THEN
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ASSERT result_dut = result_expected REPORT "Error: wrong result_dut" SEVERITY ERROR;
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END IF;
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END IF;
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END PROCESS;
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END tb;
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