OpenCores
URL https://opencores.org/ocsvn/astron_diagnostics/astron_diagnostics/trunk

Subversion Repositories astron_diagnostics

[/] [astron_diagnostics/] [trunk/] [diag_block_gen_reg.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 danv 
-----------------------------------------------------------------------------
2 
--
3 
-- Copyright (C) 2010
4 
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5 
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 
--
7 
-- This program is free software: you can redistribute it and/or modify
8 
-- it under the terms of the GNU General Public License as published by
9 
-- the Free Software Foundation, either version 3 of the License, or
10 
-- (at your option) any later version.
11 
--
12 
-- This program is distributed in the hope that it will be useful,
13 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
-- GNU General Public License for more details.
16 
--
17 
-- You should have received a copy of the GNU General Public License
18 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 
--
20 
-------------------------------------------------------------------------------
21 
 
22 
 
23 
library IEEE, common_pkg_lib, common_ram_lib, common_components_lib;
24 
use IEEE.std_logic_1164.ALL;
25 
use IEEE.numeric_std.ALL;
26 
use common_pkg_lib.common_pkg.ALL;
27 
use common_ram_lib.common_ram_pkg.ALL;
28 
use work.diag_pkg.ALL;
29 
 
30 
entity diag_block_gen_reg is
31 
  generic (
32 
    g_cross_clock_domain : boolean  := TRUE;    -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
33 
    g_diag_block_gen_rst : t_diag_block_gen := c_diag_block_gen_rst
34 
  );
35 
  port (
36 
    mm_rst  : in  std_logic;                   -- Clocks and reset
37 
    mm_clk  : in  std_logic;
38 
    dp_rst  : in  std_logic := '0';
39 
    dp_clk  : in  std_logic;
40 
    mm_mosi : in  t_mem_mosi;                  -- Memory Mapped Slave in mm_clk domain
41 
    mm_miso : out t_mem_miso       := c_mem_miso_rst;
42 
    bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
43 
  );
44 
end diag_block_gen_reg;
45 
 
46 
architecture rtl of diag_block_gen_reg is
47 
 
48 
  constant c_adrs_width : positive := c_diag_bg_reg_adr_w;
49 
  signal   mm_bg_ctrl   : t_diag_block_gen := g_diag_block_gen_rst;
50 
  signal   dp_bg_ctrl   : t_diag_block_gen := g_diag_block_gen_rst;
51 
 
52 
begin
53 
 
54 
  ------------------------------------------------------------------------------
55 
  -- MM register access in the mm_clk domain
56 
  -- . Hardcode the shared MM slave register directly in RTL instead of using
57 
  --   the common_reg_r_w instance. Directly using RTL is easier when the large
58 
  --   MM register has multiple different fields and with different read and
59 
  --   write options per field in one MM register.
60 
  ------------------------------------------------------------------------------
61 
 
62 
  p_mm_reg : process (mm_rst, mm_clk)
63 
  begin
64 
    if(mm_rst = '1') then
65 
      mm_miso    <= c_mem_miso_rst;
66 
      mm_bg_ctrl <= g_diag_block_gen_rst;
67 
    elsif(rising_edge(mm_clk)) then
68 
      -- Read access defaults
69 
      mm_miso.rdval <= '0';
70 
      -- Write access: set register value
71 
      if(mm_mosi.wr = '1') then
72 
        case TO_UINT(mm_mosi.address(c_adrs_width-1 downto 0)) is
73 
          when 0 =>
74 
            mm_bg_ctrl.enable                 <= mm_mosi.wrdata(0);
75 
            mm_bg_ctrl.enable_sync            <= mm_mosi.wrdata(1);
76 
          when 1 =>
77 
            mm_bg_ctrl.samples_per_packet     <= mm_mosi.wrdata(c_diag_bg_samples_per_packet_w -1 downto 0);
78 
          when 2 =>
79 
            mm_bg_ctrl.blocks_per_sync        <= mm_mosi.wrdata(c_diag_bg_blocks_per_sync_w    -1 downto 0);
80 
          when 3 =>
81 
            mm_bg_ctrl.gapsize                <= mm_mosi.wrdata(c_diag_bg_gapsize_w            -1 downto 0);
82 
          when 4 =>
83 
            mm_bg_ctrl.mem_low_adrs           <= mm_mosi.wrdata(c_diag_bg_mem_low_adrs_w       -1 downto 0);
84 
          when 5 =>
85 
            mm_bg_ctrl.mem_high_adrs          <= mm_mosi.wrdata(c_diag_bg_mem_high_adrs_w      -1 downto 0);
86 
          when 6 =>
87 
            mm_bg_ctrl.bsn_init(31 downto  0) <= mm_mosi.wrdata(31 downto 0);
88 
          when 7 =>
89 
            mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
90 
          when others => null;  -- not used MM addresses
91 
        end case;
92 
      -- Read access: get register value
93 
      elsif mm_mosi.rd = '1' then
94 
        mm_miso       <= c_mem_miso_rst;    -- set unused rddata bits to '0' when read
95 
        mm_miso.rdval <= '1';
96 
        case TO_UINT(mm_mosi.address(c_adrs_width-1 downto 0)) is
97 
          -- Read Block Sync
98 
          when 0 =>
99 
            mm_miso.rddata(0)                                          <= mm_bg_ctrl.enable;
100 
            mm_miso.rddata(1)                                          <= mm_bg_ctrl.enable_sync;
101 
          when 1 =>
102 
            mm_miso.rddata(c_diag_bg_samples_per_packet_w -1 downto 0) <= mm_bg_ctrl.samples_per_packet;
103 
          when 2 =>
104 
            mm_miso.rddata(c_diag_bg_blocks_per_sync_w    -1 downto 0) <= mm_bg_ctrl.blocks_per_sync;
105 
          when 3 =>
106 
            mm_miso.rddata(c_diag_bg_gapsize_w            -1 downto 0) <= mm_bg_ctrl.gapsize;
107 
          when 4 =>
108 
            mm_miso.rddata(c_diag_bg_mem_low_adrs_w       -1 downto 0) <= mm_bg_ctrl.mem_low_adrs;
109 
          when 5 =>
110 
            mm_miso.rddata(c_diag_bg_mem_high_adrs_w      -1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
111 
          when 6 =>
112 
            mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
113 
          when 7 =>
114 
            mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
115 
          when others => null;  -- not used MM addresses
116 
        end case;
117 
      end if;
118 
    end if;
119 
  end process;
120 
 
121 
  ------------------------------------------------------------------------------
122 
  -- Transfer register value between mm_clk and dp_clk domain.
123 
  -- If the function of the register ensures that the value will not be used
124 
  -- immediately when it was set, then the transfer between the clock domains
125 
  -- can be done by wires only. Otherwise if the change in register value can
126 
  -- have an immediate effect then the bit or word value needs to be transfered
127 
  -- using:
128 
  --
129 
  -- . common_async            --> for single-bit level signal
130 
  -- . common_spulse           --> for single-bit pulse signal
131 
  -- . common_reg_cross_domain --> for a multi-bit (a word) signal
132 
  --
133 
  -- Typically always use a crossing component for the single bit signals (to
134 
  -- be on the save side) and only use a crossing component for the word
135 
  -- signals if it is necessary (to avoid using more logic than necessary).
136 
  ------------------------------------------------------------------------------
137 
 
138 
  no_cross : if g_cross_clock_domain = FALSE generate
139 
    dp_bg_ctrl <= mm_bg_ctrl;
140 
  end generate;  -- no_cross
141 
 
142 
  gen_crossing : if g_cross_clock_domain = TRUE generate
143 
    -- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
144 
    -- the other diag BG control fields are stable as well
145 
    u_bg_enable : entity common_components_lib.common_async
146 
    generic map (
147 
      g_rst_level => '0'
148 
    )
149 
    port map (
150 
      rst  => dp_rst,
151 
      clk  => dp_clk,
152 
      din  => mm_bg_ctrl.enable,
153 
      dout => dp_bg_ctrl.enable
154 
    );
155 
    dp_bg_ctrl.enable_sync        <= mm_bg_ctrl.enable_sync;
156 
    dp_bg_ctrl.samples_per_packet <= mm_bg_ctrl.samples_per_packet;
157 
    dp_bg_ctrl.blocks_per_sync    <= mm_bg_ctrl.blocks_per_sync;
158 
    dp_bg_ctrl.gapsize            <= mm_bg_ctrl.gapsize;
159 
    dp_bg_ctrl.mem_low_adrs       <= mm_bg_ctrl.mem_low_adrs;
160 
    dp_bg_ctrl.mem_high_adrs      <= mm_bg_ctrl.mem_high_adrs;
161 
    dp_bg_ctrl.bsn_init           <= mm_bg_ctrl.bsn_init;
162 
  end generate;  -- gen_crossing
163 
 
164 
  bg_ctrl <= dp_bg_ctrl;
165 
 
166 
end rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.