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-----------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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library IEEE, common_pkg_lib, astron_ram_lib, common_components_lib;
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use IEEE.std_logic_1164.ALL;
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use IEEE.numeric_std.ALL;
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use common_pkg_lib.common_pkg.ALL;
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use astron_ram_lib.common_ram_pkg.ALL;
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use work.diag_pkg.ALL;
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entity diag_block_gen_reg is
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generic (
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g_cross_clock_domain : boolean := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
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g_diag_block_gen_rst : t_diag_block_gen := c_diag_block_gen_rst
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);
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port (
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mm_rst : in std_logic; -- Clocks and reset
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mm_clk : in std_logic;
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dp_rst : in std_logic := '0';
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dp_clk : in std_logic;
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mm_mosi : in t_mem_mosi; -- Memory Mapped Slave in mm_clk domain
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mm_miso : out t_mem_miso := c_mem_miso_rst;
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bg_ctrl : out t_diag_block_gen := g_diag_block_gen_rst
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);
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end diag_block_gen_reg;
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architecture rtl of diag_block_gen_reg is
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constant c_adrs_width : positive := c_diag_bg_reg_adr_w;
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signal mm_bg_ctrl : t_diag_block_gen := g_diag_block_gen_rst;
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signal dp_bg_ctrl : t_diag_block_gen := g_diag_block_gen_rst;
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begin
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------------------------------------------------------------------------------
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-- MM register access in the mm_clk domain
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-- . Hardcode the shared MM slave register directly in RTL instead of using
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-- the common_reg_r_w instance. Directly using RTL is easier when the large
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-- MM register has multiple different fields and with different read and
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-- write options per field in one MM register.
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------------------------------------------------------------------------------
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p_mm_reg : process (mm_rst, mm_clk)
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begin
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if(mm_rst = '1') then
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mm_miso <= c_mem_miso_rst;
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mm_bg_ctrl <= g_diag_block_gen_rst;
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elsif(rising_edge(mm_clk)) then
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-- Read access defaults
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mm_miso.rdval <= '0';
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-- Write access: set register value
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if(mm_mosi.wr = '1') then
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case TO_UINT(mm_mosi.address(c_adrs_width-1 downto 0)) is
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when 0 =>
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mm_bg_ctrl.enable <= mm_mosi.wrdata(0);
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mm_bg_ctrl.enable_sync <= mm_mosi.wrdata(1);
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when 1 =>
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mm_bg_ctrl.samples_per_packet <= mm_mosi.wrdata(c_diag_bg_samples_per_packet_w -1 downto 0);
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when 2 =>
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mm_bg_ctrl.blocks_per_sync <= mm_mosi.wrdata(c_diag_bg_blocks_per_sync_w -1 downto 0);
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when 3 =>
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mm_bg_ctrl.gapsize <= mm_mosi.wrdata(c_diag_bg_gapsize_w -1 downto 0);
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when 4 =>
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mm_bg_ctrl.mem_low_adrs <= mm_mosi.wrdata(c_diag_bg_mem_low_adrs_w -1 downto 0);
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when 5 =>
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mm_bg_ctrl.mem_high_adrs <= mm_mosi.wrdata(c_diag_bg_mem_high_adrs_w -1 downto 0);
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when 6 =>
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mm_bg_ctrl.bsn_init(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
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when 7 =>
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mm_bg_ctrl.bsn_init(63 downto 32) <= mm_mosi.wrdata(31 downto 0);
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when others => null; -- not used MM addresses
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end case;
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-- Read access: get register value
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elsif mm_mosi.rd = '1' then
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mm_miso <= c_mem_miso_rst; -- set unused rddata bits to '0' when read
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mm_miso.rdval <= '1';
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case TO_UINT(mm_mosi.address(c_adrs_width-1 downto 0)) is
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-- Read Block Sync
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when 0 =>
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mm_miso.rddata(0) <= mm_bg_ctrl.enable;
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mm_miso.rddata(1) <= mm_bg_ctrl.enable_sync;
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when 1 =>
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mm_miso.rddata(c_diag_bg_samples_per_packet_w -1 downto 0) <= mm_bg_ctrl.samples_per_packet;
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when 2 =>
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mm_miso.rddata(c_diag_bg_blocks_per_sync_w -1 downto 0) <= mm_bg_ctrl.blocks_per_sync;
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when 3 =>
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mm_miso.rddata(c_diag_bg_gapsize_w -1 downto 0) <= mm_bg_ctrl.gapsize;
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when 4 =>
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mm_miso.rddata(c_diag_bg_mem_low_adrs_w -1 downto 0) <= mm_bg_ctrl.mem_low_adrs;
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when 5 =>
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mm_miso.rddata(c_diag_bg_mem_high_adrs_w -1 downto 0) <= mm_bg_ctrl.mem_high_adrs;
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when 6 =>
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mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(31 downto 0);
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when 7 =>
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mm_miso.rddata(31 downto 0) <= mm_bg_ctrl.bsn_init(63 downto 32);
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when others => null; -- not used MM addresses
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end case;
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end if;
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end if;
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end process;
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------------------------------------------------------------------------------
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-- Transfer register value between mm_clk and dp_clk domain.
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-- If the function of the register ensures that the value will not be used
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-- immediately when it was set, then the transfer between the clock domains
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-- can be done by wires only. Otherwise if the change in register value can
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-- have an immediate effect then the bit or word value needs to be transfered
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-- using:
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--
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-- . common_async --> for single-bit level signal
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-- . common_spulse --> for single-bit pulse signal
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-- . common_reg_cross_domain --> for a multi-bit (a word) signal
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--
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-- Typically always use a crossing component for the single bit signals (to
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-- be on the save side) and only use a crossing component for the word
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-- signals if it is necessary (to avoid using more logic than necessary).
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------------------------------------------------------------------------------
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no_cross : if g_cross_clock_domain = FALSE generate
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dp_bg_ctrl <= mm_bg_ctrl;
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end generate; -- no_cross
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gen_crossing : if g_cross_clock_domain = TRUE generate
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-- Assume diag BG enable gets written last, so when diag BG enable is transfered properly to the dp_clk domain, then
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-- the other diag BG control fields are stable as well
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u_bg_enable : entity common_components_lib.common_async
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generic map (
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g_rst_level => '0'
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)
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port map (
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rst => dp_rst,
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clk => dp_clk,
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din => mm_bg_ctrl.enable,
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dout => dp_bg_ctrl.enable
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);
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dp_bg_ctrl.enable_sync <= mm_bg_ctrl.enable_sync;
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dp_bg_ctrl.samples_per_packet <= mm_bg_ctrl.samples_per_packet;
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dp_bg_ctrl.blocks_per_sync <= mm_bg_ctrl.blocks_per_sync;
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dp_bg_ctrl.gapsize <= mm_bg_ctrl.gapsize;
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dp_bg_ctrl.mem_low_adrs <= mm_bg_ctrl.mem_low_adrs;
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dp_bg_ctrl.mem_high_adrs <= mm_bg_ctrl.mem_high_adrs;
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dp_bg_ctrl.bsn_init <= mm_bg_ctrl.bsn_init;
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end generate; -- gen_crossing
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bg_ctrl <= dp_bg_ctrl;
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end rtl;
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