OpenCores
URL https://opencores.org/ocsvn/astron_diagnostics/astron_diagnostics/trunk

Subversion Repositories astron_diagnostics

[/] [astron_diagnostics/] [trunk/] [mms_diag_rx_seq.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 danv
 -------------------------------------------------------------------------------
2
--
3
-- Copyright (C) 2015
4
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5
-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
6
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
7
--
8
-- This program is free software: you can redistribute it and/or modify
9
-- it under the terms of the GNU General Public License as published by
10
-- the Free Software Foundation, either version 3 of the License, or
11
-- (at your option) any later version.
12
--
13
-- This program is distributed in the hope that it will be useful,
14
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
15
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
-- GNU General Public License for more details.
17
--
18
-- You should have received a copy of the GNU General Public License
19
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
20
--
21
-------------------------------------------------------------------------------
22
 
23
-- Purpose: Provide MM access via slave register to diag_rx_seq
24
-- Description:
25
--
26
--   Each DP stream has its own diag_rx_seq and its own MM control register.
27
--   The MM control registers are accessible via a single MM port thanks to
28
--   the common_mem_mux. Each single MM control register is defined as:
29
--
30
--   31             24 23             16 15              8 7               0  wi
31
--  |-----------------|-----------------|-----------------|-----------------|
32
--  |                                         diag_sel = [1], diag_en = [0] |  0  RW
33
--  |-----------------------------------------------------------------------|
34
--  |                                       res_val_n = [1], res_ok_n = [0] |  1  RO
35
--  |-----------------------------------------------------------------------|
36
--  |                                      rx_cnt[31:0]                     |  2  RO
37
--  |-----------------------------------------------------------------------|
38
--  |                              rx_sample[g_seq_dat_w-1:0]               |  3  RO
39
--  |-----------------------------------------------------------------------|
40
--  |                      diag_steps_arr[0][g_seq_dat_w-1:0]               |  4  RW
41
--  |-----------------------------------------------------------------------|
42
--  |                      diag_steps_arr[1][g_seq_dat_w-1:0]               |  5  RW
43
--  |-----------------------------------------------------------------------|
44
--  |                      diag_steps_arr[2][g_seq_dat_w-1:0]               |  6  RW
45
--  |-----------------------------------------------------------------------|
46
--  |                      diag_steps_arr[3][g_seq_dat_w-1:0]               |  7  RW
47
--  |-----------------------------------------------------------------------|
48
--
49
-- . g_nof_streams
50
--   The MM control register for stream I in 0:g_nof_streams-1 starts at word
51
--   index wi = I * 2**c_mm_reg.adr_w.
52
--
53
-- . diag_en
54
--     '0' = stop and reset input sequence verification
55
--     '1' = enable input sequence verification
56
--   
57
-- . diag_sel
58
--     '0' = verify PSRG data
59
--     '1' = verify CNTR data
60
--
61
-- . Results
62
--   When res_val_n = '1' then no valid data is being received. When
63
--   res_val_n = '0' then at least two valid data have been received so the
64
--   diag_rx_seq can detect whether the subsequent data is ok. When res_ok_n
65
--   = '0' then indeed all data that has been received so far is correct.
66
--   When res_ok_n = '1' then at least 1 data word was received with errors.
67
--   Once res_ok_n goes high it remains high.
68
--
69
-- . g_data_w and g_seq_dat_w
70
--   The DP streaming data field is c_dp_stream_data_w bits wide but only
71
--   g_data_w bits are used. The g_seq_dat_w must be >= 1 and <= g_data_w.
72
--   If g_seq_dat_w < g_data_w then the data carries replicated copies of 
73
--   the g_seq_dat_w. The maximum g_seq_dat_w depends on the pseudo random
74
--   data width of the LFSR sequeces in common_lfsr_sequences_pkg and on
75
--   whether timing closure can still be achieved for wider g_seq_dat_w.
76
--   Thanks to the replication a smaller g_seq_dat_w can be used to provide
77
--   CNTR or LFSR data for the DP data. If the higher bits do notmatch the 
78
--   sequence in the lower bits, then the rx data is forced to -1, and that
79
--   will then be detected and reported by u_diag_rx_seq as a sequence error.
80
--
81
-- . rx_cnt
82
--   Counts the number of valid input data that was received since diag_en
83
--   went active. An incrementing rx_cnt shows that data is being received.
84
--
85
-- . rx_sample
86
--   The rx_sample keeps the last valid in_dat value. When diag_en='0' it is
87
--   reset to 0. Reading rx_sample via MM gives an impression of the valid
88
--   in_dat activity.
89
--
90
-- . g_use_steps
91
--   When g_use_steps=FALSE then diag_sel selects whether PSRG or COUNTER
92
--   data with increment +1 is used to verify the input data.
93
--   When g_use_steps=TRUE then the g_nof_steps = 
94
--   c_diag_seq_rx_reg_nof_steps = 4 MM step registers define the allowed
95
--   COUNTER increment values.
96
 
97
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, mm_lib, common_ram_lib;
98
USE IEEE.std_logic_1164.ALL;
99
USE IEEE.numeric_std.ALL;
100
USE common_pkg_lib.common_pkg.ALL;
101
USE common_ram_lib.common_ram_pkg.ALL;
102
USE mm_lib.common_field_pkg.ALL;
103
USE dp_pkg_lib.dp_stream_pkg.ALL;
104
USE work.diag_pkg.ALL;
105
 
106
ENTITY mms_diag_rx_seq IS
107
  GENERIC (
108
    g_nof_streams : NATURAL := 1;
109
    g_use_steps   : BOOLEAN := FALSE;
110
    g_nof_steps   : NATURAL := c_diag_seq_rx_reg_nof_steps;
111
    g_seq_dat_w   : NATURAL := c_word_w;  -- >= 1, test sequence data width
112
    g_data_w      : NATURAL := c_word_w   -- >= g_seq_dat_w, user data width
113
  );
114
  PORT (
115
    -- Clocks and reset
116
    mm_rst         : IN  STD_LOGIC;  -- reset synchronous with mm_clk
117
    mm_clk         : IN  STD_LOGIC;  -- MM bus clock
118
    dp_rst         : IN  STD_LOGIC;  -- reset synchronous with dp_clk
119
    dp_clk         : IN  STD_LOGIC;  -- DP streaming bus clock
120
 
121
    -- Memory Mapped Slave
122
    reg_mosi       : IN  t_mem_mosi;   -- multiplexed port for g_nof_streams MM control/status registers
123
    reg_miso       : OUT t_mem_miso;
124
 
125
    -- Streaming interface
126
    rx_snk_in_arr  : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
127
  );
128
END mms_diag_rx_seq;
129
 
130
 
131
ARCHITECTURE str OF mms_diag_rx_seq IS
132
 
133
  -- Define MM slave register size
134
  CONSTANT c_mm_reg      : t_c_mem  := (latency  => 1,
135
                                        adr_w    => c_diag_seq_rx_reg_adr_w,
136
                                        dat_w    => c_word_w,                   -- Use MM bus data width = c_word_w = 32 for all MM registers
137
                                        nof_dat  => c_diag_seq_rx_reg_nof_dat,
138
                                        init_sl  => '0');
139
 
140
  -- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
141
  CONSTANT c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat-1 DOWNTO 0) := ( ( field_name_pad("step_3"),    "RW", c_word_w, field_default(0) ),   -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
142
                                                                                     ( field_name_pad("step_2"),    "RW", c_word_w, field_default(0) ),   -- [6] = diag_steps_arr[2]
143
                                                                                     ( field_name_pad("step_1"),    "RW", c_word_w, field_default(0) ),   -- [5] = diag_steps_arr[1]
144
                                                                                     ( field_name_pad("step_0"),    "RW", c_word_w, field_default(0) ),   -- [4] = diag_steps_arr[0]
145
                                                                                     ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ),   -- [3]
146
                                                                                     ( field_name_pad("rx_cnt"),    "RO", c_word_w, field_default(0) ),   -- [2]
147
                                                                                     ( field_name_pad("result"),    "RO",        2, field_default(0) ),   -- [1] = result[1:0]  = res_val_n & res_ok_n
148
                                                                                     ( field_name_pad("control"),   "RW",        2, field_default(0) ));  -- [0] = control[1:0] = diag_sel & diag_en
149
 
150
  CONSTANT c_reg_slv_w   : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
151
  CONSTANT c_reg_dat_w   : NATURAL := smallest(c_word_w, g_seq_dat_w);
152
 
153
  CONSTANT c_nof_steps_wi     : NATURAL := c_diag_seq_rx_reg_nof_steps_wi;
154
 
155
  TYPE t_reg_slv_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_reg_slv_w-1 DOWNTO 0);
156
  TYPE t_seq_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_seq_dat_w-1 DOWNTO 0);
157
  TYPE t_data_arr    IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
158
  TYPE t_steps_2arr  IS ARRAY (INTEGER RANGE <>) OF t_integer_arr(g_nof_steps-1 DOWNTO 0);
159
 
160
  SIGNAL reg_mosi_arr        : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
161
  SIGNAL reg_miso_arr        : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
162
 
163
  -- Registers in dp_clk domain
164
  SIGNAL ctrl_reg_arr        : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
165
  SIGNAL stat_reg_arr        : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
166
 
167
  SIGNAL diag_en_arr         : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
168
  SIGNAL diag_sel_arr        : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
169
  SIGNAL diag_steps_2arr     : t_steps_2arr(g_nof_streams-1 DOWNTO 0);
170
 
171
  SIGNAL rx_cnt_arr          : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);  -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
172
  SIGNAL rx_sample_arr       : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
173
  SIGNAL rx_sample_diff_arr  : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
174
  SIGNAL rx_sample_val_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
175
  SIGNAL rx_seq_arr          : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
176
  SIGNAL rx_seq_val_arr      : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
177
  SIGNAL rx_data_arr         : t_data_arr(g_nof_streams-1 DOWNTO 0);
178
  SIGNAL rx_data_val_arr     : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
179
 
180
  SIGNAL diag_res_arr        : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
181
  SIGNAL diag_res_val_arr    : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
182
 
183
  SIGNAL stat_res_ok_n_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
184
  SIGNAL stat_res_val_n_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
185
 
186
BEGIN
187
 
188
  ASSERT g_data_w >= g_seq_dat_w REPORT "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed." SEVERITY FAILURE;
189
 
190
  gen_nof_streams: FOR I IN 0 to g_nof_streams-1 GENERATE
191
 
192
    -- no unreplicate needed
193
    gen_one : IF g_data_w = g_seq_dat_w GENERATE
194
      rx_seq_arr(I)     <= rx_snk_in_arr(i).data(g_seq_dat_w-1 DOWNTO 0);
195
      rx_seq_val_arr(I) <= rx_snk_in_arr(i).valid;
196
    END GENERATE;
197
 
198
    -- unreplicate needed
199
    gen_unreplicate : IF g_data_w > g_seq_dat_w GENERATE
200
      -- keep sequence in low bits and set high bits to '1' if they mismatch the corresponding bit in the sequence
201
      rx_data_arr(I)     <= UNREPLICATE_DP_DATA(rx_snk_in_arr(i).data(g_data_w-1 DOWNTO 0), g_seq_dat_w);
202
      rx_data_val_arr(I) <=                     rx_snk_in_arr(i).valid;
203
 
204
      -- keep sequence in low bits if the high bits match otherwise force low bits value to -1 to indicate the mismatch
205
      p_rx_seq : PROCESS(dp_clk)
206
      BEGIN
207
        IF rising_edge(dp_clk) THEN  -- register to ease timing closure
208
          IF UNSIGNED(rx_data_arr(I)(g_data_w-1 DOWNTO g_seq_dat_w))=0 THEN
209
            rx_seq_arr(I) <= rx_data_arr(I)(g_seq_dat_w-1 DOWNTO 0);
210
          ELSE
211
            rx_seq_arr(I) <= TO_SVEC(-1, g_seq_dat_w);
212
          END IF;
213
          rx_seq_val_arr(I) <= rx_data_val_arr(I);
214
        END IF;
215
      END PROCESS;
216
    END GENERATE;
217
 
218
    -- detect rx sequence errors
219
    u_diag_rx_seq: ENTITY WORK.diag_rx_seq
220
    GENERIC MAP (
221
      g_use_steps       => g_use_steps,
222
      g_nof_steps       => g_nof_steps,
223
      g_cnt_w           => c_word_w,
224
      g_dat_w           => g_seq_dat_w,
225
      g_diag_res_w      => g_seq_dat_w  -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
226
    )
227
    PORT MAP (
228
      rst               => dp_rst,
229
      clk               => dp_clk,
230
 
231
      -- Write and read back registers:
232
      diag_en           => diag_en_arr(I),
233
      diag_sel          => diag_sel_arr(I),
234
      diag_steps_arr    => diag_steps_2arr(I),
235
 
236
      -- Read only registers:
237
      diag_res          => diag_res_arr(I),
238
      diag_res_val      => diag_res_val_arr(I),
239
      diag_sample       => rx_sample_arr(I),
240
      diag_sample_diff  => rx_sample_diff_arr(I),
241
      diag_sample_val   => rx_sample_val_arr(I),
242
 
243
      -- Streaming
244
      in_cnt            => rx_cnt_arr(I),
245
      in_dat            => rx_seq_arr(I),
246
      in_val            => rx_seq_val_arr(I)
247
    );
248
 
249
    -- Map diag_res to single bit and register it to ease timing closure
250
    stat_res_ok_n_arr(I)  <= orv(diag_res_arr(I))    WHEN rising_edge(dp_clk);
251
    stat_res_val_n_arr(I) <= NOT diag_res_val_arr(I) WHEN rising_edge(dp_clk);
252
 
253
    -- Register mapping
254
    -- . write ctrl_reg_arr
255
    diag_en_arr(I)   <= ctrl_reg_arr(I)(0);  -- address 0, data bit [0]
256
    diag_sel_arr(I)  <= ctrl_reg_arr(I)(1);  -- address 0, data bit [1]
257
 
258
    gen_diag_steps_2arr : FOR J IN 0 TO g_nof_steps-1 GENERATE
259
      diag_steps_2arr(I)(J) <= TO_SINT(ctrl_reg_arr(I)(c_reg_dat_w-1 + (c_nof_steps_wi+J)*c_word_w DOWNTO (c_nof_steps_wi+J)*c_word_w));  -- address 4, 5, 6, 7
260
    END GENERATE;
261
 
262
    -- . read stat_reg_arr
263
    p_stat_reg_arr : PROCESS(ctrl_reg_arr, stat_res_ok_n_arr, stat_res_val_n_arr, rx_cnt_arr, rx_sample_arr)
264
    BEGIN
265
      -- Default write / readback:
266
      stat_reg_arr(I) <= ctrl_reg_arr(I);                                        -- default control read back
267
      -- Status read only:
268
      stat_reg_arr(I)(                  0+1*c_word_w) <= stat_res_ok_n_arr(I);   -- address 1, data bit [0]
269
      stat_reg_arr(I)(                  1+1*c_word_w) <= stat_res_val_n_arr(I);  -- address 1, data bit [1]
270
      stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= rx_cnt_arr(I);          -- address 2: read rx_cnt per stream
271
      stat_reg_arr(I)(4*c_word_w-1 DOWNTO 3*c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w);  -- address 3: read valid sample per stream
272
    END PROCESS;
273
 
274
    u_reg : ENTITY mm_lib.common_reg_r_w_dc
275
    GENERIC MAP (
276
      g_cross_clock_domain => TRUE,
277
      g_readback           => FALSE,  -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
278
      g_reg                => c_mm_reg
279
    )
280
    PORT MAP (
281
      -- Clocks and reset
282
      mm_rst      => mm_rst,
283
      mm_clk      => mm_clk,
284
      st_rst      => dp_rst,
285
      st_clk      => dp_clk,
286
 
287
      -- Memory Mapped Slave in mm_clk domain
288
      sla_in      => reg_mosi_arr(I),
289
      sla_out     => reg_miso_arr(I),
290
 
291
      -- MM registers in dp_clk domain
292
      in_reg      => stat_reg_arr(I),
293
      out_reg     => ctrl_reg_arr(I)
294
    );
295
  END GENERATE;
296
 
297
  -- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
298
  u_mem_mux : ENTITY mm_lib.common_mem_mux
299
  GENERIC MAP (
300
    g_nof_mosi    => g_nof_streams,
301
    g_mult_addr_w => c_mm_reg.adr_w
302
  )
303
  PORT MAP (
304
    mosi     => reg_mosi,
305
    miso     => reg_miso,
306
    mosi_arr => reg_mosi_arr,
307
    miso_arr => reg_miso_arr
308
  );
309
 
310
END str;
311
 
312
 
313
 
314
 
315
 
316
 
317
 
318
 
319
 
320
 
321
 
322
 
323
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.