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1 2 danv
 -------------------------------------------------------------------------------
2
--
3 3 danv
-- Copyright 2020
4 2 danv
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 3 danv
-- 
7
-- Licensed under the Apache License, Version 2.0 (the "License");
8
-- you may not use this file except in compliance with the License.
9
-- You may obtain a copy of the License at
10
-- 
11
--     http://www.apache.org/licenses/LICENSE-2.0
12
-- 
13
-- Unless required by applicable law or agreed to in writing, software
14
-- distributed under the License is distributed on an "AS IS" BASIS,
15
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16
-- See the License for the specific language governing permissions and
17
-- limitations under the License.
18 2 danv
--
19
-------------------------------------------------------------------------------
20
 
21
-- Purpose: Provide MM access via slave register to diag_rx_seq
22
-- Description:
23
--
24
--   Each DP stream has its own diag_rx_seq and its own MM control register.
25
--   The MM control registers are accessible via a single MM port thanks to
26
--   the common_mem_mux. Each single MM control register is defined as:
27
--
28
--   31             24 23             16 15              8 7               0  wi
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--  |-----------------|-----------------|-----------------|-----------------|
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--  |                                         diag_sel = [1], diag_en = [0] |  0  RW
31
--  |-----------------------------------------------------------------------|
32
--  |                                       res_val_n = [1], res_ok_n = [0] |  1  RO
33
--  |-----------------------------------------------------------------------|
34
--  |                                      rx_cnt[31:0]                     |  2  RO
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--  |-----------------------------------------------------------------------|
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--  |                              rx_sample[g_seq_dat_w-1:0]               |  3  RO
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--  |-----------------------------------------------------------------------|
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--  |                      diag_steps_arr[0][g_seq_dat_w-1:0]               |  4  RW
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--  |-----------------------------------------------------------------------|
40
--  |                      diag_steps_arr[1][g_seq_dat_w-1:0]               |  5  RW
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--  |-----------------------------------------------------------------------|
42
--  |                      diag_steps_arr[2][g_seq_dat_w-1:0]               |  6  RW
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--  |-----------------------------------------------------------------------|
44
--  |                      diag_steps_arr[3][g_seq_dat_w-1:0]               |  7  RW
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--  |-----------------------------------------------------------------------|
46
--
47
-- . g_nof_streams
48
--   The MM control register for stream I in 0:g_nof_streams-1 starts at word
49
--   index wi = I * 2**c_mm_reg.adr_w.
50
--
51
-- . diag_en
52
--     '0' = stop and reset input sequence verification
53
--     '1' = enable input sequence verification
54
--   
55
-- . diag_sel
56
--     '0' = verify PSRG data
57
--     '1' = verify CNTR data
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--
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-- . Results
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--   When res_val_n = '1' then no valid data is being received. When
61
--   res_val_n = '0' then at least two valid data have been received so the
62
--   diag_rx_seq can detect whether the subsequent data is ok. When res_ok_n
63
--   = '0' then indeed all data that has been received so far is correct.
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--   When res_ok_n = '1' then at least 1 data word was received with errors.
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--   Once res_ok_n goes high it remains high.
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--
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-- . g_data_w and g_seq_dat_w
68
--   The DP streaming data field is c_dp_stream_data_w bits wide but only
69
--   g_data_w bits are used. The g_seq_dat_w must be >= 1 and <= g_data_w.
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--   If g_seq_dat_w < g_data_w then the data carries replicated copies of 
71
--   the g_seq_dat_w. The maximum g_seq_dat_w depends on the pseudo random
72
--   data width of the LFSR sequeces in common_lfsr_sequences_pkg and on
73
--   whether timing closure can still be achieved for wider g_seq_dat_w.
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--   Thanks to the replication a smaller g_seq_dat_w can be used to provide
75
--   CNTR or LFSR data for the DP data. If the higher bits do notmatch the 
76
--   sequence in the lower bits, then the rx data is forced to -1, and that
77
--   will then be detected and reported by u_diag_rx_seq as a sequence error.
78
--
79
-- . rx_cnt
80
--   Counts the number of valid input data that was received since diag_en
81
--   went active. An incrementing rx_cnt shows that data is being received.
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--
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-- . rx_sample
84
--   The rx_sample keeps the last valid in_dat value. When diag_en='0' it is
85
--   reset to 0. Reading rx_sample via MM gives an impression of the valid
86
--   in_dat activity.
87
--
88
-- . g_use_steps
89
--   When g_use_steps=FALSE then diag_sel selects whether PSRG or COUNTER
90
--   data with increment +1 is used to verify the input data.
91
--   When g_use_steps=TRUE then the g_nof_steps = 
92
--   c_diag_seq_rx_reg_nof_steps = 4 MM step registers define the allowed
93
--   COUNTER increment values.
94
 
95
LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, mm_lib, common_ram_lib;
96
USE IEEE.std_logic_1164.ALL;
97
USE IEEE.numeric_std.ALL;
98
USE common_pkg_lib.common_pkg.ALL;
99
USE common_ram_lib.common_ram_pkg.ALL;
100
USE mm_lib.common_field_pkg.ALL;
101
USE dp_pkg_lib.dp_stream_pkg.ALL;
102
USE work.diag_pkg.ALL;
103
 
104
ENTITY mms_diag_rx_seq IS
105
  GENERIC (
106
    g_nof_streams : NATURAL := 1;
107
    g_use_steps   : BOOLEAN := FALSE;
108
    g_nof_steps   : NATURAL := c_diag_seq_rx_reg_nof_steps;
109
    g_seq_dat_w   : NATURAL := c_word_w;  -- >= 1, test sequence data width
110
    g_data_w      : NATURAL := c_word_w   -- >= g_seq_dat_w, user data width
111
  );
112
  PORT (
113
    -- Clocks and reset
114
    mm_rst         : IN  STD_LOGIC;  -- reset synchronous with mm_clk
115
    mm_clk         : IN  STD_LOGIC;  -- MM bus clock
116
    dp_rst         : IN  STD_LOGIC;  -- reset synchronous with dp_clk
117
    dp_clk         : IN  STD_LOGIC;  -- DP streaming bus clock
118
 
119
    -- Memory Mapped Slave
120
    reg_mosi       : IN  t_mem_mosi;   -- multiplexed port for g_nof_streams MM control/status registers
121
    reg_miso       : OUT t_mem_miso;
122
 
123
    -- Streaming interface
124
    rx_snk_in_arr  : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0)
125
  );
126
END mms_diag_rx_seq;
127
 
128
 
129
ARCHITECTURE str OF mms_diag_rx_seq IS
130
 
131
  -- Define MM slave register size
132
  CONSTANT c_mm_reg      : t_c_mem  := (latency  => 1,
133
                                        adr_w    => c_diag_seq_rx_reg_adr_w,
134
                                        dat_w    => c_word_w,                   -- Use MM bus data width = c_word_w = 32 for all MM registers
135
                                        nof_dat  => c_diag_seq_rx_reg_nof_dat,
136
                                        init_sl  => '0');
137
 
138
  -- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
139
  CONSTANT c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat-1 DOWNTO 0) := ( ( field_name_pad("step_3"),    "RW", c_word_w, field_default(0) ),   -- [7] = diag_steps_arr[3], c_diag_seq_rx_reg_nof_steps = 4
140
                                                                                     ( field_name_pad("step_2"),    "RW", c_word_w, field_default(0) ),   -- [6] = diag_steps_arr[2]
141
                                                                                     ( field_name_pad("step_1"),    "RW", c_word_w, field_default(0) ),   -- [5] = diag_steps_arr[1]
142
                                                                                     ( field_name_pad("step_0"),    "RW", c_word_w, field_default(0) ),   -- [4] = diag_steps_arr[0]
143
                                                                                     ( field_name_pad("rx_sample"), "RO", c_word_w, field_default(0) ),   -- [3]
144
                                                                                     ( field_name_pad("rx_cnt"),    "RO", c_word_w, field_default(0) ),   -- [2]
145
                                                                                     ( field_name_pad("result"),    "RO",        2, field_default(0) ),   -- [1] = result[1:0]  = res_val_n & res_ok_n
146
                                                                                     ( field_name_pad("control"),   "RW",        2, field_default(0) ));  -- [0] = control[1:0] = diag_sel & diag_en
147
 
148
  CONSTANT c_reg_slv_w   : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
149
  CONSTANT c_reg_dat_w   : NATURAL := smallest(c_word_w, g_seq_dat_w);
150
 
151
  CONSTANT c_nof_steps_wi     : NATURAL := c_diag_seq_rx_reg_nof_steps_wi;
152
 
153
  TYPE t_reg_slv_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_reg_slv_w-1 DOWNTO 0);
154
  TYPE t_seq_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_seq_dat_w-1 DOWNTO 0);
155
  TYPE t_data_arr    IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_data_w-1 DOWNTO 0);
156
  TYPE t_steps_2arr  IS ARRAY (INTEGER RANGE <>) OF t_integer_arr(g_nof_steps-1 DOWNTO 0);
157
 
158
  SIGNAL reg_mosi_arr        : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
159
  SIGNAL reg_miso_arr        : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
160
 
161
  -- Registers in dp_clk domain
162
  SIGNAL ctrl_reg_arr        : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
163
  SIGNAL stat_reg_arr        : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
164
 
165
  SIGNAL diag_en_arr         : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
166
  SIGNAL diag_sel_arr        : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
167
  SIGNAL diag_steps_2arr     : t_steps_2arr(g_nof_streams-1 DOWNTO 0);
168
 
169
  SIGNAL rx_cnt_arr          : t_slv_32_arr(g_nof_streams-1 DOWNTO 0);  -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
170
  SIGNAL rx_sample_arr       : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
171
  SIGNAL rx_sample_diff_arr  : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
172
  SIGNAL rx_sample_val_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
173
  SIGNAL rx_seq_arr          : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
174
  SIGNAL rx_seq_val_arr      : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
175
  SIGNAL rx_data_arr         : t_data_arr(g_nof_streams-1 DOWNTO 0);
176
  SIGNAL rx_data_val_arr     : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
177
 
178
  SIGNAL diag_res_arr        : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
179
  SIGNAL diag_res_val_arr    : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
180
 
181
  SIGNAL stat_res_ok_n_arr   : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
182
  SIGNAL stat_res_val_n_arr  : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
183
 
184
BEGIN
185
 
186
  ASSERT g_data_w >= g_seq_dat_w REPORT "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed." SEVERITY FAILURE;
187
 
188
  gen_nof_streams: FOR I IN 0 to g_nof_streams-1 GENERATE
189
 
190
    -- no unreplicate needed
191
    gen_one : IF g_data_w = g_seq_dat_w GENERATE
192
      rx_seq_arr(I)     <= rx_snk_in_arr(i).data(g_seq_dat_w-1 DOWNTO 0);
193
      rx_seq_val_arr(I) <= rx_snk_in_arr(i).valid;
194
    END GENERATE;
195
 
196
    -- unreplicate needed
197
    gen_unreplicate : IF g_data_w > g_seq_dat_w GENERATE
198
      -- keep sequence in low bits and set high bits to '1' if they mismatch the corresponding bit in the sequence
199
      rx_data_arr(I)     <= UNREPLICATE_DP_DATA(rx_snk_in_arr(i).data(g_data_w-1 DOWNTO 0), g_seq_dat_w);
200
      rx_data_val_arr(I) <=                     rx_snk_in_arr(i).valid;
201
 
202
      -- keep sequence in low bits if the high bits match otherwise force low bits value to -1 to indicate the mismatch
203
      p_rx_seq : PROCESS(dp_clk)
204
      BEGIN
205
        IF rising_edge(dp_clk) THEN  -- register to ease timing closure
206
          IF UNSIGNED(rx_data_arr(I)(g_data_w-1 DOWNTO g_seq_dat_w))=0 THEN
207
            rx_seq_arr(I) <= rx_data_arr(I)(g_seq_dat_w-1 DOWNTO 0);
208
          ELSE
209
            rx_seq_arr(I) <= TO_SVEC(-1, g_seq_dat_w);
210
          END IF;
211
          rx_seq_val_arr(I) <= rx_data_val_arr(I);
212
        END IF;
213
      END PROCESS;
214
    END GENERATE;
215
 
216
    -- detect rx sequence errors
217
    u_diag_rx_seq: ENTITY WORK.diag_rx_seq
218
    GENERIC MAP (
219
      g_use_steps       => g_use_steps,
220
      g_nof_steps       => g_nof_steps,
221
      g_cnt_w           => c_word_w,
222
      g_dat_w           => g_seq_dat_w,
223
      g_diag_res_w      => g_seq_dat_w  -- do not use g_seq_dat_w+1 to include NOT diag_res_val in MSbit, instead use diag_res_val output
224
    )
225
    PORT MAP (
226
      rst               => dp_rst,
227
      clk               => dp_clk,
228
 
229
      -- Write and read back registers:
230
      diag_en           => diag_en_arr(I),
231
      diag_sel          => diag_sel_arr(I),
232
      diag_steps_arr    => diag_steps_2arr(I),
233
 
234
      -- Read only registers:
235
      diag_res          => diag_res_arr(I),
236
      diag_res_val      => diag_res_val_arr(I),
237
      diag_sample       => rx_sample_arr(I),
238
      diag_sample_diff  => rx_sample_diff_arr(I),
239
      diag_sample_val   => rx_sample_val_arr(I),
240
 
241
      -- Streaming
242
      in_cnt            => rx_cnt_arr(I),
243
      in_dat            => rx_seq_arr(I),
244
      in_val            => rx_seq_val_arr(I)
245
    );
246
 
247
    -- Map diag_res to single bit and register it to ease timing closure
248
    stat_res_ok_n_arr(I)  <= orv(diag_res_arr(I))    WHEN rising_edge(dp_clk);
249
    stat_res_val_n_arr(I) <= NOT diag_res_val_arr(I) WHEN rising_edge(dp_clk);
250
 
251
    -- Register mapping
252
    -- . write ctrl_reg_arr
253
    diag_en_arr(I)   <= ctrl_reg_arr(I)(0);  -- address 0, data bit [0]
254
    diag_sel_arr(I)  <= ctrl_reg_arr(I)(1);  -- address 0, data bit [1]
255
 
256
    gen_diag_steps_2arr : FOR J IN 0 TO g_nof_steps-1 GENERATE
257
      diag_steps_2arr(I)(J) <= TO_SINT(ctrl_reg_arr(I)(c_reg_dat_w-1 + (c_nof_steps_wi+J)*c_word_w DOWNTO (c_nof_steps_wi+J)*c_word_w));  -- address 4, 5, 6, 7
258
    END GENERATE;
259
 
260
    -- . read stat_reg_arr
261
    p_stat_reg_arr : PROCESS(ctrl_reg_arr, stat_res_ok_n_arr, stat_res_val_n_arr, rx_cnt_arr, rx_sample_arr)
262
    BEGIN
263
      -- Default write / readback:
264
      stat_reg_arr(I) <= ctrl_reg_arr(I);                                        -- default control read back
265
      -- Status read only:
266
      stat_reg_arr(I)(                  0+1*c_word_w) <= stat_res_ok_n_arr(I);   -- address 1, data bit [0]
267
      stat_reg_arr(I)(                  1+1*c_word_w) <= stat_res_val_n_arr(I);  -- address 1, data bit [1]
268
      stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= rx_cnt_arr(I);          -- address 2: read rx_cnt per stream
269
      stat_reg_arr(I)(4*c_word_w-1 DOWNTO 3*c_word_w) <= RESIZE_UVEC(rx_sample_arr(I), c_word_w);  -- address 3: read valid sample per stream
270
    END PROCESS;
271
 
272
    u_reg : ENTITY mm_lib.common_reg_r_w_dc
273
    GENERIC MAP (
274
      g_cross_clock_domain => TRUE,
275
      g_readback           => FALSE,  -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
276
      g_reg                => c_mm_reg
277
    )
278
    PORT MAP (
279
      -- Clocks and reset
280
      mm_rst      => mm_rst,
281
      mm_clk      => mm_clk,
282
      st_rst      => dp_rst,
283
      st_clk      => dp_clk,
284
 
285
      -- Memory Mapped Slave in mm_clk domain
286
      sla_in      => reg_mosi_arr(I),
287
      sla_out     => reg_miso_arr(I),
288
 
289
      -- MM registers in dp_clk domain
290
      in_reg      => stat_reg_arr(I),
291
      out_reg     => ctrl_reg_arr(I)
292
    );
293
  END GENERATE;
294
 
295
  -- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
296
  u_mem_mux : ENTITY mm_lib.common_mem_mux
297
  GENERIC MAP (
298
    g_nof_mosi    => g_nof_streams,
299
    g_mult_addr_w => c_mm_reg.adr_w
300
  )
301
  PORT MAP (
302
    mosi     => reg_mosi,
303
    miso     => reg_miso,
304
    mosi_arr => reg_mosi_arr,
305
    miso_arr => reg_miso_arr
306
  );
307
 
308
END str;
309
 
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