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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2015
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Provide MM access via slave register to diag_tx_seq
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-- Description:
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--
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-- Each DP stream has its own diag_tx_seq, because each stream can have its
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-- own flow control. Each DP stream also has its own MM control register to
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-- support reading tx_cnt per stream.
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--
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-- 31 24 23 16 15 8 7 0 wi
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-- |-----------------|-----------------|-----------------|-----------------|
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-- | diag_dc = [2], diag_sel = [1], diag_en = [0] | 0 RW
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-- |-----------------------------------------------------------------------|
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-- | diag_init[31:0] | 1 RW
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-- |-----------------------------------------------------------------------|
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-- | tx_cnt[31:0] | 2 RO
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-- |-----------------------------------------------------------------------|
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-- | diag_mod[31:0] | 3 RW
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-- |-----------------------------------------------------------------------|
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--
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-- . g_use_usr_input
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-- When diag_en='0' then the usr_sosi_arr input is passed on.
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-- When diag_en='1' then the the tx_seq data overrules the usr_sosi_arr. Dependent on g_use_usr_input
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-- the overule differs:
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--
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-- 1) When g_use_usr_input=TRUE then usr_sosi_arr().valid sets the pace else
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-- 2) when g_use_usr_input=FALSE then tx_src_in_arr().ready sets the pace of the valid output data.
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--
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-- This scheme allows filling user data with Tx seq data using the user valid or to completely
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-- overrule the user by deriving the Tx seq valid directly from the ready.
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--
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-- g_use_usr_input=FALSE :
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--
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-- g_nof_streams
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-- c_latency=1
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-- .
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-- .
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-- usr_snk_out_arr <-------------------/------------------------------ tx_src_in_arr
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-- usr_snk_in_arr --------------------|---------------->|\
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-- . | |0|
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-- ______ | | |---------> tx_src_out_arr
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-- | | |.ready | |
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-- |diag |<----/ |1|
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-- |tx_seq|---------------------->|/
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-- |______| . |
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-- __|___ . |
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-- |u_reg | tx_seq_src_in_arr |
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-- |______| tx_seq_src_out_arr |
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-- __|___ |
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-- | mux | diag_en_arr
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-- |______|
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-- |
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-- MM =================
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--
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--
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-- g_use_usr_input=TRUE :
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-- g_nof_streams
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-- c_latency=0
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-- .
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-- . ____
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-- usr_snk_out_arr ------------------------------------------------| |<-- tx_src_in_arr
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-- usr_snk_in_arr -----------------------\------------>|\ |dp |
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-- . | |0| |pipe|
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-- ______ valid | | |------->|line|--> tx_src_out_arr
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-- |diag |<-------/ |1| . |arr |
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-- |tx_seq|--------------------->|/ . |____|
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-- |______| . | .
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-- __|___ . | mux_seq_src_in_arr
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-- |u_reg | tx_seq_src_in_arr | mux_seq_src_out_arr
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-- |______| tx_seq_src_out_arr |
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-- __|___ |
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-- | mux | diag_en_arr
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-- |______|
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-- |
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-- MM =================
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--
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--
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-- . g_nof_streams
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-- The MM control register for stream I in 0:g_nof_streams-1 starts at word
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-- index wi = I * 2**c_mm_reg.adr_w.
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--
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-- . g_mm_broadcast
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-- Use default g_mm_broadcast=FALSE for multiplexed individual MM access to
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-- each reg_mosi_arr/reg_miso_arr MM port. When g_mm_broadcast=TRUE then a
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-- write access to MM port [0] is passed on to all ports and a read access
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-- is done from MM port [0]. The other MM array ports cannot be read then.
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--
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-- . g_seq_dat_w
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-- The g_seq_dat_w must be >= 1. The DP streaming data field is
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-- c_dp_stream_data_w bits wide and the REPLICATE_DP_DATA() is used to wire
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-- the g_seq_dat_w from the u_diag_tx_seq to fill the entire DP data width.
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-- The maximum g_seq_dat_w depends on the pseudo random data width of the
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-- LFSR sequeces in common_lfsr_sequences_pkg and on whether timing closure
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-- can still be achieved for wider g_seq_dat_w. Thanks to the replication a
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-- smaller g_seq_dat_w can be used to provide CNTR or LFSR data for the DP
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-- data.
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--
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-- . diag_en
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-- '0' = init and disable output sequence
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-- '1' = enable output sequence
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--
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-- . diag_sel
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-- '0' = generate PSRG data
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-- '1' = generate CNTR data
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--
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-- . diag_dc
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-- '0' = Output sequence data (as selected by diag_sel)
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-- '1' = Output constant data (value as set by diag_init)
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--
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-- . diag_init
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-- Note that MM diag_init has c_word_w=32 bits, so if g_seq_dat_w is wider
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-- then the MSbits are 0 and if it is smaller, then the MSbits are ignored.
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--
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-- . tx_cnt
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-- Counts the number of valid output data that was transmitted on stream 0
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-- since diag_en went active. An incrementing tx_cnt shows that data is
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-- being transmitted.
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--
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-- . diag_mod
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-- CNTR counts modulo diag_mod, so diag_mod becomes 0. Use diag_mod = 0
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-- for default binary wrap at 2**g_seq_dat_w. For diag_rx_seq choose
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-- diag_step = 2**g_seq_dat_w - diag_mod + g_cnt_incr to verify ok as
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-- simulated with tb_tb_diag_rx_seq. In this mms_diag_tx_seq g_cnt_incr=1
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-- fixed for diag_tx_seq.
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-- The default diag_mod=0 is equivalent to diag_mod=2**g_seq_dat_w.
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-- Using diag_mod < 2**g_seq_dat_w can be useful to generate tx seq CNTR
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-- data that is written to a memory that is larger than 2**g_seq_dat_w
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-- addresses. The CNTR values then differ from the memory address values,
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-- which can be useful to ensure that reading e.g. address 2**g_seq_dat_w
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-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, dp_pipeline_lib, common_ram_lib, mm_lib; -- init value for out_dat when diag_en = '0'
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE mm_lib.common_field_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE work.diag_pkg.ALL;
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ENTITY mms_diag_tx_seq IS
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GENERIC (
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g_use_usr_input : BOOLEAN := FALSE;
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g_mm_broadcast : BOOLEAN := FALSE;
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g_nof_streams : NATURAL := 1;
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g_seq_dat_w : NATURAL := c_word_w -- >= 1, test sequence data width
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);
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PORT (
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-- Clocks and reset
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mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
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mm_clk : IN STD_LOGIC; -- MM bus clock
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dp_rst : IN STD_LOGIC; -- reset synchronous with dp_clk
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dp_clk : IN STD_LOGIC; -- DP streaming bus clock
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-- MM interface
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reg_mosi : IN t_mem_mosi; -- single MM control register applied to all g_nof_streams
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reg_miso : OUT t_mem_miso;
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-- DP streaming interface
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usr_snk_out_arr : OUT t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
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usr_snk_in_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst);
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tx_src_out_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
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tx_src_in_arr : IN t_dp_siso_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_siso_rdy) -- Default xon='1';
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);
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END mms_diag_tx_seq;
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ARCHITECTURE str OF mms_diag_tx_seq IS
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-- Define MM slave register size
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CONSTANT c_mm_reg : t_c_mem := (latency => 1,
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adr_w => c_diag_seq_tx_reg_adr_w,
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dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
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nof_dat => c_diag_seq_tx_reg_nof_dat,
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init_sl => '0');
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-- Define MM slave register fields for Python peripheral using pi_common.py (specify MM register access per word, not per individual bit because mm_fields assumes 1 field per MM word)
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CONSTANT c_mm_reg_field_arr : t_common_field_arr(c_mm_reg.nof_dat-1 DOWNTO 0) := ( ( field_name_pad("modulo"), "RW", c_word_w, field_default(0) ),
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( field_name_pad("tx_cnt"), "RO", c_word_w, field_default(0) ),
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( field_name_pad("init"), "RW", c_word_w, field_default(0) ),
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( field_name_pad("control"), "RW", 3, field_default(0) )); -- control[2:0] = diag_dc & diag_sel & diag_en
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CONSTANT c_reg_slv_w : NATURAL := c_mm_reg.nof_dat*c_mm_reg.dat_w;
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CONSTANT c_latency : NATURAL := sel_a_b(g_use_usr_input, 0, 1); -- default 1 for registered diag_tx_seq out_cnt/dat/val output, use 0 for immediate combinatorial diag_tx_seq out_cnt/dat/val output
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TYPE t_reg_slv_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_reg_slv_w-1 DOWNTO 0);
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TYPE t_seq_dat_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(g_seq_dat_w-1 DOWNTO 0);
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TYPE t_replicate_arr IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(c_dp_stream_data_w-1 DOWNTO 0);
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SIGNAL reg_mosi_arr : t_mem_mosi_arr(g_nof_streams-1 DOWNTO 0);
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SIGNAL reg_miso_arr : t_mem_miso_arr(g_nof_streams-1 DOWNTO 0);
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-- Registers in dp_clk domain
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SIGNAL ctrl_reg_arr : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL stat_reg_arr : t_reg_slv_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL diag_en_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
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SIGNAL diag_sel_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
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SIGNAL diag_dc_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
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SIGNAL diag_init_mm_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
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SIGNAL diag_init_arr : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL diag_mod_mm_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0')); -- can use t_slv_32_arr because c -- init value for out_dat when diag_en = '0'_mm_reg.dat_w = c_word_w = 32 fixed
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SIGNAL diag_mod_arr : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>(OTHERS=>'0'));
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SIGNAL tx_cnt_arr : t_slv_32_arr(g_nof_streams-1 DOWNTO 0); -- can use t_slv_32_arr because c_mm_reg.dat_w = c_word_w = 32 fixed
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SIGNAL tx_dat_arr : t_seq_dat_arr(g_nof_streams-1 DOWNTO 0);
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SIGNAL tx_val_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
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SIGNAL tx_req_arr : STD_LOGIC_VECTOR(g_nof_streams-1 DOWNTO 0);
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SIGNAL tx_replicate_dat_arr : t_dp_data_slv_arr(g_nof_streams-1 DOWNTO 0);
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SIGNAL tx_seq_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0);
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SIGNAL tx_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0) := (OTHERS=>c_dp_sosi_rst); -- default set all other fields then data and valid to inactive.
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-- Use user input or self generate
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SIGNAL mux_seq_src_in_arr : t_dp_siso_arr(g_nof_streams-1 DOWNTO 0); -- multiplex user sosi control with tx_seq data
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SIGNAL mux_seq_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
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BEGIN
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gen_nof_streams: FOR I IN 0 to g_nof_streams-1 GENERATE
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u_diag_tx_seq: ENTITY WORK.diag_tx_seq
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GENERIC MAP (
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g_latency => c_latency,
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g_cnt_w => c_word_w,
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g_dat_w => g_seq_dat_w
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)
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PORT MAP (
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rst => dp_rst,
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clk => dp_clk,
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-- Write and read back registers:
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diag_en => diag_en_arr(I),
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diag_sel => diag_sel_arr(I),
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diag_dc => diag_dc_arr(I),
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diag_init => diag_init_arr(I),
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diag_mod => diag_mod_arr(I),
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-- Streaming
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diag_req => tx_req_arr(I),
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out_cnt => tx_cnt_arr(I),
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out_dat => tx_dat_arr(I),
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out_val => tx_val_arr(I)
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);
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tx_req_arr(I) <= tx_seq_src_in_arr(I).ready;
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tx_replicate_dat_arr(I) <= REPLICATE_DP_DATA(tx_dat_arr(I));
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-- for some reason the intermediate tx_replicate_dat_arr() signal is needed, otherwise the assignment to the tx_seq_src_out_arr().data field remains void in the Wave window
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tx_seq_src_out_arr(I).data <= tx_replicate_dat_arr(I);
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tx_seq_src_out_arr(I).valid <= tx_val_arr(I);
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-- Register mapping
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diag_en_arr(I) <= ctrl_reg_arr(I)( 0); -- address 0, data bit [0]
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diag_sel_arr(I) <= ctrl_reg_arr(I)( 1); -- address 0, data bit [1]
|
280 |
|
|
diag_dc_arr(I) <= ctrl_reg_arr(I)( 2); -- address 0, data bit [2]
|
281 |
|
|
diag_init_mm_arr(I) <= ctrl_reg_arr(I)(2*c_word_w-1 DOWNTO c_word_w); -- address 1, data bits [31:0]
|
282 |
|
|
diag_mod_mm_arr(I) <= ctrl_reg_arr(I)(4*c_word_w-1 DOWNTO 3*c_word_w); -- address 3, data bits [31:0]
|
283 |
|
|
|
284 |
|
|
diag_init_arr(I) <= RESIZE_UVEC(diag_init_mm_arr(I), g_seq_dat_w);
|
285 |
|
|
diag_mod_arr(I) <= RESIZE_UVEC(diag_mod_mm_arr(I), g_seq_dat_w);
|
286 |
|
|
|
287 |
|
|
p_stat_reg : PROCESS(ctrl_reg_arr(I), tx_cnt_arr)
|
288 |
|
|
BEGIN
|
289 |
|
|
-- Default write / readback:
|
290 |
|
|
stat_reg_arr(I) <= ctrl_reg_arr(I); -- address 0, 1: control read back
|
291 |
|
|
-- Status read only:
|
292 |
|
|
stat_reg_arr(I)(3*c_word_w-1 DOWNTO 2*c_word_w) <= tx_cnt_arr(I); -- address 2: read tx_cnt
|
293 |
|
|
END PROCESS;
|
294 |
|
|
|
295 |
|
|
u_reg : ENTITY mm_lib.common_reg_r_w_dc
|
296 |
|
|
GENERIC MAP (
|
297 |
|
|
g_cross_clock_domain => TRUE,
|
298 |
|
|
g_readback => FALSE, -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
|
299 |
|
|
g_reg => c_mm_reg
|
300 |
|
|
)
|
301 |
|
|
PORT MAP (
|
302 |
|
|
-- Clocks and reset
|
303 |
|
|
mm_rst => mm_rst,
|
304 |
|
|
mm_clk => mm_clk,
|
305 |
|
|
st_rst => dp_rst,
|
306 |
|
|
st_clk => dp_clk,
|
307 |
|
|
|
308 |
|
|
-- Memory Mapped Slave in mm_clk domain
|
309 |
|
|
sla_in => reg_mosi_arr(I),
|
310 |
|
|
sla_out => reg_miso_arr(I),
|
311 |
|
|
|
312 |
|
|
-- MM registers in dp_clk domain
|
313 |
|
|
in_reg => stat_reg_arr(I), -- connect out_reg to in_reg for write and readback register
|
314 |
|
|
out_reg => ctrl_reg_arr(I)
|
315 |
|
|
);
|
316 |
|
|
END GENERATE;
|
317 |
|
|
|
318 |
|
|
-- Combine the internal array of mm interfaces for the bg_data to one array that is connected to the port of the MM bus
|
319 |
|
|
u_mem_mux : ENTITY mm_lib.common_mem_mux
|
320 |
|
|
GENERIC MAP (
|
321 |
|
|
g_broadcast => g_mm_broadcast,
|
322 |
|
|
g_nof_mosi => g_nof_streams,
|
323 |
|
|
g_mult_addr_w => c_mm_reg.adr_w
|
324 |
|
|
)
|
325 |
|
|
PORT MAP (
|
326 |
|
|
mosi => reg_mosi,
|
327 |
|
|
miso => reg_miso,
|
328 |
|
|
mosi_arr => reg_mosi_arr,
|
329 |
|
|
miso_arr => reg_miso_arr
|
330 |
|
|
);
|
331 |
|
|
|
332 |
|
|
ignore_usr_input : IF g_use_usr_input=FALSE GENERATE
|
333 |
|
|
-- flow control
|
334 |
|
|
usr_snk_out_arr <= tx_src_in_arr;
|
335 |
|
|
tx_seq_src_in_arr <= tx_src_in_arr;
|
336 |
|
|
|
337 |
|
|
-- data
|
338 |
|
|
p_tx_src_out_arr : PROCESS (usr_snk_in_arr, tx_seq_src_out_arr, diag_en_arr)
|
339 |
|
|
BEGIN
|
340 |
|
|
tx_src_out_arr <= usr_snk_in_arr; -- Default pass on the usr data
|
341 |
|
|
FOR I IN 0 TO g_nof_streams-1 LOOP
|
342 |
|
|
IF diag_en_arr(I)='1' THEN
|
343 |
|
|
tx_src_out_arr(I) <= tx_seq_src_out_arr(I); -- When diag is enabled then pass on the Tx seq data
|
344 |
|
|
END IF;
|
345 |
|
|
END LOOP;
|
346 |
|
|
END PROCESS;
|
347 |
|
|
END GENERATE;
|
348 |
|
|
|
349 |
|
|
use_usr_input : IF g_use_usr_input=TRUE GENERATE
|
350 |
|
|
-- Request tx_seq data at user data valid rate
|
351 |
|
|
p_tx_seq_src_in_arr : PROCESS(usr_snk_in_arr)
|
352 |
|
|
BEGIN
|
353 |
|
|
FOR I IN 0 TO g_nof_streams-1 LOOP
|
354 |
|
|
tx_seq_src_in_arr(I).ready <= usr_snk_in_arr(I).valid;
|
355 |
|
|
END LOOP;
|
356 |
|
|
END PROCESS;
|
357 |
|
|
|
358 |
|
|
-- Default output the user input or BG data, else when tx_seq is enabled overrule output with tx_seq data
|
359 |
|
|
usr_snk_out_arr <= mux_seq_src_in_arr;
|
360 |
|
|
|
361 |
|
|
p_mux_seq_src_out_arr : PROCESS (usr_snk_in_arr, tx_seq_src_out_arr, diag_en_arr)
|
362 |
|
|
BEGIN
|
363 |
|
|
mux_seq_src_out_arr <= usr_snk_in_arr;
|
364 |
|
|
FOR I IN 0 TO g_nof_streams-1 LOOP
|
365 |
|
|
IF diag_en_arr(I)='1' THEN
|
366 |
|
|
mux_seq_src_out_arr(I).data <= tx_seq_src_out_arr(I).data;
|
367 |
|
|
END IF;
|
368 |
|
|
END LOOP;
|
369 |
|
|
END PROCESS;
|
370 |
|
|
|
371 |
|
|
-- Pipeline the streams by 1 to register the mux_seq_src_out_arr data to ease timing closure given that c_tx_seq_latency=0
|
372 |
|
|
u_dp_pipeline_arr : ENTITY dp_pipeline_lib.dp_pipeline_arr
|
373 |
|
|
GENERIC MAP (
|
374 |
|
|
g_nof_streams => g_nof_streams
|
375 |
|
|
)
|
376 |
|
|
PORT MAP (
|
377 |
|
|
rst => dp_rst,
|
378 |
|
|
clk => dp_clk,
|
379 |
|
|
-- ST sink
|
380 |
|
|
snk_out_arr => mux_seq_src_in_arr,
|
381 |
|
|
snk_in_arr => mux_seq_src_out_arr,
|
382 |
|
|
-- ST source
|
383 |
|
|
src_in_arr => tx_src_in_arr,
|
384 |
|
|
src_out_arr => tx_src_out_arr
|
385 |
|
|
);
|
386 |
|
|
END GENERATE;
|
387 |
|
|
|
388 |
|
|
END str;
|
389 |
|
|
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
|
394 |
|
|
|
395 |
|
|
|
396 |
|
|
|
397 |
|
|
|
398 |
|
|
|
399 |
|
|
|
400 |
|
|
|
401 |
|
|
|