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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Single clock FIFO
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LIBRARY IEEE, common_pkg_lib, common_components_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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ENTITY common_fifo_sc IS
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GENERIC (
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g_technology : NATURAL := 0; --c_tech_select_default;
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g_note_is_ful : BOOLEAN := TRUE; -- when TRUE report NOTE when FIFO goes full, fifo overflow is always reported as FAILURE
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g_fail_rd_emp : BOOLEAN := FALSE; -- when TRUE report FAILURE when read from an empty FIFO
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g_use_lut : BOOLEAN := FALSE; -- when TRUE then force using LUTs via Altera eab="OFF",
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-- else use default eab="ON" and ram_block_type="AUTO", default ram_block_type="AUTO" is sufficient, because
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-- there seems no need to force using RAM and there are two types of Stratix IV RAM (M9K and M144K)
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g_reset : BOOLEAN := FALSE; -- when TRUE release FIFO reset some cycles after rst release, else use rst directly
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g_init : BOOLEAN := FALSE; -- when TRUE force wr_req inactive for some cycles after FIFO reset release, else use wr_req as is
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g_dat_w : NATURAL := 36; -- 36 * 256 = 1 M9K
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g_nof_words : NATURAL := c_bram_m9k_fifo_depth;
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g_af_margin : NATURAL := 0 -- FIFO almost full margin for wr_aful flagging
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);
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PORT (
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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wr_dat : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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wr_req : IN STD_LOGIC;
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wr_ful : OUT STD_LOGIC;
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wr_aful : OUT STD_LOGIC; -- registered FIFO almost full flag
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rd_dat : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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rd_req : IN STD_LOGIC;
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rd_emp : OUT STD_LOGIC;
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rd_val : OUT STD_LOGIC;
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usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_nof_words)-1 DOWNTO 0)
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);
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END common_fifo_sc;
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ARCHITECTURE str OF common_fifo_sc IS
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CONSTANT c_use_eab : STRING := sel_a_b(g_use_lut, "OFF", "ON"); -- when g_use_lut=TRUE then force using LUTs via Altera eab="OFF", else default to ram_block_type = "AUTO"
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CONSTANT c_fifo_af_latency : NATURAL := 1; -- pipeline register wr_aful
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CONSTANT c_fifo_af_margin : NATURAL := g_af_margin+c_fifo_af_latency; -- FIFO almost full level
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SIGNAL fifo_rst : STD_LOGIC;
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SIGNAL fifo_init : STD_LOGIC;
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SIGNAL fifo_wr_en : STD_LOGIC;
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SIGNAL nxt_fifo_wr_en : STD_LOGIC;
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SIGNAL fifo_wr_dat : STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
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SIGNAL nxt_fifo_wr_dat : STD_LOGIC_VECTOR(fifo_wr_dat'RANGE);
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SIGNAL fifo_rd_en : STD_LOGIC;
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SIGNAL fifo_full : STD_LOGIC;
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SIGNAL fifo_empty : STD_LOGIC;
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SIGNAL fifo_usedw : STD_LOGIC_VECTOR(usedw'RANGE);
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SIGNAL nxt_wr_aful : STD_LOGIC;
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SIGNAL nxt_rd_val : STD_LOGIC;
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BEGIN
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-- Control logic copied from common_fifo_sc(virtex4).vhd
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gen_fifo_rst : IF g_reset=TRUE GENERATE
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-- Make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf). This is necessary in case
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-- the FIFO reset is also used functionally to flush it, so not only after power up.
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u_fifo_rst : ENTITY common_components_lib.common_areset
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GENERIC MAP (
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g_rst_level => '1',
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g_delay_len => 4
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)
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PORT MAP (
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in_rst => rst,
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clk => clk,
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out_rst => fifo_rst
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);
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END GENERATE;
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no_fifo_rst : IF g_reset=FALSE GENERATE
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fifo_rst <= rst;
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END GENERATE;
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gen_init : IF g_init=TRUE GENERATE
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-- Wait at least 3 cycles after reset release before allowing fifo_wr_en (see fifo_generator_ug175.pdf)
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u_fifo_init : ENTITY common_components_lib.common_areset
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GENERIC MAP (
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g_rst_level => '1',
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g_delay_len => 4
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)
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PORT MAP (
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in_rst => fifo_rst,
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clk => clk,
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out_rst => fifo_init
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);
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p_init_reg : PROCESS(fifo_rst, clk)
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BEGIN
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IF fifo_rst='1' THEN
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fifo_wr_en <= '0';
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ELSIF rising_edge(clk) THEN
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fifo_wr_dat <= nxt_fifo_wr_dat;
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fifo_wr_en <= nxt_fifo_wr_en;
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END IF;
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END PROCESS;
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nxt_fifo_wr_dat <= wr_dat;
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nxt_fifo_wr_en <= wr_req AND NOT fifo_init; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
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END GENERATE;
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no_init : IF g_init=FALSE GENERATE
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fifo_wr_dat <= wr_dat;
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fifo_wr_en <= wr_req; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
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END GENERATE;
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wr_ful <= fifo_full;
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rd_emp <= fifo_empty;
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usedw <= fifo_usedw;
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fifo_rd_en <= rd_req; -- check on NOT empty is not necessary according to fifo_generator_ds317.pdf, so skip it to easy synthesis timing
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nxt_rd_val <= fifo_rd_en AND NOT fifo_empty; -- check on NOT empty is necessary for rd_val
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nxt_wr_aful <= '0' WHEN TO_UINT(fifo_usedw)<g_nof_words-c_fifo_af_margin ELSE '1';
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p_clk : PROCESS(fifo_rst, clk)
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BEGIN
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IF fifo_rst='1' THEN
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wr_aful <= '0';
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rd_val <= '0';
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ELSIF rising_edge(clk) THEN
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wr_aful <= nxt_wr_aful;
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rd_val <= nxt_rd_val;
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END IF;
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END PROCESS;
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-- 0 < some threshold < usedw < g_nof_words can be used as FIFO almost_full
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-- 0 < usedw < some threshold < g_nof_words can be used as FIFO almost_empty
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danv |
u_fifo : ENTITY work.tech_fifo_sc
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danv |
GENERIC MAP (
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g_technology => g_technology,
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g_use_eab => c_use_eab,
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g_dat_w => g_dat_w,
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g_nof_words => g_nof_words
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)
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PORT MAP (
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aclr => fifo_rst,
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clock => clk,
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data => fifo_wr_dat,
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rdreq => fifo_rd_en,
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wrreq => fifo_wr_en,
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empty => fifo_empty,
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full => fifo_full,
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q => rd_dat,
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usedw => fifo_usedw
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);
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proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
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END str;
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