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--------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--------------------------------------------------------------------------------
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-- Purpose: DP FIFO for dual clock (= dc) domain wr and rd.
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-- Description: See dp_fifo_core.vhd.
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LIBRARY IEEE, common_pkg_lib, dp_pkg_lib, technology_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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ENTITY dp_fifo_dc IS
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_data_w : NATURAL := 16; -- Should be 2 times the c_complex_w if g_use_complex = TRUE
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g_bsn_w : NATURAL := 1;
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g_empty_w : NATURAL := 1;
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g_channel_w : NATURAL := 1;
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g_error_w : NATURAL := 1;
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g_use_bsn : BOOLEAN := FALSE;
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g_use_empty : BOOLEAN := FALSE;
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g_use_channel : BOOLEAN := FALSE;
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g_use_error : BOOLEAN := FALSE;
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g_use_sync : BOOLEAN := FALSE;
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g_use_ctrl : BOOLEAN := TRUE; -- sop & eop
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g_use_complex : BOOLEAN := FALSE; -- TRUE feeds the concatenated complex fields (im & re) through the FIFO instead of the data field.
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g_fifo_size : NATURAL := 512; -- (16+2) * 512 = 1 M9K, g_data_w+2 for sop and eop
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g_fifo_af_margin : NATURAL := 4; -- >=4, Nof words below max (full) at which fifo is considered almost full
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g_fifo_rl : NATURAL := 1
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);
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PORT (
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wr_rst : IN STD_LOGIC;
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wr_clk : IN STD_LOGIC;
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rd_rst : IN STD_LOGIC;
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rd_clk : IN STD_LOGIC;
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-- Monitor FIFO filling
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wr_ful : OUT STD_LOGIC;
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wr_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
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rd_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_fifo_size)-1 DOWNTO 0);
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rd_emp : OUT STD_LOGIC;
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-- ST sink
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snk_out : OUT t_dp_siso;
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snk_in : IN t_dp_sosi;
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-- ST source
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src_in : IN t_dp_siso;
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src_out : OUT t_dp_sosi
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);
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END dp_fifo_dc;
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ARCHITECTURE str OF dp_fifo_dc IS
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BEGIN
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u_dp_fifo_core : ENTITY work.dp_fifo_core
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GENERIC MAP (
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g_technology => g_technology,
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g_use_dual_clock => TRUE,
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g_data_w => g_data_w,
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g_bsn_w => g_bsn_w,
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g_empty_w => g_empty_w,
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g_channel_w => g_channel_w,
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g_error_w => g_error_w,
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g_use_bsn => g_use_bsn,
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g_use_empty => g_use_empty,
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g_use_channel => g_use_channel,
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g_use_error => g_use_error,
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g_use_sync => g_use_sync,
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g_use_ctrl => g_use_ctrl,
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g_use_complex => g_use_complex,
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g_fifo_size => g_fifo_size,
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g_fifo_af_margin => g_fifo_af_margin,
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g_fifo_rl => g_fifo_rl
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)
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PORT MAP (
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wr_rst => wr_rst,
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wr_clk => wr_clk,
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rd_rst => rd_rst,
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rd_clk => rd_clk,
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-- Monitor FIFO filling
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wr_ful => wr_ful,
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wr_usedw => wr_usedw,
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rd_usedw => rd_usedw,
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rd_emp => rd_emp,
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-- ST sink
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snk_out => snk_out,
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snk_in => snk_in,
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-- ST source
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src_in => src_in,
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src_out => src_out
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);
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END str;
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