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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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ENTITY tb_common_fifo_rd IS
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GENERIC (
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g_random_control : BOOLEAN := TRUE -- use TRUE for random rd_req control
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);
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END tb_common_fifo_rd;
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-- Run -all, observe rd_dat in wave window
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ARCHITECTURE tb OF tb_common_fifo_rd IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_dat_w : NATURAL := 16;
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CONSTANT c_fifo_rl : NATURAL := 1; -- FIFO has RL = 1
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CONSTANT c_read_rl : NATURAL := 0; -- show ahead FIFO has RL = 0
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL fifo_req : STD_LOGIC;
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SIGNAL fifo_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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SIGNAL fifo_val : STD_LOGIC;
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SIGNAL rd_req : STD_LOGIC;
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SIGNAL rd_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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SIGNAL rd_val : STD_LOGIC;
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SIGNAL enable : STD_LOGIC := '1';
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SIGNAL random : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL verify_en : STD_LOGIC := '1';
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SIGNAL prev_rd_req : STD_LOGIC;
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SIGNAL prev_rd_dat : STD_LOGIC_VECTOR(c_dat_w-1 DOWNTO 0);
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BEGIN
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rst <= '1', '0' AFTER clk_period*7;
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clk <= NOT clk OR tb_end AFTER clk_period/2;
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tb_end <= '0', '1' AFTER 20 us;
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verify_en <= '0', '1' AFTER clk_period*35;
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-- Model FIFO output with c_rl = 1 and counter data starting at 0
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proc_common_gen_data(c_fifo_rl, 0, rst, clk, enable, fifo_req, fifo_dat, fifo_val);
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-- Model rd_req
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random <= func_common_random(random) WHEN rising_edge(clk);
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rd_req <= random(random'HIGH) WHEN g_random_control=TRUE ELSE '1';
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-- Verify dut output incrementing data
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proc_common_verify_data(c_read_rl, clk, verify_en, rd_req, rd_val, rd_dat, prev_rd_dat);
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-- Verify dut output stream ready - valid relation, prev_rd_req is an auxiliary signal needed by the proc
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proc_common_verify_valid(c_read_rl, clk, verify_en, rd_req, prev_rd_req, rd_val);
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u_dut : ENTITY work.common_fifo_rd
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GENERIC MAP (
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g_dat_w => c_dat_w
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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-- ST sink: RL = 1
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fifo_req => fifo_req,
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fifo_dat => fifo_dat,
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fifo_val => fifo_val,
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-- ST source: RL = 0
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rd_req => rd_req,
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rd_dat => rd_dat,
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rd_val => rd_val
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);
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END tb;
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