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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee, technology_lib;
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USE ieee.std_logic_1164.all;
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USE work.tech_fifo_component_pkg.ALL;
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USE technology_lib.technology_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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LIBRARY ip_stratixiv_fifo_lib;
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--LIBRARY ip_arria10_fifo_lib;
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--LIBRARY ip_arria10_e3sge3_fifo_lib;
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--LIBRARY ip_arria10_e1sg_fifo_lib;
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ENTITY tech_fifo_dc IS
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_use_eab : STRING := "ON";
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g_dat_w : NATURAL;
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g_nof_words : NATURAL
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);
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PORT (
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aclr : IN STD_LOGIC := '0';
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data : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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rdclk : IN STD_LOGIC;
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rdreq : IN STD_LOGIC;
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wrclk : IN STD_LOGIC;
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wrreq : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
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rdempty : OUT STD_LOGIC;
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rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0);
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wrfull : OUT STD_LOGIC;
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wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
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);
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END tech_fifo_dc;
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ARCHITECTURE str OF tech_fifo_dc IS
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BEGIN
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gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
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u0 : ip_stratixiv_fifo_dc
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GENERIC MAP (g_dat_w, g_nof_words)
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PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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END GENERATE;
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-- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
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-- u0 : ip_arria10_fifo_dc
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-- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
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-- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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-- END GENERATE;
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--
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-- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
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-- u0 : ip_arria10_e3sge3_fifo_dc
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-- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
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-- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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-- END GENERATE;
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--
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-- gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
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-- u0 : ip_arria10_e1sg_fifo_dc
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-- GENERIC MAP (g_use_eab, g_dat_w, g_nof_words)
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-- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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-- END GENERATE;
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END ARCHITECTURE;
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