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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2014
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee, technology_lib;
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USE ieee.std_logic_1164.all;
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USE work.tech_fifo_component_pkg.ALL;
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USE technology_lib.technology_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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LIBRARY ip_stratixiv_fifo_lib;
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--LIBRARY ip_arria10_fifo_lib;
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--LIBRARY ip_arria10_e3sge3_fifo_lib;
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--LIBRARY ip_arria10_e1sg_fifo_lib;
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ENTITY tech_fifo_dc_mixed_widths IS
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_nof_words : NATURAL; -- FIFO size in nof wr_dat words
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g_wrdat_w : NATURAL;
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g_rddat_w : NATURAL
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);
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PORT (
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aclr : IN STD_LOGIC := '0';
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data : IN STD_LOGIC_VECTOR (g_wrdat_w-1 DOWNTO 0);
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rdclk : IN STD_LOGIC;
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rdreq : IN STD_LOGIC;
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wrclk : IN STD_LOGIC;
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wrreq : IN STD_LOGIC;
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q : OUT STD_LOGIC_VECTOR (g_rddat_w-1 DOWNTO 0);
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rdempty : OUT STD_LOGIC;
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rdusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words*g_wrdat_w/g_rddat_w)-1 DOWNTO 0);
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wrfull : OUT STD_LOGIC;
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wrusedw : OUT STD_LOGIC_VECTOR (tech_ceil_log2(g_nof_words)-1 DOWNTO 0)
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);
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END tech_fifo_dc_mixed_widths;
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ARCHITECTURE str OF tech_fifo_dc_mixed_widths IS
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BEGIN
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gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
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u0 : ip_stratixiv_fifo_dc_mixed_widths
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GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
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PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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END GENERATE;
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-- gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
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-- u0 : ip_arria10_fifo_dc_mixed_widths
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-- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
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-- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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-- END GENERATE;
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--
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-- gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
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-- u0 : ip_arria10_e3sge3_fifo_dc_mixed_widths
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-- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
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-- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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-- END GENERATE;
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--
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-- gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
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-- u0 : ip_arria10_e1sg_fifo_dc_mixed_widths
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-- GENERIC MAP (g_nof_words, g_wrdat_w, g_rddat_w)
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-- PORT MAP (aclr, data, rdclk, rdreq, wrclk, wrreq, q, rdempty, rdusedw, wrfull, wrusedw);
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-- END GENERATE;
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END ARCHITECTURE;
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