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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2010
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, common_ram_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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-- Purpose: Get in_dat from in_clk to out_clk domain when in_new is asserted.
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-- Remarks:
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-- . If in_new is a pulse, then new in_dat is available after g_in_new_latency.
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-- . It is also allowed to hold in_new high, then out_new will pulse once for
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-- every 24 out_clk cycles.
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-- . Use in_done to be sure that in_dat due to in_new has crossed the clock
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-- domain, in case of multiple in_new pulses in a row the in_done will only
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-- pulse when this state remains s_idle, so after the last in_new.
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-- . If the in_dat remains unchanged during the crossing of in_new to out_en
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-- then g_input_buf=FALSE may be used to save some flipflops
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ENTITY common_reg_cross_domain IS
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GENERIC (
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g_input_buf : BOOLEAN := TRUE;
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g_in_new_latency : NATURAL := 0; -- >= 0
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g_out_dat_init : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
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);
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PORT (
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in_rst : IN STD_LOGIC;
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in_clk : IN STD_LOGIC;
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in_new : IN STD_LOGIC := '1'; -- when '1' then new in_dat is available after g_in_new_latency
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in_dat : IN STD_LOGIC_VECTOR;
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in_done : OUT STD_LOGIC; -- pulses when no more pending in_new
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out_rst : IN STD_LOGIC;
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out_clk : IN STD_LOGIC;
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out_dat : OUT STD_LOGIC_VECTOR;
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out_new : OUT STD_LOGIC -- when '1' then the out_dat was updated with in_dat due to in_new
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);
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END common_reg_cross_domain;
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ARCHITECTURE rtl OF common_reg_cross_domain IS
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CONSTANT c_dat : STD_LOGIC_VECTOR(in_dat'RANGE) := g_out_dat_init(in_dat'RANGE);
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------------------------------------------------------------------------------
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-- in_clk domain
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------------------------------------------------------------------------------
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SIGNAL reg_new : STD_LOGIC_VECTOR(0 TO g_in_new_latency) := (OTHERS=>'0');
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SIGNAL nxt_reg_new : STD_LOGIC_VECTOR(reg_new'RANGE);
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SIGNAL in_buf : STD_LOGIC_VECTOR(c_dat'RANGE) := c_dat;
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SIGNAL in_buf_reg : STD_LOGIC_VECTOR(c_dat'RANGE) := c_dat;
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SIGNAL nxt_in_buf_reg : STD_LOGIC_VECTOR(c_dat'RANGE);
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-- Register access clock domain crossing
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TYPE t_state_enum IS (s_idle, s_busy);
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SIGNAL cross_req : STD_LOGIC;
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SIGNAL cross_busy : STD_LOGIC;
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SIGNAL nxt_in_done : STD_LOGIC;
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SIGNAL state : t_state_enum;
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SIGNAL nxt_state : t_state_enum;
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SIGNAL prev_state : t_state_enum;
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SIGNAL in_new_hold : STD_LOGIC;
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SIGNAL nxt_in_new_hold : STD_LOGIC;
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------------------------------------------------------------------------------
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-- out_clk domain
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------------------------------------------------------------------------------
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SIGNAL out_en : STD_LOGIC;
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SIGNAL i_out_dat : STD_LOGIC_VECTOR(c_dat'RANGE) := c_dat; -- register init without physical reset
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SIGNAL nxt_out_dat : STD_LOGIC_VECTOR(c_dat'RANGE);
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BEGIN
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out_dat <= i_out_dat;
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------------------------------------------------------------------------------
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-- in_clk domain
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------------------------------------------------------------------------------
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reg_new(0) <= in_new;
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gen_latency : IF g_in_new_latency>0 GENERATE
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p_reg_new : PROCESS(in_rst, in_clk)
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BEGIN
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IF in_rst='1' THEN
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reg_new(1 TO g_in_new_latency) <= (OTHERS=>'0');
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ELSIF rising_edge(in_clk) THEN
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reg_new(1 TO g_in_new_latency) <= nxt_reg_new(1 TO g_in_new_latency);
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END IF;
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END PROCESS;
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nxt_reg_new(1 TO g_in_new_latency) <= reg_new(0 TO g_in_new_latency-1);
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END GENERATE;
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p_in_clk : PROCESS(in_rst, in_clk)
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BEGIN
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IF in_rst='1' THEN
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in_new_hold <= '0';
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in_done <= '0';
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state <= s_idle;
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prev_state <= s_idle;
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ELSIF rising_edge(in_clk) THEN
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in_buf_reg <= nxt_in_buf_reg;
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in_new_hold <= nxt_in_new_hold;
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in_done <= nxt_in_done;
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state <= nxt_state;
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prev_state <= state;
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END IF;
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END PROCESS;
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-- capture the new register data
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no_in_buf : IF g_input_buf=FALSE GENERATE
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in_buf <= in_dat; -- assumes that in_dat remains unchanged during the crossing of in_new to out_en
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END GENERATE;
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gen_in_buf : IF g_input_buf=TRUE GENERATE
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nxt_in_buf_reg <= in_dat WHEN cross_req='1' ELSE in_buf_reg;
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in_buf <= in_buf_reg;
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END GENERATE;
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-- handshake control of the clock domain crossing by u_cross_req
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-- hold any subsequent in_new during cross domain busy to ensure that the out_dat will get the latest value of in_dat
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p_state : PROCESS(state, prev_state, reg_new, in_new_hold, cross_busy)
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BEGIN
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cross_req <= '0';
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nxt_in_done <= '0';
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nxt_in_new_hold <= in_new_hold;
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nxt_state <= state;
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CASE state IS
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WHEN s_idle =>
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nxt_in_new_hold <= '0';
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IF reg_new(g_in_new_latency)='1' OR in_new_hold='1' THEN
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cross_req <= '1';
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nxt_state <= s_busy;
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ELSIF UNSIGNED(reg_new)=0 AND prev_state=s_busy THEN
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nxt_in_done <= '1'; -- no pending in_new at input or in shift register and just left s_busy, so signal in_done
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END IF;
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WHEN OTHERS => -- s_busy
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IF reg_new(g_in_new_latency)='1' THEN
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nxt_in_new_hold <= '1';
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END IF;
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IF cross_busy='0' THEN
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nxt_state <= s_idle;
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END IF;
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END CASE;
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END PROCESS;
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------------------------------------------------------------------------------
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-- cross clock domain
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------------------------------------------------------------------------------
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u_cross_req : ENTITY common_components_lib.common_spulse
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PORT MAP (
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in_rst => in_rst,
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in_clk => in_clk,
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in_pulse => cross_req,
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in_busy => cross_busy,
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out_rst => out_rst,
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out_clk => out_clk,
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out_pulse => out_en
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);
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------------------------------------------------------------------------------
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-- out_clk domain
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------------------------------------------------------------------------------
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p_out_clk : PROCESS(out_rst, out_clk)
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BEGIN
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IF out_rst='1' THEN
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out_new <= '0';
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ELSIF rising_edge(out_clk) THEN
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i_out_dat <= nxt_out_dat;
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out_new <= out_en;
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END IF;
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END PROCESS;
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-- some clock cycles after the cross_req the in_buf data is stable for sure
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nxt_out_dat <= in_buf WHEN out_en='1' ELSE i_out_dat;
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END rtl;
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