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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Provide dual clock domain crossing to common_reg_r_w.vhd
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-- Description:
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-- . Write vector to out_reg
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-- . Read vector from in_reg or readback from out_reg
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--
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-- 31 24 23 16 15 8 7 0 wi
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-- |-----------------|-----------------|-----------------|-----------------|
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-- | data[31:0] | 0
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-- |-----------------------------------------------------------------------|
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-- | data[63:32] | 1
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-- |-----------------------------------------------------------------------|
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--
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-- . g_readback
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-- When g_readback is TRUE then the written data is read back from the st_clk
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-- domain directly into the mm_clk domain, so without ST --> MM clock domain
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-- crossing logic. This is allowed because the read back value is stable.
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-- For readback the out_reg needs to be connected to in_reg, independent of
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-- the g_readback setting, because the readback value is read back from the
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-- st_clk domain. In this way the readback value also reveals that the
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-- written value is indeed available in the st_clk domain (ie. this shows
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-- that the st_clk is active). If g_cross_clock_domain=FALSE, then g_readback
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-- is don't care.
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-- In fact g_readback could better be called g_st_readback. An alternative
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-- g_mm_readback could define direct read back in the MM clock domain and
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-- would allow leaving the in_reg not connected.
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LIBRARY IEEE, common_pkg_lib, common_components_lib, common_ram_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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ENTITY common_reg_r_w_dc IS
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GENERIC (
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g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
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g_in_new_latency : NATURAL := 0; -- >= 0
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g_readback : BOOLEAN := FALSE; -- must use FALSE for write/read or read only register when g_cross_clock_domain=TRUE
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--g_readback : BOOLEAN := TRUE; -- can use TRUE for write and readback register
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g_reg : t_c_mem := c_mem_reg;
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g_init_reg : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
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);
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PORT (
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-- Clocks and reset
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mm_rst : IN STD_LOGIC; -- reset synchronous with mm_clk
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mm_clk : IN STD_LOGIC; -- memory-mapped bus clock
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st_rst : IN STD_LOGIC; -- reset synchronous with st_clk
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st_clk : IN STD_LOGIC; -- other clock domain clock
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-- Memory Mapped Slave in mm_clk domain
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sla_in : IN t_mem_mosi; -- actual ranges defined by g_reg
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sla_out : OUT t_mem_miso; -- actual ranges defined by g_reg
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-- MM registers in st_clk domain
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reg_wr_arr : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
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reg_rd_arr : OUT STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
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in_new : IN STD_LOGIC := '1';
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in_reg : IN STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
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out_reg : OUT STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
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out_new : OUT STD_LOGIC -- Pulses '1' when new data has been written.
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);
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END common_reg_r_w_dc;
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ARCHITECTURE str OF common_reg_r_w_dc IS
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-- Registers in mm_clk domain
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SIGNAL vector_wr_arr : STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
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SIGNAL vector_rd_arr : STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
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SIGNAL out_vector : STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
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SIGNAL in_vector : STD_LOGIC_VECTOR(g_reg.dat_w*g_reg.nof_dat-1 DOWNTO 0);
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-- Initialize output to avoid Warning: (vsim-8684) No drivers exist on out port *, and its initial value is not used
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SIGNAL i_sla_out : t_mem_miso := c_mem_miso_rst;
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SIGNAL reg_wr_arr_i : STD_LOGIC_VECTOR( g_reg.nof_dat-1 DOWNTO 0);
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SIGNAL wr_pulse : STD_LOGIC;
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SIGNAL toggle : STD_LOGIC;
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SIGNAL out_new_i : STD_LOGIC;
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BEGIN
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------------------------------------------------------------------------------
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-- MM register access in the mm_clk domain
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------------------------------------------------------------------------------
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sla_out <= i_sla_out;
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u_reg : ENTITY work.common_reg_r_w
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GENERIC MAP (
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g_reg => g_reg,
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g_init_reg => g_init_reg
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)
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PORT MAP (
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rst => mm_rst,
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clk => mm_clk,
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-- control side
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wr_en => sla_in.wr,
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wr_adr => sla_in.address(g_reg.adr_w-1 DOWNTO 0),
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wr_dat => sla_in.wrdata(g_reg.dat_w-1 DOWNTO 0),
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rd_en => sla_in.rd,
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rd_adr => sla_in.address(g_reg.adr_w-1 DOWNTO 0),
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rd_dat => i_sla_out.rddata(g_reg.dat_w-1 DOWNTO 0),
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rd_val => i_sla_out.rdval,
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-- data side
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reg_wr_arr => vector_wr_arr,
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reg_rd_arr => vector_rd_arr,
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out_reg => out_vector,
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in_reg => in_vector
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);
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------------------------------------------------------------------------------
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-- Transfer register value between mm_clk and st_clk domain.
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-- If the function of the register ensures that the value will not be used
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-- immediately when it was set, then the transfer between the clock domains
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-- can be done by wires only. Otherwise if the change in register value can
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-- have an immediate effect then the bit or word value needs to be transfered
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-- using:
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--
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-- . common_async --> for single-bit level signal
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-- . common_spulse --> for single-bit pulse signal
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-- . common_reg_cross_domain --> for a multi-bit (a word) signal
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--
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-- Typically always use a crossing component for the single bit signals (to
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-- be on the save side) and only use a crossing component for the word
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-- signals if it is necessary (to avoid using more logic than necessary).
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------------------------------------------------------------------------------
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no_cross : IF g_cross_clock_domain = FALSE GENERATE
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in_vector <= in_reg;
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out_reg <= out_vector;
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reg_wr_arr <= vector_wr_arr;
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reg_rd_arr <= vector_rd_arr;
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out_new <= vector_wr_arr(0);
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END GENERATE; -- no_cross
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gen_cross : IF g_cross_clock_domain = TRUE GENERATE
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gen_rdback : IF g_readback=TRUE GENERATE
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in_vector <= in_reg;
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END GENERATE;
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gen_rd : IF g_readback=FALSE GENERATE
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u_in_vector : ENTITY work.common_reg_cross_domain
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GENERIC MAP (
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g_in_new_latency => g_in_new_latency
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)
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PORT MAP (
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in_rst => st_rst,
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in_clk => st_clk,
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in_new => in_new,
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in_dat => in_reg,
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in_done => OPEN,
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out_rst => mm_rst,
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out_clk => mm_clk,
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out_dat => in_vector,
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out_new => OPEN
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);
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END GENERATE;
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u_out_reg : ENTITY work.common_reg_cross_domain
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GENERIC MAP(
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g_out_dat_init => g_init_reg
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)
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PORT MAP (
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in_rst => mm_rst,
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in_clk => mm_clk,
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in_dat => out_vector,
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in_done => OPEN,
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out_rst => st_rst,
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out_clk => st_clk,
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out_dat => out_reg,
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out_new => out_new_i
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);
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u_toggle : ENTITY common_components_lib.common_switch
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GENERIC MAP (
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g_rst_level => '0',
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g_priority_lo => FALSE,
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g_or_high => FALSE,
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g_and_low => FALSE
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)
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PORT MAP (
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rst => st_rst,
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clk => st_clk,
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switch_high => wr_pulse,
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switch_low => out_new_i,
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out_level => toggle
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);
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wr_pulse <= '0' WHEN vector_or(reg_wr_arr_i)='0' ELSE '1';
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out_new <= out_new_i AND toggle;
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reg_wr_arr <= reg_wr_arr_i;
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gen_access_evt : FOR I IN 0 TO g_reg.nof_dat-1 GENERATE
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u_reg_wr_arr : ENTITY common_components_lib.common_spulse
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PORT MAP (
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in_rst => mm_rst,
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in_clk => mm_clk,
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in_pulse => vector_wr_arr(I),
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in_busy => OPEN,
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out_rst => st_rst,
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out_clk => st_clk,
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out_pulse => reg_wr_arr_i(I)
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);
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u_reg_rd_arr : ENTITY common_components_lib.common_spulse
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PORT MAP (
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in_rst => mm_rst,
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in_clk => mm_clk,
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in_pulse => vector_rd_arr(I),
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in_busy => OPEN,
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out_rst => st_rst,
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out_clk => st_clk,
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out_pulse => reg_rd_arr(I)
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);
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END GENERATE;
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END GENERATE; -- gen_cross
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END str;
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