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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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danv |
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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-- Purpose:
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-- . Define fields in an SLV that can be read/written via an MM interface.
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-- Description:
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-- . This is basically a wrapper around common_reg_r_w_dc, but with the
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-- addition of a generic field description array and package functions
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-- to ease the definition and assignment of individual fields within
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-- the i/o SLVs.
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-- . Each field defined in g_field_arr will get its own 32-bit MM register(s)
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-- based on its defined length:
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-- . <32 bits = one dedicated 32-bit register for that field
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-- . >32 bits = multiple dedicated 32-bit registers for that field
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-- . The register mode can be "RO" for input from slv_in (e.g. status) or "RW"
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-- for output via slv_out (e.g. control). Other modes are not supported.
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-- Hence the length of the reg_slv_* signals is equal to slv_in'LENGTH +
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-- slv_out'LENGTH.
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-- . The figure below shows how the following example field array would be mapped.
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--
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-- c_my_field_arr:= (( "my_field_2", "RW", 2 ),
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-- ( "my_field_1", "RO", 2 ),
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-- ( "my_field_0", "RO", 1 ));
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--
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-- ----------------------------------------------------------------------------------------------------------------
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-- | slv_in reg_slv_in_arr reg_slv_in common_reg_r_w reg_slv_out slv_out|
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-- | |
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-- | __ __ ______________ __ |
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-- | w0|f0| w0|f0| |0 | w0| | |
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-- | | | =====> | | =====> | RO | =====> | | =====> |
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-- | | | | | | | | | |
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-- | __ |--| |--| |--------------| |--| |
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-- | |f0| w1|f1| w1|f1| |1 | w1| | __ |
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-- | |f1| ==field_map_in==> |f1| =====> |f1| =====> | RO | =====> | | =====> field_map_out==> |f2| |
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-- | |f1| | | | | | | | | |f2| |
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-- | |--| |--| |--------------| |--| |
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-- | w2| | w2|f2| |2 | w2|f2| |
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-- | | | /===> |f2| =====> | RW | =====> |f2| ==+==> |
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-- | |__| | |__| |______________| |__| | |
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-- | | | |
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-- | \================================================/ |
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-- | |
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-- ----------------------------------------------------------------------------------------------------------------
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-- . slv_in = 3 bits wide
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-- . slv_out = 2 bits wide (= my_field_2 which is looped back to reg_slv_in because it is defined "RW")
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-- . reg_reg_slv_in_arr, reg_slv_in, reg_slv_out = 3*c_word_w bits wide
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-- Remarks:
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LIBRARY IEEE, common_pkg_lib, common_ram_lib;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE work.common_field_pkg.ALL;
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ENTITY mm_fields IS
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GENERIC (
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g_cross_clock_domain : BOOLEAN := TRUE;
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g_use_slv_in_val : BOOLEAN := TRUE; -- use TRUE when slv_in_val is used, use FALSE to save logic when always slv_in_val='1'
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g_field_arr : t_common_field_arr
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);
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PORT (
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mm_rst : IN STD_LOGIC;
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mm_clk : IN STD_LOGIC;
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mm_mosi : IN t_mem_mosi;
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mm_miso : OUT t_mem_miso;
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slv_rst : IN STD_LOGIC;
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slv_clk : IN STD_LOGIC;
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--fields in these SLVs are defined by g_field_arr
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slv_in : IN STD_LOGIC_VECTOR(field_slv_in_len( g_field_arr)-1 DOWNTO 0) := (OTHERS=>'0'); -- slv of all "RO" fields in g_field_arr
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slv_in_val : IN STD_LOGIC := '0'; -- strobe to signal that slv_in is valid and needs to be captured
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slv_out : OUT STD_LOGIC_VECTOR(field_slv_out_len(g_field_arr)-1 DOWNTO 0) -- slv of all "RW" fields in g_field_arr
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);
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END mm_fields;
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ARCHITECTURE str OF mm_fields IS
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CONSTANT c_reg_nof_words : NATURAL := field_nof_words(g_field_arr, c_word_w);
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CONSTANT c_reg : t_c_mem := (latency => 1,
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adr_w => ceil_log2(c_reg_nof_words),
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dat_w => c_word_w,
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nof_dat => c_reg_nof_words,
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init_sl => '0');
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CONSTANT c_slv_out_defaults : STD_LOGIC_VECTOR(field_slv_out_len(g_field_arr)-1 DOWNTO 0) := field_map_defaults(g_field_arr);
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-- Map the default values onto c_init_reg
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CONSTANT c_init_reg : STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := RESIZE_UVEC(field_map_in(g_field_arr, c_slv_out_defaults, c_reg.dat_w, "RW"), c_mem_reg_init_w);
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SIGNAL slv_in_arr : STD_LOGIC_VECTOR(c_reg.dat_w*c_reg.nof_dat-1 DOWNTO 0);
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SIGNAL reg_slv_in_arr : STD_LOGIC_VECTOR(c_reg.dat_w*c_reg.nof_dat-1 DOWNTO 0);
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SIGNAL nxt_reg_slv_in_arr : STD_LOGIC_VECTOR(c_reg.dat_w*c_reg.nof_dat-1 DOWNTO 0);
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SIGNAL reg_slv_in : STD_LOGIC_VECTOR(c_reg.dat_w*c_reg.nof_dat-1 DOWNTO 0);
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SIGNAL reg_slv_out : STD_LOGIC_VECTOR(c_reg.dat_w*c_reg.nof_dat-1 DOWNTO 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- reg_slv_out is persistent (always valid) while slv_in is not. Register
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-- slv_in_arr so reg_slv_in is persistent also.
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-----------------------------------------------------------------------------
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gen_capture_input : IF g_use_slv_in_val=TRUE GENERATE
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p_clk : PROCESS(slv_clk, slv_rst)
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BEGIN
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IF slv_rst='1' THEN
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reg_slv_in_arr <= (OTHERS=>'0');
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ELSIF rising_edge(slv_clk) THEN
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reg_slv_in_arr <= nxt_reg_slv_in_arr;
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END IF;
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END PROCESS;
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nxt_reg_slv_in_arr <= slv_in_arr WHEN slv_in_val = '1' ELSE reg_slv_in_arr;
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END GENERATE;
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gen_wire_input : IF g_use_slv_in_val=FALSE GENERATE
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reg_slv_in_arr <= slv_in_arr;
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END GENERATE;
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-----------------------------------------------------------------------------
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-- Field mapping
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-----------------------------------------------------------------------------
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-- Extract the all input fields ("RO") from slv_in and assign them to slv_in_arr
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slv_in_arr <= field_map_in(g_field_arr, slv_in, c_reg.dat_w, "RO");
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-- Map reg_slv_out onto slv_out for the write fields
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slv_out <= field_map_out(g_field_arr, reg_slv_out, c_reg.dat_w);
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-- Create the correct reg_slv_in using fields from both reg_slv_in_arr ("RO") reg_slv_out ("RW")
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reg_slv_in <= field_map(g_field_arr, reg_slv_in_arr, reg_slv_out, c_reg.dat_w);
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-----------------------------------------------------------------------------
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-- Actual MM <-> SLV R/W functionality is provided by common_reg_r_w_dc
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-----------------------------------------------------------------------------
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u_common_reg_r_w_dc : ENTITY work.common_reg_r_w_dc
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GENERIC MAP (
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g_cross_clock_domain => g_cross_clock_domain,
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g_readback => FALSE,
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g_reg => c_reg,
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g_init_reg => c_init_reg
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)
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PORT MAP (
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mm_rst => mm_rst,
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mm_clk => mm_clk,
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st_rst => slv_rst,
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st_clk => slv_clk,
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sla_in => mm_mosi,
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sla_out => mm_miso,
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in_reg => reg_slv_in,
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out_reg => reg_slv_out
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);
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END str;
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