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[/] [astron_mm/] [trunk/] [tb_mm_file.vhd] - Blame information for rev 3

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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--
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-- Author:
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--   D. van der Schuur  May 2012  Original with manual file IO using an editor.
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--   E. Kooistra        Feb 2017  Added purpose and description
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--                                Added external control by p_mm_stimuli and
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--                                p_sim_stimuli
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-- Purpose: Testbench for MM and simulation control via file io
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-- Description:
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--   This testbench verifies mm_file and mm_file_pkg.
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--   1) p_mm_stimuli
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--     The p_mm_stimuli uses mmf_mm_bus_wr() and mmf_mm_bus_rd() to access a MM
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--     slave register instance of common_reg_r_w_dc via mm_file using a MM slave
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--     .ctrl and .stat file. The p_mm_stimuli verifies the W/R accesses.
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--   2) p_sim_stimuli
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--     The p_sim_stimuli waits for get_now and then it uses mmf_sim_get_now() to
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--     read the simulator status via mmf_poll_sim_ctrl_file() using a sim.ctrl
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--     and sim.stat file. The p_sim_stimuli does not verify read rd_now value,
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--     but it does print it.
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-- Usage:
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--   > as 5
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--   > run -all
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--   The tb is self stopping and self checking. 
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--   For example observe mm_mosi, mm_miso, rd_now and out_reg_arr in wave window.
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LIBRARY IEEE, common_pkg_lib, common_ram_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE common_pkg_lib.common_str_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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USE work.mm_file_pkg.ALL;
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ENTITY tb_mm_file IS
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  GENERIC (
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    g_tb_index           : NATURAL := 0;
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    g_mm_nof_accesses    : NATURAL := 100;
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    g_mm_timeout         : TIME := 0 ns;--100 ns;   -- default 0 ns for full speed MM, use > 0 to define number of mm_clk without MM access after which the MM file IO is paused
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    g_mm_pause           : TIME := 1000 ns;  -- defines the time for which MM file IO is paused to reduce the file IO rate when the MM slave is idle
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    g_timeout_gap        : INTEGER := -1;--4;    -- no gap when < 0, else force MM access gap after g_timeout_gap wr or rd strobes
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    g_cross_clock_domain : BOOLEAN := FALSE --TRUE
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  );
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END tb_mm_file;
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ARCHITECTURE tb OF tb_mm_file IS
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  CONSTANT c_mm_clk_period            : TIME := c_mmf_mm_clk_period;  -- = 100 ps;
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  CONSTANT c_mm_nof_dat               : NATURAL := smallest(c_mem_reg_init_w/c_32, g_mm_nof_accesses);
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  CONSTANT c_mm_rd_latency            : NATURAL := 2;
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70
  CONSTANT c_cross_nof_mm_clk         : NATURAL := sel_a_b(g_cross_clock_domain, 100, 0);  -- > 2*24 see common_reg_cross_domain, factor 2 for W/R
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72
  -- Determine node mm_file prefix based on --unb --gn (similar as done in mmf_unb_file_prefix())
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  CONSTANT c_unb_nr                   : NATURAL := 3;  --unb
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  CONSTANT c_pn_nr                    : NATURAL := 1;  --gn = 0:7
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  CONSTANT c_node_type                : STRING(1 TO 2):= sel_a_b(c_pn_nr<4, "FN", "BN");
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  CONSTANT c_node_nr                  : NATURAL := sel_a_b(c_node_type="BN", c_pn_nr-4, c_pn_nr);
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78
  -- Use local mmfiles/ subdirectory in mm project build directory
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  CONSTANT c_sim_file_pathname        : STRING := mmf_slave_prefix("TB", g_tb_index) & "sim";
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  CONSTANT c_reg_r_w_dc_file_pathname : STRING := mmf_slave_prefix("TB", g_tb_index, "UNB", c_unb_nr, c_node_type, c_node_nr) & "REG_R_W_DC";
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82
  --TYPE t_c_mem IS RECORD
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  --  latency   : NATURAL;    -- read latency
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  --  adr_w     : NATURAL;
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  --  dat_w     : NATURAL;
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  --  nof_dat   : NATURAL;    -- optional, nof dat words <= 2**adr_w
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  --  init_sl   : STD_LOGIC;  -- optional, init all dat words to std_logic '0', '1' or 'X'
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  --  --init_file : STRING;     -- "UNUSED", unconstrained length can not be in record
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  --END RECORD;
90
  CONSTANT c_mem_reg            : t_c_mem := (c_mm_rd_latency, ceil_log2(c_mm_nof_dat), c_32, c_mm_nof_dat, '0');
91
 
92
  SIGNAL tb_state           : STRING(1 TO 5) := "Init ";
93
  SIGNAL tb_end             : STD_LOGIC := '0';
94
  SIGNAL mm_clk             : STD_LOGIC := '0';
95
  SIGNAL mm_rst             : STD_LOGIC;
96
 
97
  SIGNAL get_now            : STD_LOGIC := '0';
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  SIGNAL rd_now             : STRING(1 TO 16);  -- sufficient to fit TIME NOW in ns as a string
99
 
100
  SIGNAL mm_mosi            : t_mem_mosi;
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  SIGNAL mm_miso            : t_mem_miso;
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  SIGNAL file_wr_data       : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
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  SIGNAL file_rd_data       : STD_LOGIC_VECTOR(c_32-1 DOWNTO 0);
104
 
105
  SIGNAL reg_wr_arr         : STD_LOGIC_VECTOR(     c_mem_reg.nof_dat-1 DOWNTO 0);
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  SIGNAL reg_rd_arr         : STD_LOGIC_VECTOR(     c_mem_reg.nof_dat-1 DOWNTO 0);
107
  SIGNAL in_new             : STD_LOGIC := '1';
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  SIGNAL in_reg             : STD_LOGIC_VECTOR(c_32*c_mem_reg.nof_dat-1 DOWNTO 0);
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  SIGNAL out_reg            : STD_LOGIC_VECTOR(c_32*c_mem_reg.nof_dat-1 DOWNTO 0);
110
  SIGNAL out_new            : STD_LOGIC;    -- Pulses '1' when new data has been written.
111
 
112
  SIGNAL out_reg_arr        : t_slv_32_arr(c_mem_reg.nof_dat-1 DOWNTO 0);
113
 
114
BEGIN
115
 
116
  mm_clk <= NOT mm_clk OR tb_end AFTER c_mm_clk_period/2;
117
  mm_rst <= '1', '0' AFTER c_mm_clk_period*10;
118
 
119
  -- DUT mm access files 'c_reg_r_w_dc_file_pathname'.ctrl and 'c_reg_r_w_dc_file_pathname'.stat
120
  p_mm_stimuli : PROCESS
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    VARIABLE v_addr : NATURAL;
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  BEGIN
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    proc_common_wait_until_low(mm_clk, mm_rst);
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    proc_common_wait_some_cycles(mm_clk, 3);
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    -- Write all nof_dat once
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    tb_state <= "Write";
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    FOR I IN 0 TO c_mm_nof_dat-1 LOOP
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      IF I=g_timeout_gap THEN
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        WAIT FOR 2*c_mmf_mm_timeout;
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      END IF;
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      file_wr_data <= TO_UVEC(I, c_32);
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      mmf_mm_bus_wr(c_reg_r_w_dc_file_pathname, I, I, mm_clk);
134
    END LOOP;
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    proc_common_wait_some_cycles(mm_clk, c_cross_nof_mm_clk);
137
 
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    -- Read all nof_dat once
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    tb_state <= "Read ";
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    FOR I IN 0 TO c_mm_nof_dat-1 LOOP
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      IF I=g_timeout_gap THEN
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        WAIT FOR 2*c_mmf_mm_timeout;
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      END IF;
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      mmf_mm_bus_rd(c_reg_r_w_dc_file_pathname, c_mem_reg.latency, I, file_rd_data, mm_clk);
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      ASSERT I=TO_UINT(file_rd_data) REPORT "Read data is wrong." SEVERITY ERROR;
146
    END LOOP;
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148
    -- Write/Read
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    tb_state <= "Both ";
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    FOR I IN 0 TO g_mm_nof_accesses-1 LOOP
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      IF I=g_timeout_gap THEN
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        WAIT FOR 2*c_mmf_mm_timeout;
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      END IF;
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      file_wr_data <= TO_UVEC(I, c_32);
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      v_addr := I MOD c_mm_nof_dat;
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      mmf_mm_bus_wr(c_reg_r_w_dc_file_pathname, v_addr, I, mm_clk);
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      proc_common_wait_some_cycles(mm_clk, c_cross_nof_mm_clk);
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      mmf_mm_bus_rd(c_reg_r_w_dc_file_pathname, c_mem_reg.latency, v_addr, file_rd_data, mm_clk);
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      ASSERT TO_UINT(file_wr_data)=TO_UINT(file_rd_data) REPORT "Write/read data is wrong." SEVERITY ERROR;
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    END LOOP;
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    proc_common_gen_pulse(mm_clk, get_now);
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    tb_state <= "End  ";
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    proc_common_wait_some_cycles(mm_clk, g_mm_nof_accesses);
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    tb_end <= '1';
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    WAIT;
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  END PROCESS;
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  u_mm_file : ENTITY work.mm_file
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  GENERIC MAP(
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    g_file_prefix   => c_reg_r_w_dc_file_pathname,
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    g_mm_rd_latency => c_mem_reg.latency,  -- the mm_file g_mm_rd_latency must be >= the MM slave read latency
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    g_mm_timeout    => g_mm_timeout,
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    g_mm_pause      => g_mm_pause
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  )
177
  PORT MAP (
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    mm_rst        => mm_rst,
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    mm_clk        => mm_clk,
180
 
181
    mm_master_out => mm_mosi,
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    mm_master_in  => mm_miso
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  );
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  -- Target MM reg
186
  u_reg_r_w_dc : ENTITY work.common_reg_r_w_dc
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  GENERIC MAP (
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    g_cross_clock_domain => g_cross_clock_domain,
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    g_in_new_latency     => 0,
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    g_readback           => FALSE,
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    g_reg                => c_mem_reg
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    --g_init_reg           => STD_LOGIC_VECTOR(c_mem_reg_init_w-1 DOWNTO 0) := (OTHERS => '0')
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  )
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  PORT MAP (
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    -- Clocks and reset
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    mm_rst      => mm_rst,
197
    mm_clk      => mm_clk,
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    st_rst      => mm_rst,
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    st_clk      => mm_clk,
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    -- Memory Mapped Slave in mm_clk domain
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    sla_in      => mm_mosi,
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    sla_out     => mm_miso,
204
 
205
    -- MM registers in st_clk domain
206
    reg_wr_arr  => reg_wr_arr,
207
    reg_rd_arr  => reg_rd_arr,
208
    in_new      => in_new,
209
    in_reg      => in_reg,
210
    out_reg     => out_reg,
211
    out_new     => out_new
212
  );
213
 
214
  in_reg <= out_reg;
215
 
216
  p_wire : PROCESS(out_reg)
217
  BEGIN
218
    FOR I IN c_mem_reg.nof_dat-1 DOWNTO 0 LOOP
219
      out_reg_arr(I) <= out_reg((I+1)*c_32-1 DOWNTO I*c_32);
220
    END LOOP;
221
  END PROCESS;
222
 
223
  -- Also verify simulation status access
224
  mmf_poll_sim_ctrl_file(mm_clk, c_sim_file_pathname & ".ctrl", c_sim_file_pathname & ".stat");
225
 
226
  p_sim_stimuli : PROCESS
227
  BEGIN
228
    proc_common_wait_until_low(mm_clk, mm_rst);
229
    proc_common_wait_some_cycles(mm_clk, 10);
230
 
231
    proc_common_wait_until_hi_lo(mm_clk, get_now);
232
    mmf_sim_get_now(c_sim_file_pathname, rd_now, mm_clk);
233
    WAIT;
234
  END PROCESS;
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END tb;

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