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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2015
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Output frame busy control signal that is active from sop to eop
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-- Description:
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-- The busy is active during the entire frame from sop to eop, so busy
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-- remains active in case valid goes low during a frame.
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-- Default use g_pipeline=0 to have snk_in_busy in phase with sop and eop.
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-- Use g_pipeline > 0 to register snk_in_busy to ease timing closure.
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LIBRARY IEEE, common_pkg_lib, common_components_lib, dp_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE dp_pkg_lib.dp_stream_pkg.ALL;
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ENTITY dp_frame_busy IS
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GENERIC (
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g_pipeline : NATURAL := 0
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);
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PORT (
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rst : IN STD_LOGIC;
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clk : IN STD_LOGIC;
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snk_in : IN t_dp_sosi;
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snk_in_busy : OUT STD_LOGIC
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);
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END dp_frame_busy;
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ARCHITECTURE str OF dp_frame_busy IS
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SIGNAL busy : STD_LOGIC;
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BEGIN
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u_common_switch : ENTITY common_components_lib.common_switch
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GENERIC MAP (
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g_rst_level => '0', -- Defines the output level at reset.
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g_priority_lo => TRUE, -- When TRUE then input switch_low has priority, else switch_high. Don't care when switch_high and switch_low are pulses that do not occur simultaneously.
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g_or_high => TRUE, -- When TRUE and priority hi then the registered switch_level is OR-ed with the input switch_high to get out_level, else out_level is the registered switch_level
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g_and_low => FALSE -- When TRUE and priority lo then the registered switch_level is AND-ed with the input switch_low to get out_level, else out_level is the registered switch_level
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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switch_high => snk_in.sop, -- A pulse on switch_high makes the out_level go high
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switch_low => snk_in.eop, -- A pulse on switch_low makes the out_level go low
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out_level => busy
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);
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u_common_pipeline_sl : ENTITY common_components_lib.common_pipeline_sl
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GENERIC MAP (
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g_pipeline => g_pipeline, -- 0 for wires, > 0 for registers,
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g_reset_value => 0, -- 0 or 1, bit reset value,
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g_out_invert => FALSE
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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in_dat => busy,
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out_dat => snk_in_busy
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);
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END str;
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