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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_mult_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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--
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-- Function: Signed complex multiply
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-- p = a * b when g_conjugate_b = FALSE
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-- = (ar + j ai) * (br + j bi)
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-- = ar*br - ai*bi + j ( ar*bi + ai*br)
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--
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-- p = a * conj(b) when g_conjugate_b = TRUE
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-- = (ar + j ai) * (br - j bi)
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-- = ar*br + ai*bi + j (-ar*bi + ai*br)
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--
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-- Architectures:
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-- . rtl : uses RTL to have all registers in one clocked process
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-- . str : uses two RTL instances of common_mult_add2 for out_pr and out_pi
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-- . str_stratix4 : uses two Stratix4 instances of common_mult_add2 for out_pr and out_pi
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-- . stratix4 : uses MegaWizard component from common_complex_mult(stratix4).vhd
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-- . rtl_dsp : uses RTL with one process (as in Altera example)
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-- . altera_rtl : uses RTL with one process (as in Altera example, by Raj R. Thilak)
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--
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-- Preferred architecture: 'str', see synth\quartus\common_top.vhd
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ENTITY common_complex_mult IS
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GENERIC (
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g_sim : BOOLEAN := FALSE;
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g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
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g_technology : NATURAL := c_tech_select_default;
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g_variant : STRING := "RTL";
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g_in_a_w : POSITIVE;
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g_in_b_w : POSITIVE;
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g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
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g_conjugate_b : BOOLEAN := FALSE;
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g_pipeline_input : NATURAL := 1; -- 0 or 1
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g_pipeline_product : NATURAL := 0; -- 0 or 1
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g_pipeline_adder : NATURAL := 1; -- 0 or 1
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g_pipeline_output : NATURAL := 1 -- >= 0
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);
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PORT (
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rst : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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in_ar : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
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in_ai : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
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in_br : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
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in_bi : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
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in_val : IN STD_LOGIC := '1';
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out_pr : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
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out_pi : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
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out_val : OUT STD_LOGIC
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);
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END common_complex_mult;
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ARCHITECTURE str OF common_complex_mult IS
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CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
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-- MegaWizard IP ip_stratixiv_complex_mult was generated with latency c_dsp_latency = 3
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CONSTANT c_dsp_latency : NATURAL := 3;
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-- Extra output pipelining is only needed when c_pipeline > c_dsp_latency
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CONSTANT c_pipeline_output : NATURAL := sel_a_b(c_pipeline>c_dsp_latency, c_pipeline-c_dsp_latency, 0);
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SIGNAL result_re : STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
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SIGNAL result_im : STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
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BEGIN
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-- User specificied latency must be >= MegaWizard IP dsp_mult_add2 latency
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ASSERT c_pipeline >= c_dsp_latency
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REPORT "tech_complex_mult: pipeline value not supported"
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SEVERITY FAILURE;
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-- Propagate in_val with c_pipeline latency
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u_out_val : ENTITY common_components_lib.common_pipeline_sl
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GENERIC MAP (
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g_pipeline => c_pipeline
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => clken,
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in_dat => in_val,
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out_dat => out_val
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);
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u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
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GENERIC MAP(
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g_sim => g_sim,
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g_sim_level => g_sim_level,
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g_technology => g_technology,
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g_variant => g_variant,
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g_in_a_w => g_in_a_w,
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g_in_b_w => g_in_b_w,
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g_out_p_w => g_out_p_w,
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g_conjugate_b => g_conjugate_b,
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g_pipeline_input => g_pipeline_input,
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g_pipeline_product => g_pipeline_product,
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g_pipeline_adder => g_pipeline_adder,
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g_pipeline_output => g_pipeline_output
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)
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PORT MAP(
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rst => rst,
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clk => clk,
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clken => clken,
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in_ar => in_ar,
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in_ai => in_ai,
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in_br => in_br,
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in_bi => in_bi,
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result_re => result_re,
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result_im => result_im
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);
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------------------------------------------------------------------------------
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-- Extra output pipelining
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------------------------------------------------------------------------------
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u_output_re_pipe : ENTITY common_components_lib.common_pipeline -- pipeline output
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GENERIC MAP (
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g_representation => "SIGNED",
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g_pipeline => c_pipeline_output,
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g_in_dat_w => g_out_p_w,
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g_out_dat_w => g_out_p_w
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)
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PORT MAP (
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clk => clk,
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clken => clken,
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in_dat => STD_LOGIC_VECTOR(result_re),
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out_dat => out_pr
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);
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u_output_im_pipe : ENTITY common_components_lib.common_pipeline -- pipeline output
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GENERIC MAP (
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g_representation => "SIGNED",
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g_pipeline => c_pipeline_output,
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g_in_dat_w => g_out_p_w,
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g_out_dat_w => g_out_p_w
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)
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PORT MAP (
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clk => clk,
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clken => clken,
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in_dat => STD_LOGIC_VECTOR(result_im),
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out_dat => out_pi
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);
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END str;
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