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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2011
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee, common_pkg_lib, common_components_lib;
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USE ieee.std_logic_1164.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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-- Function: Default one or more independent products dependent on g_nof_mult
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--
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-- If g_nof_mult = 2 then the input vectors are
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-- a = a(1) & a(0) and b = b(1) & b(0)
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-- and the independent products in the product vector will be:
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-- p = a(1)*b(1) & a(0)*b(0)
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--
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-- Remarks:
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-- . When g_out_p_w < g_in_a_w+g_in_b_w then the common_mult truncates the
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-- MSbit of the product.
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-- . For c_prod_w = g_in_a_w+g_in_b_w the full product range is preserved. Use
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-- g_out_p_w = c_prod_w-1 to skip the double sign bit that is only needed
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-- when the maximum positive product -2**(g_in_a_w-1) * -2**(g_in_b_w-1) has
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-- to be represented, which is typically not needed in DSP.
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ENTITY common_mult IS
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GENERIC (
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g_technology : NATURAL := 0;
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g_variant : STRING := "IP";
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g_in_a_w : POSITIVE := 18;
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g_in_b_w : POSITIVE := 18;
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g_out_p_w : POSITIVE := 36; -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
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g_nof_mult : POSITIVE := 1; -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
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g_pipeline_input : NATURAL := 1; -- 0 or 1
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g_pipeline_product : NATURAL := 1; -- 0 or 1
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g_pipeline_output : NATURAL := 1; -- >= 0
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g_representation : STRING := "SIGNED" -- or "UNSIGNED"
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);
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PORT (
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rst : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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in_a : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
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in_b : IN STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
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in_val : IN STD_LOGIC := '1'; -- only propagate valid, not used internally
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out_p : OUT STD_LOGIC_VECTOR(g_nof_mult*g_out_p_w-1 DOWNTO 0);
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out_val : OUT STD_LOGIC
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);
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END common_mult;
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ARCHITECTURE str OF common_mult IS
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CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_output;
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-- Extra output pipelining using common_pipeline is only needed when g_pipeline_output > 1
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CONSTANT c_pipeline_output : NATURAL := sel_a_b(g_pipeline_output>0, g_pipeline_output-1, 0);
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SIGNAL result : STD_LOGIC_VECTOR(out_p'RANGE); -- stage dependent on g_pipeline_output being 0 or 1
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BEGIN
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u_mult : ENTITY work.tech_mult
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GENERIC MAP(
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g_technology => g_technology,
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g_variant => g_variant,
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g_in_a_w => g_in_a_w,
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g_in_b_w => g_in_b_w,
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g_out_p_w => g_out_p_w,
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g_nof_mult => g_nof_mult,
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g_pipeline_input => g_pipeline_input,
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g_pipeline_product => g_pipeline_product,
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g_pipeline_output => g_pipeline_output,
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g_representation => g_representation
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)
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PORT MAP(
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rst => rst,
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clk => clk,
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clken => clken,
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in_a => in_a,
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in_b => in_b,
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out_p => result
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);
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-- Propagate in_val with c_pipeline latency
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u_out_val : ENTITY common_components_lib.common_pipeline_sl
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GENERIC MAP (
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g_pipeline => c_pipeline
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => clken,
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in_dat => in_val,
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out_dat => out_val
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);
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------------------------------------------------------------------------------
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-- Extra output pipelining
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------------------------------------------------------------------------------
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u_output_pipe : ENTITY common_components_lib.common_pipeline -- pipeline output
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GENERIC MAP (
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g_representation => g_representation,
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g_pipeline => c_pipeline_output,
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g_in_dat_w => result'LENGTH,
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g_out_dat_w => result'LENGTH
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => clken,
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in_dat => STD_LOGIC_VECTOR(result),
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out_dat => out_p
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);
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END str;
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