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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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danv |
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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danv |
--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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--
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-- Function: Signed complex multiply
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-- p = a * b when g_conjugate_b = FALSE
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-- = (ar + j ai) * (br + j bi)
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-- = ar*br - ai*bi + j ( ar*bi + ai*br)
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--
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-- p = a * conj(b) when g_conjugate_b = TRUE
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-- = (ar + j ai) * (br - j bi)
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-- = ar*br + ai*bi + j (-ar*bi + ai*br)
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--
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-- Architectures:
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-- . rtl : uses RTL to have all registers in one clocked process
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-- . str : uses two RTL instances of common_mult_add2 for out_pr and out_pi
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-- . str_stratix4 : uses two Stratix4 instances of common_mult_add2 for out_pr and out_pi
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-- . stratix4 : uses MegaWizard component from common_complex_mult(stratix4).vhd
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-- . rtl_dsp : uses RTL with one process (as in Altera example)
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-- . altera_rtl : uses RTL with one process (as in Altera example, by Raj R. Thilak)
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--
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-- Preferred architecture: 'str', see synth\quartus\common_top.vhd
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ENTITY ip_stratixiv_complex_mult_rtl IS
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GENERIC (
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g_in_a_w : POSITIVE;
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g_in_b_w : POSITIVE;
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g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
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g_conjugate_b : BOOLEAN := FALSE;
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g_pipeline_input : NATURAL := 1; -- 0 or 1
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g_pipeline_product : NATURAL := 0; -- 0 or 1
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g_pipeline_adder : NATURAL := 1; -- 0 or 1
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g_pipeline_output : NATURAL := 1 -- >= 0
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);
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PORT (
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rst : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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in_ar : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
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in_ai : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
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in_br : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
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in_bi : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
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result_re : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
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result_im : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
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);
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END ip_stratixiv_complex_mult_rtl;
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ARCHITECTURE str OF ip_stratixiv_complex_mult_rtl IS
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FUNCTION RESIZE_NUM(s : SIGNED; w : NATURAL) RETURN SIGNED IS
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BEGIN
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-- extend sign bit or keep LS part
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IF w>s'LENGTH THEN
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RETURN RESIZE(s, w); -- extend sign bit
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ELSE
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RETURN SIGNED(RESIZE(UNSIGNED(s), w)); -- keep LSbits (= vec[w-1:0])
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END IF;
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END;
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CONSTANT c_prod_w : NATURAL := g_in_a_w+g_in_b_w;
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CONSTANT c_sum_w : NATURAL := c_prod_w+1;
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-- CONSTANT c_re_add_sub : STRING := sel_a_b(g_conjugate_b, "ADD", "SUB");
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-- CONSTANT c_im_add_sub : STRING := sel_a_b(g_conjugate_b, "SUB", "ADD");
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-- registers
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SIGNAL reg_ar : SIGNED(g_in_a_w-1 DOWNTO 0);
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SIGNAL reg_ai : SIGNED(g_in_a_w-1 DOWNTO 0);
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SIGNAL reg_br : SIGNED(g_in_b_w-1 DOWNTO 0);
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SIGNAL reg_bi : SIGNED(g_in_b_w-1 DOWNTO 0);
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SIGNAL reg_prod_ar_br : SIGNED(c_prod_w-1 DOWNTO 0); -- re
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SIGNAL reg_prod_ai_bi : SIGNED(c_prod_w-1 DOWNTO 0);
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SIGNAL reg_prod_ai_br : SIGNED(c_prod_w-1 DOWNTO 0); -- im
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SIGNAL reg_prod_ar_bi : SIGNED(c_prod_w-1 DOWNTO 0);
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SIGNAL reg_sum_re : SIGNED(c_sum_w-1 DOWNTO 0);
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SIGNAL reg_sum_im : SIGNED(c_sum_w-1 DOWNTO 0);
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SIGNAL reg_result_re : SIGNED(g_out_p_w-1 DOWNTO 0);
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SIGNAL reg_result_im : SIGNED(g_out_p_w-1 DOWNTO 0);
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-- combinatorial
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SIGNAL nxt_ar : SIGNED(g_in_a_w-1 DOWNTO 0);
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SIGNAL nxt_ai : SIGNED(g_in_a_w-1 DOWNTO 0);
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SIGNAL nxt_br : SIGNED(g_in_b_w-1 DOWNTO 0);
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SIGNAL nxt_bi : SIGNED(g_in_b_w-1 DOWNTO 0);
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SIGNAL nxt_prod_ar_br : SIGNED(c_prod_w-1 DOWNTO 0); -- re
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SIGNAL nxt_prod_ai_bi : SIGNED(c_prod_w-1 DOWNTO 0);
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SIGNAL nxt_prod_ai_br : SIGNED(c_prod_w-1 DOWNTO 0); -- im
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SIGNAL nxt_prod_ar_bi : SIGNED(c_prod_w-1 DOWNTO 0);
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SIGNAL nxt_sum_re : SIGNED(c_sum_w-1 DOWNTO 0);
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SIGNAL nxt_sum_im : SIGNED(c_sum_w-1 DOWNTO 0);
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SIGNAL nxt_result_re : SIGNED(g_out_p_w-1 DOWNTO 0);
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SIGNAL nxt_result_im : SIGNED(g_out_p_w-1 DOWNTO 0);
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-- the active signals
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SIGNAL ar : SIGNED(g_in_a_w-1 DOWNTO 0);
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SIGNAL ai : SIGNED(g_in_a_w-1 DOWNTO 0);
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SIGNAL br : SIGNED(g_in_b_w-1 DOWNTO 0);
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SIGNAL bi : SIGNED(g_in_b_w-1 DOWNTO 0);
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SIGNAL prod_ar_br : SIGNED(c_prod_w-1 DOWNTO 0); -- re
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SIGNAL prod_ai_bi : SIGNED(c_prod_w-1 DOWNTO 0);
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SIGNAL prod_ai_br : SIGNED(c_prod_w-1 DOWNTO 0); -- im
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SIGNAL prod_ar_bi : SIGNED(c_prod_w-1 DOWNTO 0);
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SIGNAL sum_re : SIGNED(c_sum_w-1 DOWNTO 0);
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SIGNAL sum_im : SIGNED(c_sum_w-1 DOWNTO 0);
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BEGIN
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------------------------------------------------------------------------------
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-- Registers
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------------------------------------------------------------------------------
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-- Put all potential registers in a single process for optimal DSP inferrence
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-- Use rst only if it is supported by the DSP primitive, else leave it at '0'
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p_reg : PROCESS (rst, clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF rst='1' THEN
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reg_ar <= (OTHERS=>'0');
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reg_ai <= (OTHERS=>'0');
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reg_br <= (OTHERS=>'0');
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reg_bi <= (OTHERS=>'0');
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reg_prod_ar_br <= (OTHERS=>'0');
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reg_prod_ai_bi <= (OTHERS=>'0');
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reg_prod_ai_br <= (OTHERS=>'0');
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reg_prod_ar_bi <= (OTHERS=>'0');
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reg_sum_re <= (OTHERS=>'0');
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reg_sum_im <= (OTHERS=>'0');
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reg_result_re <= (OTHERS=>'0');
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reg_result_im <= (OTHERS=>'0');
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ELSIF clken='1' THEN
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reg_ar <= nxt_ar; -- inputs
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reg_ai <= nxt_ai;
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reg_br <= nxt_br;
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reg_bi <= nxt_bi;
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reg_prod_ar_br <= nxt_prod_ar_br; -- products for re
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reg_prod_ai_bi <= nxt_prod_ai_bi;
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reg_prod_ai_br <= nxt_prod_ai_br; -- products for im
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reg_prod_ar_bi <= nxt_prod_ar_bi;
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reg_sum_re <= nxt_sum_re; -- sum
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reg_sum_im <= nxt_sum_im;
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reg_result_re <= nxt_result_re; -- result sum after optional register stage
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reg_result_im <= nxt_result_im;
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END IF;
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END IF;
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END PROCESS;
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------------------------------------------------------------------------------
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-- Inputs
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------------------------------------------------------------------------------
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nxt_ar <= SIGNED(in_ar);
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nxt_ai <= SIGNED(in_ai);
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nxt_br <= SIGNED(in_br);
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nxt_bi <= SIGNED(in_bi);
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no_input_reg : IF g_pipeline_input=0 GENERATE -- wired
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ar <= nxt_ar;
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ai <= nxt_ai;
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br <= nxt_br;
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bi <= nxt_bi;
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END GENERATE;
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gen_input_reg : IF g_pipeline_input>0 GENERATE -- register input
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ar <= reg_ar;
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ai <= reg_ai;
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br <= reg_br;
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bi <= reg_bi;
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END GENERATE;
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------------------------------------------------------------------------------
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-- Products
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------------------------------------------------------------------------------
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nxt_prod_ar_br <= ar * br; -- products for re
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nxt_prod_ai_bi <= ai * bi;
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nxt_prod_ai_br <= ai * br; -- products for im
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nxt_prod_ar_bi <= ar * bi;
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no_product_reg : IF g_pipeline_product=0 GENERATE -- wired
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prod_ar_br <= nxt_prod_ar_br;
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prod_ai_bi <= nxt_prod_ai_bi;
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prod_ai_br <= nxt_prod_ai_br;
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prod_ar_bi <= nxt_prod_ar_bi;
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END GENERATE;
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gen_product_reg : IF g_pipeline_product>0 GENERATE -- register
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prod_ar_br <= reg_prod_ar_br;
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prod_ai_bi <= reg_prod_ai_bi;
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prod_ai_br <= reg_prod_ai_br;
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prod_ar_bi <= reg_prod_ar_bi;
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END GENERATE;
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------------------------------------------------------------------------------
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-- Sum
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------------------------------------------------------------------------------
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-- Re
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-- . "ADD" for a*conj(b) : ar*br + ai*bi
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-- . "SUB" for a*b : ar*br - ai*bi
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gen_re_add : IF g_conjugate_b GENERATE
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nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) + prod_ai_bi;
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END GENERATE;
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gen_re_sub : IF NOT g_conjugate_b GENERATE
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nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) - prod_ai_bi;
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END GENERATE;
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-- Im
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-- . "ADD" for a*b : ai*br + ar*bi
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-- . "SUB" for a*conj(b) : ai*br - ar*bi
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gen_im_add : IF NOT g_conjugate_b GENERATE
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nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) + prod_ar_bi;
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END GENERATE;
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gen_im_sub : IF g_conjugate_b GENERATE
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nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) - prod_ar_bi;
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END GENERATE;
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no_adder_reg : IF g_pipeline_adder=0 GENERATE -- wired
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sum_re <= nxt_sum_re;
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sum_im <= nxt_sum_im;
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END GENERATE;
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gen_adder_reg : IF g_pipeline_adder>0 GENERATE -- register
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sum_re <= reg_sum_re;
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sum_im <= reg_sum_im;
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END GENERATE;
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------------------------------------------------------------------------------
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-- Result sum after optional rounding
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------------------------------------------------------------------------------
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nxt_result_re <= RESIZE_NUM(sum_re, g_out_p_w);
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nxt_result_im <= RESIZE_NUM(sum_im, g_out_p_w);
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no_result_reg : IF g_pipeline_output=0 GENERATE -- wired
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result_re <= STD_LOGIC_VECTOR(nxt_result_re);
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result_im <= STD_LOGIC_VECTOR(nxt_result_im);
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END GENERATE;
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gen_result_reg : IF g_pipeline_output>0 GENERATE -- register
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result_re <= STD_LOGIC_VECTOR(reg_result_re);
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result_im <= STD_LOGIC_VECTOR(reg_result_im);
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END GENERATE;
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END ARCHITECTURE;
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