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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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-- Purpose: Verify different architectures of common_complex_mult
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-- Description:
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-- p_verify verifies that the instances of common_complex_mult all yield the
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-- expected results and ASSERTs an ERROR in case they differ.
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-- Usage:
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-- > as 10
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-- > run -all -- signal tb_end will stop the simulation by stopping the clk
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib, tech_mult_lib; --, ip_stratixiv_mult_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.common_lfsr_sequences_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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ENTITY tb_common_complex_mult IS
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GENERIC (
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g_in_dat_w : NATURAL := 4;
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g_out_dat_w : NATURAL := 8; -- g_in_dat_w*2 for multiply and +1 for adder
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g_conjugate_b : BOOLEAN := FALSE; -- When FALSE p = a * b, else p = a * conj(b)
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g_pipeline_input : NATURAL := 1;
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g_pipeline_product : NATURAL := 0;
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g_pipeline_adder : NATURAL := 1;
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g_pipeline_output : NATURAL := 1
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);
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END tb_common_complex_mult;
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ARCHITECTURE tb OF tb_common_complex_mult IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
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CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1;
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CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1);
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CONSTANT c_technology : NATURAL := c_tech_select_default;
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SIGNAL tb_end : STD_LOGIC := '0';
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC := '0';
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SIGNAL random : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
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SIGNAL in_ar : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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SIGNAL in_ai : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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SIGNAL in_br : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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SIGNAL in_bi : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val
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SIGNAL result_val_expected : STD_LOGIC;
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SIGNAL result_val_rtl : STD_LOGIC;
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SIGNAL result_val_ip : STD_LOGIC;
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SIGNAL out_result_re : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- combinatorial result
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SIGNAL out_result_im : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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SIGNAL result_re_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined results
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SIGNAL result_re_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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SIGNAL result_re_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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SIGNAL result_im_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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SIGNAL result_im_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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SIGNAL result_im_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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BEGIN
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clk <= (NOT clk) OR tb_end AFTER clk_period/2;
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random <= func_common_random(random) WHEN rising_edge(clk);
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in_val <= random(random'HIGH);
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-- run -all
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p_in_stimuli : PROCESS
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BEGIN
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rst <= '1';
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in_ar <= TO_SVEC(0, g_in_dat_w);
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in_br <= TO_SVEC(0, g_in_dat_w);
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in_ai <= TO_SVEC(0, g_in_dat_w);
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in_bi <= TO_SVEC(0, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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FOR I IN 0 TO 9 LOOP
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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rst <= '0';
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FOR I IN 0 TO 9 LOOP
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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-- Some special combinations
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in_ar <= TO_SVEC(2, g_in_dat_w);
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in_ai <= TO_SVEC(4, g_in_dat_w);
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in_br <= TO_SVEC(3, g_in_dat_w);
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in_bi <= TO_SVEC(5, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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in_ar <= TO_SVEC( c_max, g_in_dat_w); -- p*p - p*p + j ( p*p + p*p) = 0 + j 2pp or p*p + p*p + j (-p*p + p*p) = 2pp + j 0
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in_ai <= TO_SVEC( c_max, g_in_dat_w);
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in_br <= TO_SVEC( c_max, g_in_dat_w);
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in_bi <= TO_SVEC( c_max, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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in_ar <= TO_SVEC( c_min, g_in_dat_w);
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in_ai <= TO_SVEC( c_min, g_in_dat_w);
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in_br <= TO_SVEC( c_min, g_in_dat_w);
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in_bi <= TO_SVEC( c_min, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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in_ar <= TO_SVEC( c_max, g_in_dat_w);
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in_ai <= TO_SVEC( c_max, g_in_dat_w);
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in_br <= TO_SVEC( c_min, g_in_dat_w);
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in_bi <= TO_SVEC( c_min, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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in_ar <= TO_SVEC( c_max, g_in_dat_w);
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in_ai <= TO_SVEC( c_max, g_in_dat_w);
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in_br <= TO_SVEC(-c_max, g_in_dat_w);
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in_bi <= TO_SVEC(-c_max, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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in_ar <= TO_SVEC( c_min, g_in_dat_w);
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in_ai <= TO_SVEC( c_min, g_in_dat_w);
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in_br <= TO_SVEC(-c_max, g_in_dat_w);
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in_bi <= TO_SVEC(-c_max, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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FOR I IN 0 TO 49 LOOP
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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-- All combinations
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FOR I IN -c_max TO c_max LOOP
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FOR J IN -c_max TO c_max LOOP
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FOR K IN -c_max TO c_max LOOP
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FOR L IN -c_max TO c_max LOOP
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in_ar <= TO_SVEC(I, g_in_dat_w);
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in_ai <= TO_SVEC(K, g_in_dat_w);
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in_br <= TO_SVEC(J, g_in_dat_w);
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in_bi <= TO_SVEC(L, g_in_dat_w);
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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END LOOP;
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END LOOP;
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END LOOP;
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FOR I IN 0 TO 49 LOOP
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WAIT UNTIL rising_edge(clk);
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END LOOP;
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tb_end <= '1';
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WAIT;
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END PROCESS;
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-- Expected combinatorial complex multiply out_result
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out_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", g_out_dat_w);
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out_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", g_out_dat_w);
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u_result_re : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => "SIGNED",
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g_pipeline => c_pipeline,
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g_reset_value => 0,
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g_in_dat_w => g_out_dat_w,
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g_out_dat_w => g_out_dat_w
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_dat => out_result_re,
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out_dat => result_re_expected
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);
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u_result_im : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => "SIGNED",
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g_pipeline => c_pipeline,
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g_reset_value => 0,
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g_in_dat_w => g_out_dat_w,
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g_out_dat_w => g_out_dat_w
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_dat => out_result_im,
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out_dat => result_im_expected
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);
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u_result_val_expected : ENTITY common_components_lib.common_pipeline_sl
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GENERIC MAP (
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g_pipeline => c_pipeline,
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g_reset_value => 0
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_dat => in_val,
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out_dat => result_val_expected
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);
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u_dut_rtl : ENTITY work.common_complex_mult
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GENERIC MAP (
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g_technology => c_technology,
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g_variant => "RTL",
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g_in_a_w => g_in_dat_w,
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g_in_b_w => g_in_dat_w,
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g_out_p_w => g_out_dat_w,
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g_conjugate_b => g_conjugate_b,
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g_pipeline_input => g_pipeline_input,
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g_pipeline_product => g_pipeline_product,
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g_pipeline_adder => g_pipeline_adder,
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g_pipeline_output => g_pipeline_output
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_ar => in_ar,
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in_ai => in_ai,
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in_br => in_br,
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in_bi => in_bi,
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in_val => in_val,
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out_pr => result_re_rtl,
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out_pi => result_im_rtl,
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out_val => result_val_rtl
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);
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u_dut_ip : ENTITY work.common_complex_mult
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GENERIC MAP (
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g_technology => c_technology,
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g_variant => "IP",
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g_in_a_w => g_in_dat_w,
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g_in_b_w => g_in_dat_w,
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g_out_p_w => g_out_dat_w,
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g_conjugate_b => g_conjugate_b,
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g_pipeline_input => g_pipeline_input,
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g_pipeline_product => g_pipeline_product,
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g_pipeline_adder => g_pipeline_adder,
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g_pipeline_output => g_pipeline_output
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)
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PORT MAP (
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rst => rst,
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clk => clk,
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clken => '1',
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in_ar => in_ar,
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in_ai => in_ai,
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in_br => in_br,
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in_bi => in_bi,
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in_val => in_val,
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out_pr => result_re_ip,
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out_pi => result_im_ip,
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out_val => result_val_ip
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);
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p_verify : PROCESS(rst, clk)
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BEGIN
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IF rst='0' THEN
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IF rising_edge(clk) THEN
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ASSERT result_re_rtl = result_re_expected REPORT "Error: RE wrong RTL result" SEVERITY ERROR;
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ASSERT result_im_rtl = result_im_expected REPORT "Error: IM wrong RTL result" SEVERITY ERROR;
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ASSERT result_val_rtl = result_val_expected REPORT "Error: VAL wrong RTL result" SEVERITY ERROR;
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ASSERT result_re_ip = result_re_expected REPORT "Error: RE wrong IP result" SEVERITY ERROR;
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ASSERT result_im_ip = result_im_expected REPORT "Error: IM wrong IP result" SEVERITY ERROR;
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ASSERT result_val_ip = result_val_expected REPORT "Error: VAL wrong IP result" SEVERITY ERROR;
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END IF;
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END IF;
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END PROCESS;
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END tb;
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