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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2009
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, technology_lib;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE technology_lib.technology_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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USE work.tech_mult_component_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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LIBRARY ip_stratixiv_mult_lib;
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--LIBRARY ip_arria10_mult_lib;
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--LIBRARY ip_arria10_mult_rtl_lib;
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--LIBRARY ip_arria10_complex_mult_altmult_complex_150;
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--LIBRARY ip_arria10_e1sg_complex_mult_altmult_complex_170;
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--LIBRARY ip_arria10_complex_mult_rtl_lib;
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--LIBRARY ip_arria10_complex_mult_rtl_canonical_lib;
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ENTITY tech_complex_mult IS
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GENERIC (
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g_sim : BOOLEAN := TRUE;
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g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
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g_technology : NATURAL := c_tech_select_default;
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g_variant : STRING := "IP";
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g_in_a_w : POSITIVE;
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g_in_b_w : POSITIVE;
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g_out_p_w : POSITIVE; -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
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g_conjugate_b : BOOLEAN := FALSE;
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g_pipeline_input : NATURAL := 1; -- 0 or 1
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g_pipeline_product : NATURAL := 0; -- 0 or 1
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g_pipeline_adder : NATURAL := 1; -- 0 or 1
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g_pipeline_output : NATURAL := 1 -- >= 0
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);
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PORT (
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rst : IN STD_LOGIC := '0';
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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in_ar : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
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in_ai : IN STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
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in_br : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
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in_bi : IN STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
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result_re : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
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result_im : OUT STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
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);
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END tech_complex_mult;
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ARCHITECTURE str of tech_complex_mult is
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-- Force to maximum 18 bit width, because:
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-- . the ip_stratixiv_complex_mult is generated for 18b inputs and 36b output and then uses 4 real multipliers and no additional registers
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-- . if one input > 18b then another IP needs to be regenerated and that will use 8 real multipliers and some extra LUTs and registers
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-- . if both inputs > 18b then another IP needs to be regenerated and that will use 16 real multipliers and some extra LUTs and registers
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-- . if the output is set to 18b+18b + 1b =37b to account for the sum then another IP needs to be regenerated and that will use some extra registers
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-- ==> for inputs <= 18b this ip_stratixiv_complex_mult is appropriate and it can not be made parametrisable to fit also inputs > 18b.
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CONSTANT c_dsp_dat_w : NATURAL := 18;
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CONSTANT c_dsp_prod_w : NATURAL := 2*c_dsp_dat_w;
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SIGNAL ar : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
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SIGNAL ai : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
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SIGNAL br : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
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SIGNAL bi : STD_LOGIC_VECTOR(c_dsp_dat_w-1 DOWNTO 0);
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SIGNAL mult_re : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
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SIGNAL mult_im : STD_LOGIC_VECTOR(c_dsp_prod_w-1 DOWNTO 0);
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-- sim_model=1
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SIGNAL result_re_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
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SIGNAL result_im_undelayed : STD_LOGIC_VECTOR(g_in_b_w+g_in_a_w-1 DOWNTO 0);
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begin
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gen_ip_stratixiv_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="IP") GENERATE
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-- Adapt DSP input widths
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ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
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ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
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br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
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bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
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u0 : ip_stratixiv_complex_mult
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PORT MAP (
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aclr => rst,
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clock => clk,
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dataa_imag => ai,
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dataa_real => ar,
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datab_imag => bi,
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datab_real => br,
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ena => clken,
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result_imag => mult_im,
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result_real => mult_re
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);
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-- Back to true input widths and then resize for output width
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result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
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result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
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END GENERATE;
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gen_ip_stratixiv_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_stratixiv AND g_variant="RTL") GENERATE
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u0 : ip_stratixiv_complex_mult_rtl
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GENERIC MAP(
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g_in_a_w => g_in_a_w,
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g_in_b_w => g_in_b_w,
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g_out_p_w => g_out_p_w,
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g_conjugate_b => g_conjugate_b,
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g_pipeline_input => g_pipeline_input,
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g_pipeline_product => g_pipeline_product,
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g_pipeline_adder => g_pipeline_adder,
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g_pipeline_output => g_pipeline_output
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)
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PORT MAP(
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rst => rst,
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clk => clk,
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clken => clken,
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in_ar => in_ar,
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in_ai => in_ai,
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in_br => in_br,
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in_bi => in_bi,
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result_re => result_re,
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result_im => result_im
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);
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END GENERATE;
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-- gen_ip_arria10_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10 AND g_variant="IP") GENERATE
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--
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-- -- Adapt DSP input widths
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-- ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
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-- ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
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-- br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
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-- bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
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--
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-- u0 : ip_arria10_complex_mult
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-- PORT MAP (
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-- aclr => rst,
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-- clock => clk,
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-- dataa_imag => ai,
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-- dataa_real => ar,
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-- datab_imag => bi,
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-- datab_real => br,
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-- ena => clken,
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-- result_imag => mult_im,
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-- result_real => mult_re
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-- );
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--
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-- -- Back to true input widths and then resize for output width
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-- result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
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-- result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
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--
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-- END GENERATE;
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--
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-- -- RTL variant is the same for unb2, unb2a and unb2b
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-- gen_ip_arria10_rtl : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND
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-- ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg ) AND g_variant="RTL") GENERATE
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-- u0 : ip_arria10_complex_mult_rtl
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-- GENERIC MAP(
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-- g_in_a_w => g_in_a_w,
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-- g_in_b_w => g_in_b_w,
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-- g_out_p_w => g_out_p_w,
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-- g_conjugate_b => g_conjugate_b,
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-- g_pipeline_input => g_pipeline_input,
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-- g_pipeline_product => g_pipeline_product,
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-- g_pipeline_adder => g_pipeline_adder,
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-- g_pipeline_output => g_pipeline_output
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-- )
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-- PORT MAP(
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-- rst => rst,
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-- clk => clk,
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-- clken => clken,
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-- in_ar => in_ar,
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-- in_ai => in_ai,
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-- in_br => in_br,
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-- in_bi => in_bi,
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-- result_re => result_re,
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-- result_im => result_im
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-- );
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-- END GENERATE;
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--
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-- gen_ip_arria10_rtl_canonical : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND
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-- ((g_technology=c_tech_arria10 OR g_technology=c_tech_arria10_e3sge3 OR g_technology=c_tech_arria10_e1sg ) AND g_variant="RTL_C") GENERATE
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-- u0 : ip_arria10_complex_mult_rtl_canonical
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-- GENERIC MAP(
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-- g_in_a_w => g_in_a_w,
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-- g_in_b_w => g_in_b_w,
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-- g_out_p_w => g_out_p_w,
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---- g_conjugate_b => g_conjugate_b, -- NOT SUPPORTED
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-- g_pipeline_input => g_pipeline_input,
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-- g_pipeline_product => g_pipeline_product,
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-- g_pipeline_adder => g_pipeline_adder,
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-- g_pipeline_output => g_pipeline_output
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-- )
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-- PORT MAP(
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-- rst => rst,
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-- clk => clk,
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-- clken => clken,
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-- in_ar => in_ar,
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-- in_ai => in_ai,
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-- in_br => in_br,
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-- in_bi => in_bi,
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-- result_re => result_re,
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-- result_im => result_im
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-- );
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-- END GENERATE;
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--
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--
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-- gen_ip_arria10_e1sg_ip : IF (g_sim=FALSE OR (g_sim=TRUE AND g_sim_level=0)) AND (g_technology=c_tech_arria10_e1sg AND g_variant="IP") GENERATE
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--
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-- -- Adapt DSP input widths
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-- ar <= RESIZE_SVEC(in_ar, c_dsp_dat_w);
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-- ai <= RESIZE_SVEC(in_ai, c_dsp_dat_w);
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-- br <= RESIZE_SVEC(in_br, c_dsp_dat_w);
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-- bi <= RESIZE_SVEC(in_bi, c_dsp_dat_w) WHEN g_conjugate_b=FALSE ELSE TO_SVEC(-TO_SINT(in_bi), c_dsp_dat_w);
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--
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--
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-- u0 : ip_arria10_e1sg_complex_mult
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-- PORT MAP (
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-- aclr => rst,
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-- clock => clk,
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-- dataa_imag => ai,
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-- dataa_real => ar,
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-- datab_imag => bi,
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-- datab_real => br,
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-- ena => clken,
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-- result_imag => mult_im,
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-- result_real => mult_re
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-- );
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--
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-- -- Back to true input widths and then resize for output width
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-- result_re <= RESIZE_SVEC(mult_re, g_out_p_w);
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-- result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
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--
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-- END GENERATE;
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-------------------------------------------------------------------------------
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-- Model: forward concatenated inputs to the 'result' output
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--
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-- Example:
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-- ______
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-- Input B.real (in_br) = 0x1111 --> | |
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-- .imag (in_bi) = 0xBBBB --> | |
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-- | mult | --> Output result.real = 0x00000000
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-- Input A.real (in_ar) = 0x0000 --> | | .imag = 0xBBBBAAAA
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-- .imag (in_ai) = 0xAAAA --> |______|
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--
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-- Note: this model is synthsizable as well.
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--
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-------------------------------------------------------------------------------
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gen_sim_level_1 : IF g_sim=TRUE AND g_sim_level=1 GENERATE --FIXME: g_sim required? This is synthesizable.
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result_re_undelayed <= in_br & in_ar;
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result_im_undelayed <= in_bi & in_ai;
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u_common_pipeline_re : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => 3,
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g_in_dat_w => g_in_b_w+g_in_a_w,
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g_out_dat_w => g_out_p_w
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)
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port map (
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clk => clk,
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in_dat => result_re_undelayed,
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out_dat => result_re
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);
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u_common_pipeline_im : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => 3,
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g_in_dat_w => g_in_b_w+g_in_a_w,
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g_out_dat_w => g_out_p_w
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)
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port map (
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clk => clk,
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in_dat => result_im_undelayed,
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out_dat => result_im
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);
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END GENERATE;
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end str;
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