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-------------------------------------------------------------------------------
2
--
3
-- Copyright (C) 2014
4
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6
--
7
-- This program is free software: you can redistribute it and/or modify
8
-- it under the terms of the GNU General Public License as published by
9
-- the Free Software Foundation, either version 3 of the License, or
10
-- (at your option) any later version.
11
--
12
-- This program is distributed in the hope that it will be useful,
13
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
14
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15
-- GNU General Public License for more details.
16
--
17
-- You should have received a copy of the GNU General Public License
18
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
19
--
20
-------------------------------------------------------------------------------
21
 
22
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
23
 
24
LIBRARY IEEE;
25
USE IEEE.STD_LOGIC_1164.ALL;
26
 
27
PACKAGE tech_mult_component_pkg IS
28
 
29
  -----------------------------------------------------------------------------
30
  -- Stratix IV components
31
  -----------------------------------------------------------------------------
32
 
33
  COMPONENT ip_stratixiv_complex_mult IS
34
  PORT
35
  (
36
    aclr          : IN STD_LOGIC ;
37
    clock         : IN STD_LOGIC ;
38
    dataa_imag    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
39
    dataa_real    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
40
    datab_imag    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
41
    datab_real    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
42
    ena           : IN STD_LOGIC ;
43
    result_imag   : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
44
    result_real   : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
45
  );
46
  END COMPONENT;
47
 
48
  COMPONENT ip_stratixiv_complex_mult_rtl IS
49
  GENERIC (
50
    g_in_a_w           : POSITIVE := 18;
51
    g_in_b_w           : POSITIVE := 18;
52
    g_out_p_w          : POSITIVE := 36;
53
    g_conjugate_b      : BOOLEAN := FALSE;
54
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
55
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
56
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
57
    g_pipeline_output  : NATURAL := 1       -- >= 0
58
  );
59
  PORT (
60
    rst        : IN   STD_LOGIC := '0';
61
    clk        : IN   STD_LOGIC;
62
    clken      : IN   STD_LOGIC := '1';
63
    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
64
    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
65
    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
66
    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
67
    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
68
    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
69
  );
70
  END COMPONENT;
71
 
72
  COMPONENT ip_stratixiv_mult IS
73
  GENERIC (
74
    g_in_a_w           : POSITIVE := 18;
75
    g_in_b_w           : POSITIVE := 18;
76
    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
77
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
78
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
79
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
80
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
81
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
82
  );
83
  PORT (
84
    clk        : IN  STD_LOGIC;
85
    clken      : IN  STD_LOGIC := '1';
86
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
87
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
88
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
89
  );
90
  END COMPONENT;
91
 
92
  COMPONENT ip_stratixiv_mult_rtl IS
93
  GENERIC (
94
    g_in_a_w           : POSITIVE := 18;
95
    g_in_b_w           : POSITIVE := 18;
96
    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
97
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
98
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
99
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
100
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
101
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
102
  );
103
  PORT (
104
    rst        : IN  STD_LOGIC;
105
    clk        : IN  STD_LOGIC;
106
    clken      : IN  STD_LOGIC := '1';
107
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
108
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
109
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
110
  );
111
  END COMPONENT;
112
 
113
  COMPONENT ip_stratixiv_mult_add2_rtl IS
114
  GENERIC (
115
    g_in_a_w           : POSITIVE;
116
    g_in_b_w           : POSITIVE;
117
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(2)
118
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
119
    g_add_sub          : STRING := "ADD";   -- or "SUB"
120
    g_nof_mult         : INTEGER := 2;      -- fixed
121
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
122
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
123
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
124
    g_pipeline_output  : NATURAL := 1       -- >= 0
125
  );
126
  PORT (
127
    rst        : IN  STD_LOGIC := '0';
128
    clk        : IN  STD_LOGIC;
129
    clken      : IN  STD_LOGIC := '1';
130
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
131
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
132
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
133
  );
134
  END COMPONENT;
135
 
136
  COMPONENT ip_stratixiv_mult_add4_rtl IS
137
  GENERIC (
138
    g_in_a_w           : POSITIVE;
139
    g_in_b_w           : POSITIVE;
140
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(4)
141
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
142
    g_add_sub0         : STRING := "ADD";   -- or "SUB"
143
    g_add_sub1         : STRING := "ADD";   -- or "SUB"
144
    g_add_sub          : STRING := "ADD";   -- or "SUB" only available with rtl architecture
145
    g_nof_mult         : INTEGER := 4;      -- fixed
146
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
147
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
148
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1, first sum
149
    g_pipeline_output  : NATURAL := 1       -- >= 0,   second sum and optional rounding
150
  );
151
  PORT (
152
    rst        : IN  STD_LOGIC := '0';
153
    clk        : IN  STD_LOGIC;
154
    clken      : IN  STD_LOGIC := '1';
155
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
156
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
157
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
158
  );
159
  END COMPONENT;
160
 
161
  -----------------------------------------------------------------------------
162
  -- Arria 10 components
163
  -----------------------------------------------------------------------------
164
 
165
  COMPONENT ip_arria10_complex_mult is
166
  PORT (
167
    dataa_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --  complex_input.dataa_real
168
    dataa_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .dataa_imag
169
    datab_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_real
170
    datab_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_imag
171
    clock       : in  std_logic                     := '0';             --               .clk
172
    aclr        : in  std_logic                     := '0';             --               .aclr
173
    ena         : in  std_logic                     := '0';             --               .ena
174
    result_real : out std_logic_vector(35 downto 0);                    -- complex_output.result_real
175
    result_imag : out std_logic_vector(35 downto 0)                     --               .result_imag
176
  );
177
  END COMPONENT;
178
 
179
 
180
  COMPONENT ip_arria10_complex_mult_rtl IS
181
  GENERIC (
182
    g_in_a_w           : POSITIVE := 18;
183
    g_in_b_w           : POSITIVE := 18;
184
    g_out_p_w          : POSITIVE := 36;
185
    g_conjugate_b      : BOOLEAN := FALSE;
186
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
187
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
188
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
189
    g_pipeline_output  : NATURAL := 1       -- >= 0
190
  );
191
  PORT (
192
    rst        : IN   STD_LOGIC := '0';
193
    clk        : IN   STD_LOGIC;
194
    clken      : IN   STD_LOGIC := '1';
195
    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
196
    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
197
    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
198
    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
199
    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
200
    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
201
  );
202
  END COMPONENT;
203
 
204
  COMPONENT ip_arria10_complex_mult_rtl_canonical IS
205
  GENERIC (
206
    g_in_a_w           : POSITIVE;
207
    g_in_b_w           : POSITIVE;
208
    g_out_p_w          : POSITIVE;          -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
209
--    g_conjugate_b      : BOOLEAN := FALSE;
210
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
211
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
212
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
213
    g_pipeline_output  : NATURAL := 1       -- >= 0
214
  );
215
  PORT (
216
    rst        : IN   STD_LOGIC := '0';
217
    clk        : IN   STD_LOGIC;
218
    clken      : IN   STD_LOGIC := '1';
219
    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
220
    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
221
    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
222
    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
223
    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
224
    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
225
  );
226
  END COMPONENT;
227
 
228
  COMPONENT ip_arria10_mult IS
229
  GENERIC (
230
    g_in_a_w           : POSITIVE := 18;      -- Width of the data A port
231
    g_in_b_w           : POSITIVE := 18;      -- Width of the data B port
232
    g_out_p_w          : POSITIVE := 36;      -- Width of the result port
233
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
234
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
235
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
236
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
237
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
238
  );
239
  PORT (
240
    clk        : IN  STD_LOGIC;
241
    clken      : IN  STD_LOGIC := '1';
242
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
243
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
244
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
245
  );
246
  END COMPONENT;
247
 
248
  COMPONENT ip_arria10_mult_rtl IS
249
  GENERIC (
250
    g_in_a_w           : POSITIVE := 18;
251
    g_in_b_w           : POSITIVE := 18;
252
    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
253
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
254
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
255
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
256
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
257
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
258
  );
259
  PORT (
260
    rst        : IN  STD_LOGIC;
261
    clk        : IN  STD_LOGIC;
262
    clken      : IN  STD_LOGIC := '1';
263
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
264
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
265
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
266
  );
267
  END COMPONENT;
268
 
269
 
270
  -----------------------------------------------------------------------------
271
  -- Arria 10 e3sge3 components
272
  -----------------------------------------------------------------------------
273
 
274
  COMPONENT ip_arria10_e3sge3_mult_add4_rtl IS
275
  GENERIC (
276
    g_in_a_w           : POSITIVE;
277
    g_in_b_w           : POSITIVE;
278
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(4)
279
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
280
    g_add_sub0         : STRING := "ADD";   -- or "SUB"
281
    g_add_sub1         : STRING := "ADD";   -- or "SUB"
282
    g_add_sub          : STRING := "ADD";   -- or "SUB" only available with rtl architecture
283
    g_nof_mult         : INTEGER := 4;      -- fixed
284
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
285
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
286
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1, first sum
287
    g_pipeline_output  : NATURAL := 1       -- >= 0,   second sum and optional rounding
288
  );
289
  PORT (
290
    rst        : IN  STD_LOGIC := '0';
291
    clk        : IN  STD_LOGIC;
292
    clken      : IN  STD_LOGIC := '1';
293
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
294
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
295
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
296
  );
297
  END COMPONENT;
298
 
299
  -----------------------------------------------------------------------------
300
  -- Arria 10 e1sg components
301
  -----------------------------------------------------------------------------
302
  COMPONENT ip_arria10_e1sg_mult_add2_rtl IS
303
  GENERIC (
304
    g_in_a_w           : POSITIVE;
305
    g_in_b_w           : POSITIVE;
306
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(2)
307
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
308
    g_add_sub          : STRING := "ADD";   -- or "SUB"
309
    g_nof_mult         : INTEGER := 2;      -- fixed
310
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
311
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
312
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
313
    g_pipeline_output  : NATURAL := 1       -- >= 0
314
  );
315
  PORT (
316
    rst        : IN  STD_LOGIC := '0';
317
    clk        : IN  STD_LOGIC;
318
    clken      : IN  STD_LOGIC := '1';
319
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
320
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
321
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
322
  );
323
  END COMPONENT;
324
 
325
  COMPONENT ip_arria10_e1sg_mult_add4_rtl IS
326
  GENERIC (
327
    g_in_a_w           : POSITIVE;
328
    g_in_b_w           : POSITIVE;
329
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(4)
330
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
331
    g_add_sub0         : STRING := "ADD";   -- or "SUB"
332
    g_add_sub1         : STRING := "ADD";   -- or "SUB"
333
    g_add_sub          : STRING := "ADD";   -- or "SUB" only available with rtl architecture
334
    g_nof_mult         : INTEGER := 4;      -- fixed
335
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
336
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
337
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1, first sum
338
    g_pipeline_output  : NATURAL := 1       -- >= 0,   second sum and optional rounding
339
  );
340
  PORT (
341
    rst        : IN  STD_LOGIC := '0';
342
    clk        : IN  STD_LOGIC;
343
    clken      : IN  STD_LOGIC := '1';
344
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
345
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
346
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
347
  );
348
  END COMPONENT;
349
 
350
  COMPONENT ip_arria10_e1sg_complex_mult is
351
  PORT (
352
    dataa_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --  complex_input.dataa_real
353
    dataa_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .dataa_imag
354
    datab_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_real
355
    datab_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_imag
356
    clock       : in  std_logic                     := '0';             --               .clk
357
    aclr        : in  std_logic                     := '0';             --               .aclr
358
    ena         : in  std_logic                     := '0';             --               .ena
359
    result_real : out std_logic_vector(35 downto 0);                    -- complex_output.result_real
360
    result_imag : out std_logic_vector(35 downto 0)                     --               .result_imag
361
  );
362
  END COMPONENT;
363
END tech_mult_component_pkg;

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