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[/] [astron_multiplier/] [trunk/] [tech_mult_component_pkg.vhd] - Blame information for rev 3

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1 2 danv 
-------------------------------------------------------------------------------
2 
--
3 3 danv 
-- Copyright 2020
4 2 danv 
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5 
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 3 danv 
--
7 
-- Licensed under the Apache License, Version 2.0 (the "License");
8 
-- you may not use this file except in compliance with the License.
9 
-- You may obtain a copy of the License at
10 
--
11 
--     http://www.apache.org/licenses/LICENSE-2.0
12 
--
13 
-- Unless required by applicable law or agreed to in writing, software
14 
-- distributed under the License is distributed on an "AS IS" BASIS,
15 
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 
-- See the License for the specific language governing permissions and
17 
-- limitations under the License.
18 2 danv 
--
19 
-------------------------------------------------------------------------------
20 
 
21 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
22 
 
23 
LIBRARY IEEE;
24 
USE IEEE.STD_LOGIC_1164.ALL;
25 
 
26 
PACKAGE tech_mult_component_pkg IS
27 
 
28 
  -----------------------------------------------------------------------------
29 
  -- Stratix IV components
30 
  -----------------------------------------------------------------------------
31 
 
32 
  COMPONENT ip_stratixiv_complex_mult IS
33 
  PORT
34 
  (
35 
    aclr          : IN STD_LOGIC ;
36 
    clock         : IN STD_LOGIC ;
37 
    dataa_imag    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
38 
    dataa_real    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
39 
    datab_imag    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
40 
    datab_real    : IN STD_LOGIC_VECTOR (17 DOWNTO 0);
41 
    ena           : IN STD_LOGIC ;
42 
    result_imag   : OUT STD_LOGIC_VECTOR (35 DOWNTO 0);
43 
    result_real   : OUT STD_LOGIC_VECTOR (35 DOWNTO 0)
44 
  );
45 
  END COMPONENT;
46 
 
47 
  COMPONENT ip_stratixiv_complex_mult_rtl IS
48 
  GENERIC (
49 
    g_in_a_w           : POSITIVE := 18;
50 
    g_in_b_w           : POSITIVE := 18;
51 
    g_out_p_w          : POSITIVE := 36;
52 
    g_conjugate_b      : BOOLEAN := FALSE;
53 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
54 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
55 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
56 
    g_pipeline_output  : NATURAL := 1       -- >= 0
57 
  );
58 
  PORT (
59 
    rst        : IN   STD_LOGIC := '0';
60 
    clk        : IN   STD_LOGIC;
61 
    clken      : IN   STD_LOGIC := '1';
62 
    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
63 
    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
64 
    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
65 
    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
66 
    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
67 
    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
68 
  );
69 
  END COMPONENT;
70 
 
71 
  COMPONENT ip_stratixiv_mult IS
72 
  GENERIC (
73 
    g_in_a_w           : POSITIVE := 18;
74 
    g_in_b_w           : POSITIVE := 18;
75 
    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
76 
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
77 
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
78 
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
79 
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
80 
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
81 
  );
82 
  PORT (
83 
    clk        : IN  STD_LOGIC;
84 
    clken      : IN  STD_LOGIC := '1';
85 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
86 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
87 
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
88 
  );
89 
  END COMPONENT;
90 
 
91 
  COMPONENT ip_stratixiv_mult_rtl IS
92 
  GENERIC (
93 
    g_in_a_w           : POSITIVE := 18;
94 
    g_in_b_w           : POSITIVE := 18;
95 
    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
96 
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
97 
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
98 
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
99 
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
100 
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
101 
  );
102 
  PORT (
103 
    rst        : IN  STD_LOGIC;
104 
    clk        : IN  STD_LOGIC;
105 
    clken      : IN  STD_LOGIC := '1';
106 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
107 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
108 
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
109 
  );
110 
  END COMPONENT;
111 
 
112 
  COMPONENT ip_stratixiv_mult_add2_rtl IS
113 
  GENERIC (
114 
    g_in_a_w           : POSITIVE;
115 
    g_in_b_w           : POSITIVE;
116 
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(2)
117 
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
118 
    g_add_sub          : STRING := "ADD";   -- or "SUB"
119 
    g_nof_mult         : INTEGER := 2;      -- fixed
120 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
121 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
122 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
123 
    g_pipeline_output  : NATURAL := 1       -- >= 0
124 
  );
125 
  PORT (
126 
    rst        : IN  STD_LOGIC := '0';
127 
    clk        : IN  STD_LOGIC;
128 
    clken      : IN  STD_LOGIC := '1';
129 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
130 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
131 
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
132 
  );
133 
  END COMPONENT;
134 
 
135 
  COMPONENT ip_stratixiv_mult_add4_rtl IS
136 
  GENERIC (
137 
    g_in_a_w           : POSITIVE;
138 
    g_in_b_w           : POSITIVE;
139 
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(4)
140 
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
141 
    g_add_sub0         : STRING := "ADD";   -- or "SUB"
142 
    g_add_sub1         : STRING := "ADD";   -- or "SUB"
143 
    g_add_sub          : STRING := "ADD";   -- or "SUB" only available with rtl architecture
144 
    g_nof_mult         : INTEGER := 4;      -- fixed
145 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
146 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
147 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1, first sum
148 
    g_pipeline_output  : NATURAL := 1       -- >= 0,   second sum and optional rounding
149 
  );
150 
  PORT (
151 
    rst        : IN  STD_LOGIC := '0';
152 
    clk        : IN  STD_LOGIC;
153 
    clken      : IN  STD_LOGIC := '1';
154 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
155 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
156 
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
157 
  );
158 
  END COMPONENT;
159 
 
160 
  -----------------------------------------------------------------------------
161 
  -- Arria 10 components
162 
  -----------------------------------------------------------------------------
163 
 
164 
  COMPONENT ip_arria10_complex_mult is
165 
  PORT (
166 
    dataa_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --  complex_input.dataa_real
167 
    dataa_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .dataa_imag
168 
    datab_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_real
169 
    datab_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_imag
170 
    clock       : in  std_logic                     := '0';             --               .clk
171 
    aclr        : in  std_logic                     := '0';             --               .aclr
172 
    ena         : in  std_logic                     := '0';             --               .ena
173 
    result_real : out std_logic_vector(35 downto 0);                    -- complex_output.result_real
174 
    result_imag : out std_logic_vector(35 downto 0)                     --               .result_imag
175 
  );
176 
  END COMPONENT;
177 
 
178 
 
179 
  COMPONENT ip_arria10_complex_mult_rtl IS
180 
  GENERIC (
181 
    g_in_a_w           : POSITIVE := 18;
182 
    g_in_b_w           : POSITIVE := 18;
183 
    g_out_p_w          : POSITIVE := 36;
184 
    g_conjugate_b      : BOOLEAN := FALSE;
185 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
186 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
187 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
188 
    g_pipeline_output  : NATURAL := 1       -- >= 0
189 
  );
190 
  PORT (
191 
    rst        : IN   STD_LOGIC := '0';
192 
    clk        : IN   STD_LOGIC;
193 
    clken      : IN   STD_LOGIC := '1';
194 
    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
195 
    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
196 
    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
197 
    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
198 
    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
199 
    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
200 
  );
201 
  END COMPONENT;
202 
 
203 
  COMPONENT ip_arria10_complex_mult_rtl_canonical IS
204 
  GENERIC (
205 
    g_in_a_w           : POSITIVE;
206 
    g_in_b_w           : POSITIVE;
207 
    g_out_p_w          : POSITIVE;          -- default use g_out_p_w = g_in_a_w+g_in_b_w = c_prod_w
208 
--    g_conjugate_b      : BOOLEAN := FALSE;
209 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
210 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
211 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
212 
    g_pipeline_output  : NATURAL := 1       -- >= 0
213 
  );
214 
  PORT (
215 
    rst        : IN   STD_LOGIC := '0';
216 
    clk        : IN   STD_LOGIC;
217 
    clken      : IN   STD_LOGIC := '1';
218 
    in_ar      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
219 
    in_ai      : IN   STD_LOGIC_VECTOR(g_in_a_w-1 DOWNTO 0);
220 
    in_br      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
221 
    in_bi      : IN   STD_LOGIC_VECTOR(g_in_b_w-1 DOWNTO 0);
222 
    result_re  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0);
223 
    result_im  : OUT  STD_LOGIC_VECTOR(g_out_p_w-1 DOWNTO 0)
224 
  );
225 
  END COMPONENT;
226 
 
227 
  COMPONENT ip_arria10_mult IS
228 
  GENERIC (
229 
    g_in_a_w           : POSITIVE := 18;      -- Width of the data A port
230 
    g_in_b_w           : POSITIVE := 18;      -- Width of the data B port
231 
    g_out_p_w          : POSITIVE := 36;      -- Width of the result port
232 
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
233 
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
234 
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
235 
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
236 
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
237 
  );
238 
  PORT (
239 
    clk        : IN  STD_LOGIC;
240 
    clken      : IN  STD_LOGIC := '1';
241 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
242 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
243 
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
244 
  );
245 
  END COMPONENT;
246 
 
247 
  COMPONENT ip_arria10_mult_rtl IS
248 
  GENERIC (
249 
    g_in_a_w           : POSITIVE := 18;
250 
    g_in_b_w           : POSITIVE := 18;
251 
    g_out_p_w          : POSITIVE := 36;      -- c_prod_w = g_in_a_w+g_in_b_w, use smaller g_out_p_w to truncate MSbits, or larger g_out_p_w to extend MSbits
252 
    g_nof_mult         : POSITIVE := 1;       -- using 2 for 18x18, 4 for 9x9 may yield better results when inferring * is used
253 
    g_pipeline_input   : NATURAL  := 1;        -- 0 or 1
254 
    g_pipeline_product : NATURAL  := 1;        -- 0 or 1
255 
    g_pipeline_output  : NATURAL  := 1;        -- >= 0
256 
    g_representation   : STRING   := "SIGNED"   -- or "UNSIGNED"
257 
  );
258 
  PORT (
259 
    rst        : IN  STD_LOGIC;
260 
    clk        : IN  STD_LOGIC;
261 
    clken      : IN  STD_LOGIC := '1';
262 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
263 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
264 
    out_p      : OUT STD_LOGIC_VECTOR(g_nof_mult*(g_in_a_w+g_in_b_w)-1 DOWNTO 0)
265 
  );
266 
  END COMPONENT;
267 
 
268 
 
269 
  -----------------------------------------------------------------------------
270 
  -- Arria 10 e3sge3 components
271 
  -----------------------------------------------------------------------------
272 
 
273 
  COMPONENT ip_arria10_e3sge3_mult_add4_rtl IS
274 
  GENERIC (
275 
    g_in_a_w           : POSITIVE;
276 
    g_in_b_w           : POSITIVE;
277 
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(4)
278 
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
279 
    g_add_sub0         : STRING := "ADD";   -- or "SUB"
280 
    g_add_sub1         : STRING := "ADD";   -- or "SUB"
281 
    g_add_sub          : STRING := "ADD";   -- or "SUB" only available with rtl architecture
282 
    g_nof_mult         : INTEGER := 4;      -- fixed
283 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
284 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
285 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1, first sum
286 
    g_pipeline_output  : NATURAL := 1       -- >= 0,   second sum and optional rounding
287 
  );
288 
  PORT (
289 
    rst        : IN  STD_LOGIC := '0';
290 
    clk        : IN  STD_LOGIC;
291 
    clken      : IN  STD_LOGIC := '1';
292 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
293 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
294 
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
295 
  );
296 
  END COMPONENT;
297 
 
298 
  -----------------------------------------------------------------------------
299 
  -- Arria 10 e1sg components
300 
  -----------------------------------------------------------------------------
301 
  COMPONENT ip_arria10_e1sg_mult_add2_rtl IS
302 
  GENERIC (
303 
    g_in_a_w           : POSITIVE;
304 
    g_in_b_w           : POSITIVE;
305 
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(2)
306 
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
307 
    g_add_sub          : STRING := "ADD";   -- or "SUB"
308 
    g_nof_mult         : INTEGER := 2;      -- fixed
309 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
310 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
311 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1
312 
    g_pipeline_output  : NATURAL := 1       -- >= 0
313 
  );
314 
  PORT (
315 
    rst        : IN  STD_LOGIC := '0';
316 
    clk        : IN  STD_LOGIC;
317 
    clken      : IN  STD_LOGIC := '1';
318 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
319 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
320 
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
321 
  );
322 
  END COMPONENT;
323 
 
324 
  COMPONENT ip_arria10_e1sg_mult_add4_rtl IS
325 
  GENERIC (
326 
    g_in_a_w           : POSITIVE;
327 
    g_in_b_w           : POSITIVE;
328 
    g_res_w            : POSITIVE;          -- g_in_a_w + g_in_b_w + log2(4)
329 
    g_force_dsp        : BOOLEAN := TRUE;   -- when TRUE resize input width to >= 18
330 
    g_add_sub0         : STRING := "ADD";   -- or "SUB"
331 
    g_add_sub1         : STRING := "ADD";   -- or "SUB"
332 
    g_add_sub          : STRING := "ADD";   -- or "SUB" only available with rtl architecture
333 
    g_nof_mult         : INTEGER := 4;      -- fixed
334 
    g_pipeline_input   : NATURAL := 1;      -- 0 or 1
335 
    g_pipeline_product : NATURAL := 0;      -- 0 or 1
336 
    g_pipeline_adder   : NATURAL := 1;      -- 0 or 1, first sum
337 
    g_pipeline_output  : NATURAL := 1       -- >= 0,   second sum and optional rounding
338 
  );
339 
  PORT (
340 
    rst        : IN  STD_LOGIC := '0';
341 
    clk        : IN  STD_LOGIC;
342 
    clken      : IN  STD_LOGIC := '1';
343 
    in_a       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_a_w-1 DOWNTO 0);
344 
    in_b       : IN  STD_LOGIC_VECTOR(g_nof_mult*g_in_b_w-1 DOWNTO 0);
345 
    res        : OUT STD_LOGIC_VECTOR(g_res_w-1 DOWNTO 0)
346 
  );
347 
  END COMPONENT;
348 
 
349 
  COMPONENT ip_arria10_e1sg_complex_mult is
350 
  PORT (
351 
    dataa_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --  complex_input.dataa_real
352 
    dataa_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .dataa_imag
353 
    datab_real  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_real
354 
    datab_imag  : in  std_logic_vector(17 downto 0) := (others => '0'); --               .datab_imag
355 
    clock       : in  std_logic                     := '0';             --               .clk
356 
    aclr        : in  std_logic                     := '0';             --               .aclr
357 
    ena         : in  std_logic                     := '0';             --               .ena
358 
    result_real : out std_logic_vector(35 downto 0);                    -- complex_output.result_real
359 
    result_imag : out std_logic_vector(35 downto 0)                     --               .result_imag
360 
  );
361 
  END COMPONENT;
362 
END tech_mult_component_pkg;

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