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--------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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--------------------------------------------------------------------------------
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library ieee, common_pkg_lib, common_components_lib;
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use IEEE.std_logic_1164.all;
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use common_pkg_lib.common_pkg.all;
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entity rTwoBFStage is
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generic (
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-- generics for this stage
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g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
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g_stage : natural; -- The stage indices are ..., 3, 2, 1. The input stage has the highest index, the output stage has index 1.
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g_bf_lat : natural := 1; -- Digital pipelining latency
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-- generics for rTwoBF
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g_bf_use_zdly : natural := 1; -- >= 1. Stage high downto g_bf_use_zdly will will use g_bf_in_a_zdly and g_bf_out_zdly
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g_bf_in_a_zdly : natural := 0; -- g_bf_in_a_zdly+g_bf_out_d_zdly must be <= the stage z^(-1) delay, note that stage 1 has only one z^(-1) delay
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g_bf_out_d_zdly : natural := 0 -- The stage z^(-1) delays are ..., 4, 2, 1.
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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in_re : in std_logic_vector;
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in_im : in std_logic_vector;
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in_val : in std_logic;
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in_sel : in std_logic;
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out_re : out std_logic_vector;
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out_im : out std_logic_vector;
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out_val : out std_logic;
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out_sel : out std_logic
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);
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end entity rTwoBFStage;
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architecture str of rTwoBFStage is
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-- Optionally move some z-1 delay into this BF stage, default 0
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constant c_bf_in_a_zdly : natural := sel_a_b(g_stage >= g_bf_use_zdly, g_bf_in_a_zdly, 0);
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constant c_bf_out_b_zdly : natural := sel_a_b(g_stage >= g_bf_use_zdly, g_bf_out_d_zdly, 0);
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constant c_bf_zdly : natural := c_bf_in_a_zdly+c_bf_out_b_zdly;
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constant c_feedback_zdly : natural := pow2(g_stage-1);
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-- The BF adds, subtracts or passes the data on, so typically c_out_dat_w = c_in_dat_w + 1
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constant c_in_dat_w : natural := in_re'length; -- re and im have same width
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constant c_out_dat_w : natural := out_re'length; -- re and im have same width
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-- Concatenate im & re into complex data to potentially ease synthesis to make more efficient use of block RAM memory for z-1 data feedback line
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signal bf_complex : std_logic_vector(c_nof_complex*c_in_dat_w-1 downto 0);
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signal bf_complex_dly : std_logic_vector(bf_complex'range);
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signal bf_re : std_logic_vector(in_re'range);
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signal bf_re_dly : std_logic_vector(in_re'range);
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signal bf_im : std_logic_vector(in_im'range);
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signal bf_im_dly : std_logic_vector(in_im'range);
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signal bf_sel : std_logic;
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signal bf_val : std_logic;
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signal bf_val_dly : std_logic;
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signal stage_complex : std_logic_vector(c_nof_complex*c_out_dat_w-1 downto 0);
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signal stage_complex_dly : std_logic_vector(stage_complex'range);
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signal stage_re : std_logic_vector(out_re'range);
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signal stage_im : std_logic_vector(out_im'range);
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signal stage_sel : std_logic;
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signal stage_val : std_logic;
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begin
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------------------------------------------------------------------------------
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-- butterfly
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------------------------------------------------------------------------------
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u_bf_re : entity work.rTwoBF
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generic map (
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g_in_a_zdly => c_bf_in_a_zdly,
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g_out_d_zdly => c_bf_out_b_zdly
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)
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port map (
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clk => clk,
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in_a => bf_re_dly,
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in_b => in_re,
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in_sel => in_sel,
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in_val => in_val,
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out_c => stage_re,
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out_d => bf_re
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);
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u_bf_im : entity work.rTwoBF
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generic map (
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g_in_a_zdly => c_bf_in_a_zdly,
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g_out_d_zdly => c_bf_out_b_zdly
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)
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port map (
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clk => clk,
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in_a => bf_im_dly,
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in_b => in_im,
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in_sel => in_sel,
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in_val => in_val,
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out_c => stage_im,
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out_d => bf_im
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);
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------------------------------------------------------------------------------
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-- feedback fifo
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------------------------------------------------------------------------------
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bf_sel <= in_sel;
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bf_val <= in_val;
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bf_complex <= bf_im & bf_re;
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bf_re_dly <= bf_complex_dly( c_in_dat_w-1 downto 0);
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bf_im_dly <= bf_complex_dly(2*c_in_dat_w-1 downto c_in_dat_w);
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-- share FIFO for Im & Re
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u_feedback : entity common_components_lib.common_delay
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generic map (
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g_dat_w => bf_complex'length,
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g_depth => c_feedback_zdly*(2**g_nof_chan)-c_bf_zdly
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)
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port map (
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clk => clk,
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in_dat => bf_complex,
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in_val => bf_val,
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out_dat => bf_complex_dly
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);
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-- compensate for feedback fifo
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u_stage_sel : entity common_components_lib.common_bit_delay
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generic map (
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g_depth => c_feedback_zdly*(2**g_nof_chan)
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)
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port map (
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clk => clk,
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rst => rst,
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in_clr => '0',
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in_val => bf_val,
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in_bit => bf_sel,
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out_bit => stage_sel
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);
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-- compensate for feedback fifo
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u_stage_val : entity common_components_lib.common_bit_delay
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generic map (
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g_depth => c_feedback_zdly*(2**g_nof_chan)
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)
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port map (
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clk => clk,
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rst => rst,
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in_clr => '0',
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in_val => bf_val,
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in_bit => bf_val,
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out_bit => bf_val_dly
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);
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-- after the z^(-1) stage delay the bf_val_dly goes high and remains high and acts as an enable for in_val to out_val
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stage_val <= in_val and bf_val_dly;
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------------------------------------------------------------------------------
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-- stage output pipelining
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------------------------------------------------------------------------------
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stage_complex <= stage_im & stage_re;
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u_pipeline_out : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => g_bf_lat,
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g_in_dat_w => stage_complex'length,
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g_out_dat_w => stage_complex'length
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)
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port map (
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clk => clk,
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in_dat => stage_complex,
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out_dat => stage_complex_dly
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);
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out_re <= stage_complex_dly( c_out_dat_w-1 downto 0);
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out_im <= stage_complex_dly(2*c_out_dat_w-1 downto c_out_dat_w);
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u_out_sel : entity common_components_lib.common_pipeline_sl
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generic map (
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g_pipeline => g_bf_lat
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)
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port map (
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clk => clk,
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in_dat => stage_sel,
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out_dat => out_sel
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);
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u_out_val : entity common_components_lib.common_pipeline_sl
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generic map (
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g_pipeline => g_bf_lat
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)
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port map (
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clk => clk,
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in_dat => stage_val,
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out_dat => out_val
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);
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end str;
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