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-- Author: Raj Thilak Rajan : rajan at astron.nl: Nov 2009
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-- Copyright (C) 2009-2010
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-- ASTRON (Netherlands Institute for Radio Astronomy)
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This file is part of the UniBoard software suite.
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-- The file is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--------------------------------------------------------------------------------
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library ieee, common_pkg_lib, common_components_lib, common_counter_lib, common_requantize_lib;
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use IEEE.std_logic_1164.all;
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use common_pkg_lib.common_pkg.all;
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use work.twiddlesPkg.all;
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use work.rTwoSDFPkg.all;
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entity rTwoSDFStage is
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generic (
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g_nof_chan : natural := 0; -- Exponent of nr of subbands (0 means 1 subband)
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g_stage : natural := 8;
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g_stage_offset : natural := 0; -- The Stage offset: 0 for normal FFT. Other than 0 in wideband FFT
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g_twiddle_offset : natural := 0; -- The twiddle offset: 0 for normal FFT. Other than 0 in wideband FFT
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g_scale_enable : boolean := TRUE; --
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g_pipeline : t_fft_pipeline := c_fft_pipeline -- internal pipeline settings
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);
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port (
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clk : in std_logic;
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rst : in std_logic;
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in_re : in std_logic_vector;
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in_im : in std_logic_vector;
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in_val : in std_logic;
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out_re : out std_logic_vector;
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out_im : out std_logic_vector;
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out_val : out std_logic
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);
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end entity rTwoSDFStage;
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architecture str of rTwoSDFStage is
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-- The amplification factor per stage is 2, therefor bit growth defintion of 1.
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-- Scale enable is defined by generic.
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constant c_rtwo_stage_bit_growth : natural := sel_a_b(g_scale_enable, 1, 0);
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-- counter for ctrl_sel
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constant c_cnt_lat : integer := 1;
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constant c_cnt_init : integer := 0;
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signal ctrl_sel : std_logic_vector(g_stage + g_nof_chan downto 1);
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signal in_sel : std_logic;
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signal bf_re : std_logic_vector(in_re'range);
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signal bf_im : std_logic_vector(in_im'range);
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signal bf_sel : std_logic;
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signal bf_val : std_logic;
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signal weight_addr : std_logic_vector(g_stage-1 downto 1);
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signal weight_re : wTyp;
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signal weight_im : wTyp;
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signal mul_out_re : std_logic_vector(out_re'range);
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signal mul_out_im : std_logic_vector(out_im'range);
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signal mul_out_val : std_logic;
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signal quant_out_re : std_logic_vector(out_re'range);
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signal quant_out_im : std_logic_vector(out_im'range);
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begin
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------------------------------------------------------------------------------
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-- stage counter
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------------------------------------------------------------------------------
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u_control : entity common_counter_lib.common_counter
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generic map (
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g_latency => c_cnt_lat,
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g_init => c_cnt_init,
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g_width => g_stage + g_nof_chan,
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g_step_size => 1
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)
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port map (
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rst => rst,
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clk => clk,
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cnt_en => in_val,
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count => ctrl_sel
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);
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------------------------------------------------------------------------------
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-- complex butterfly
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------------------------------------------------------------------------------
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in_sel <= ctrl_sel(g_stage + g_nof_chan);
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u_butterfly: entity work.rTwoBFStage
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generic map (
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g_nof_chan => g_nof_chan,
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g_stage => g_stage,
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g_bf_lat => g_pipeline.bf_lat,
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g_bf_use_zdly => g_pipeline.bf_use_zdly,
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g_bf_in_a_zdly => g_pipeline.bf_in_a_zdly,
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g_bf_out_d_zdly => g_pipeline.bf_out_d_zdly
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)
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port map (
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clk => clk,
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rst => rst,
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in_re => in_re,
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in_im => in_im,
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in_sel => in_sel,
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in_val => in_val,
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out_re => bf_re,
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out_im => bf_im,
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out_sel => bf_sel,
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out_val => bf_val
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);
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------------------------------------------------------------------------------
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-- get twiddles
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------------------------------------------------------------------------------
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weight_addr <= ctrl_sel(g_stage + g_nof_chan-1 downto g_nof_chan + 1);
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u_weights: entity work.rTwoWeights
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generic map (
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g_stage => g_stage,
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g_twiddle_offset => g_twiddle_offset,
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g_stage_offset => g_stage_offset,
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g_lat => g_pipeline.weight_lat
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)
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port map (
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clk => clk,
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in_wAdr => weight_addr,
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weight_re => weight_re,
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weight_im => weight_im
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);
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------------------------------------------------------------------------------
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-- twiddle multiplication
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------------------------------------------------------------------------------
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u_TwiddleMult: entity work.rTwoWMul
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generic map (
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g_stage => g_stage,
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g_lat => g_pipeline.mul_lat
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)
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port map (
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clk => clk,
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rst => rst,
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weight_re => weight_re,
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weight_im => weight_im,
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in_re => bf_re,
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in_im => bf_im,
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in_val => bf_val,
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in_sel => bf_sel,
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out_re => mul_out_re,
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out_im => mul_out_im,
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out_val => mul_out_val
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);
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------------------------------------------------------------------------------
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-- stage requantization
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------------------------------------------------------------------------------
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u_requantize_re : entity common_requantize_lib.common_requantize
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generic map (
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g_representation => "SIGNED",
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g_lsb_w => c_rtwo_stage_bit_growth,
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g_lsb_round => TRUE,
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g_lsb_round_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_msb => 0,
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g_in_dat_w => in_re'LENGTH,
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g_out_dat_w => out_re'LENGTH
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)
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port map (
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clk => clk,
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clken => '1',
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in_dat => mul_out_re,
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out_dat => quant_out_re,
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out_ovr => open
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);
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u_requantize_im : entity common_requantize_lib.common_requantize
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generic map (
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g_representation => "SIGNED",
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g_lsb_w => c_rtwo_stage_bit_growth,
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g_lsb_round => TRUE,
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g_lsb_round_clip => FALSE,
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g_msb_clip => FALSE,
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g_msb_clip_symmetric => FALSE,
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g_pipeline_remove_lsb => 0,
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g_pipeline_remove_msb => 0,
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g_in_dat_w => in_im'LENGTH,
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g_out_dat_w => out_im'LENGTH
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)
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port map (
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clk => clk,
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clken => '1',
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in_dat => mul_out_im,
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out_dat => quant_out_im,
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out_ovr => open
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);
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------------------------------------------------------------------------------
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-- output
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------------------------------------------------------------------------------
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u_re_lat : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => g_pipeline.stage_lat,
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g_in_dat_w => out_re'length,
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g_out_dat_w => out_re'length
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)
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port map (
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clk => clk,
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in_dat => quant_out_re,
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out_dat => out_re
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);
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u_im_lat : entity common_components_lib.common_pipeline
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generic map (
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g_pipeline => g_pipeline.stage_lat,
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g_in_dat_w => out_im'length,
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g_out_dat_w => out_im'length
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)
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port map (
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clk => clk,
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in_dat => quant_out_im,
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out_dat => out_im
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);
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u_val_lat : entity common_components_lib.common_pipeline_sl
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generic map (
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g_pipeline => g_pipeline.stage_lat
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)
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port map (
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clk => clk,
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in_dat => mul_out_val,
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out_dat => out_val
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);
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end str;
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