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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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-- Quartus Prime 18.0.0 Build 219 04/25/2018
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----------------------------------------------------------------------------
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-- ALtera Megafunction Component Declaration File
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----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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package altera_mf_components is
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type altera_mf_logic_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
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component lcell
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port (
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a_in : in std_logic;
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a_out : out std_logic);
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end component;
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component altclklock
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generic (
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inclock_period : natural := 10000; -- units in ps
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inclock_settings : string := "UNUSED";
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valid_lock_cycles : natural := 5;
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invalid_lock_cycles : natural := 5;
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valid_lock_multiplier : natural := 5;
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invalid_lock_multiplier : natural := 5;
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operation_mode : string := "NORMAL";
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clock0_boost : natural := 1;
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clock0_divide : natural := 1;
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clock0_settings : string := "UNUSED";
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clock0_time_delay : string := "0";
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clock1_boost : natural := 1;
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clock1_divide : natural := 1;
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clock1_settings : string := "UNUSED";
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clock1_time_delay : string := "0";
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clock2_boost : natural := 1;
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clock2_divide : natural := 1;
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clock2_settings : string := "UNUSED";
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clock2_time_delay : string := "0";
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clock_ext_boost : natural := 1;
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clock_ext_divide : natural := 1;
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clock_ext_settings : string := "UNUSED";
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clock_ext_time_delay : string := "0";
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outclock_phase_shift : natural := 0; -- units in ps
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intended_device_family : string := "Stratix" ;
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lpm_hint : string := "UNUSED";
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lpm_type : string := "altclklock" );
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port(
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inclock : in std_logic; -- required port, input reference clock
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inclocken : in std_logic := '1'; -- PLL enable signal
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fbin : in std_logic := '1'; -- feedback input for the PLL
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clock0 : out std_logic; -- clock0 output
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clock1 : out std_logic; -- clock1 output
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clock2 : out std_logic; -- clock2 output
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clock_ext : out std_logic; -- external clock output
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locked : out std_logic ); -- PLL lock signal
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end component;
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component altlvds_rx
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generic (
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number_of_channels : natural;
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deserialization_factor : natural;
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inclock_boost : natural:= 0;
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registered_output : string := "ON";
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inclock_period : natural;
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cds_mode : string := "UNUSED";
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intended_device_family : string := "Stratix";
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input_data_rate : natural:= 0;
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inclock_data_alignment : string := "UNUSED";
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registered_data_align_input : string :="ON";
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common_rx_tx_pll : string :="ON";
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enable_dpa_mode : string := "OFF";
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enable_dpa_pll_calibration : string := "OFF";
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enable_dpa_calibration : string := "ON";
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enable_dpa_fifo : string := "ON";
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use_dpll_rawperror : string := "OFF";
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use_coreclock_input : string := "OFF";
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dpll_lock_count : natural:= 0;
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dpll_lock_window : natural:= 0;
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outclock_resource : string := "AUTO";
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data_align_rollover : natural := 10;
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lose_lock_on_one_change : string := "OFF";
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reset_fifo_at_first_lock : string := "ON";
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use_external_pll : string := "OFF";
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implement_in_les : string := "OFF";
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buffer_implementation : string := "RAM";
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port_rx_data_align : string := "PORT_CONNECTIVITY";
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port_rx_channel_data_align : string := "PORT_CONNECTIVITY";
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pll_operation_mode : string := "NORMAL";
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x_on_bitslip : string := "ON";
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use_no_phase_shift : string := "ON";
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rx_align_data_reg : string := "RISING_EDGE";
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inclock_phase_shift : integer := 0;
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enable_soft_cdr_mode : string := "OFF";
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sim_dpa_output_clock_phase_shift : integer := 0;
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sim_dpa_is_negative_ppm_drift : string := "OFF";
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sim_dpa_net_ppm_variation : natural := 0;
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enable_dpa_align_to_rising_edge_only : string := "OFF";
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enable_dpa_initial_phase_selection : string := "OFF";
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dpa_initial_phase_value :natural := 0;
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pll_self_reset_on_loss_lock : string := "OFF";
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refclk_frequency : string := "UNUSED";
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enable_clock_pin_mode : string := "UNUSED";
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data_rate : string := "UNUSED";
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lpm_hint : string := "UNUSED";
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lpm_type : string := "altlvds_rx";
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clk_src_is_pll : string := "off" );
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port (
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rx_in : in std_logic_vector(number_of_channels-1 downto 0);
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rx_inclock : in std_logic := '0';
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rx_syncclock : in std_logic := '0';
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rx_dpaclock : in std_logic := '0';
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rx_readclock : in std_logic := '0';
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rx_enable : in std_logic := '1';
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rx_deskew : in std_logic := '0';
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rx_pll_enable : in std_logic := '1';
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rx_data_align : in std_logic := '0';
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rx_data_align_reset : in std_logic := '0';
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rx_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_dpll_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_dpll_hold : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_dpll_enable : in std_logic_vector(number_of_channels-1 downto 0) := (others => '1');
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rx_fifo_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_channel_data_align : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_cda_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_coreclk : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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pll_areset : in std_logic := '0';
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rx_data_reset : in std_logic := '0';
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dpa_pll_recal : in std_logic := '0';
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pll_phasedone : in std_logic := '1';
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rx_dpa_lock_reset : in std_logic_vector(number_of_channels-1 downto 0) := (others => '0');
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rx_out : out std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
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rx_outclock : out std_logic;
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rx_locked : out std_logic;
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rx_dpa_locked : out std_logic_vector(number_of_channels-1 downto 0);
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rx_cda_max : out std_logic_vector(number_of_channels-1 downto 0);
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rx_divfwdclk : out std_logic_vector(number_of_channels-1 downto 0);
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dpa_pll_cal_busy : out std_logic;
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pll_phasestep : out std_logic;
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pll_phaseupdown : out std_logic;
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pll_phasecounterselect: out std_logic_Vector(3 downto 0);
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pll_scanclk : out std_logic);
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end component;
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component altlvds_tx
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generic (
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number_of_channels : natural;
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deserialization_factor : natural:= 4;
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inclock_boost : natural := 0;
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outclock_divide_by : positive:= 1;
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registered_input : string := "ON";
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multi_clock : string := "OFF";
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inclock_period : natural;
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center_align_msb : string := "UNUSED";
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intended_device_family : string := "Stratix";
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output_data_rate : natural:= 0;
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outclock_resource : string := "AUTO";
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common_rx_tx_pll : string := "ON";
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inclock_data_alignment : string := "EDGE_ALIGNED";
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outclock_alignment : string := "EDGE_ALIGNED";
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use_external_pll : string := "OFF";
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implement_in_les : STRING := "OFF";
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preemphasis_setting : natural := 0;
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vod_setting : natural := 0;
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differential_drive : natural := 0;
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outclock_multiply_by : natural := 1;
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coreclock_divide_by : natural := 2;
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outclock_duty_cycle : natural := 50;
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inclock_phase_shift : integer := 0;
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outclock_phase_shift : integer := 0;
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use_no_phase_shift : string := "ON";
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pll_self_reset_on_loss_lock : string := "OFF";
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refclk_frequency : string := "UNUSED";
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enable_clock_pin_mode : string := "UNUSED";
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data_rate : string := "UNUSED";
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lpm_hint : string := "UNUSED";
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lpm_type : string := "altlvds_tx";
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clk_src_is_pll : string := "off" );
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port (
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tx_in : in std_logic_vector(deserialization_factor*number_of_channels -1 downto 0);
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tx_inclock : in std_logic := '0';
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tx_syncclock : in std_logic := '0';
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tx_enable : in std_logic := '1';
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sync_inclock : in std_logic := '0';
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tx_pll_enable : in std_logic := '1';
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pll_areset : in std_logic := '0';
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tx_data_reset : in std_logic := '0';
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tx_out : out std_logic_vector(number_of_channels-1 downto 0);
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tx_outclock : out std_logic;
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tx_coreclock : out std_logic;
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tx_locked : out std_logic );
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end component;
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component altdpram
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generic (
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width : natural;
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widthad : natural;
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numwords : natural := 0;
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lpm_file : string := "UNUSED";
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lpm_hint : string := "USE_EAB=ON";
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use_eab : string := "ON";
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indata_reg : string := "INCLOCK";
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indata_aclr : string := "ON";
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wraddress_reg : string := "INCLOCK";
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wraddress_aclr : string := "ON";
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wrcontrol_reg : string := "INCLOCK";
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wrcontrol_aclr : string := "ON";
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rdaddress_reg : string := "OUTCLOCK";
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rdaddress_aclr : string := "ON";
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rdcontrol_reg : string := "OUTCLOCK";
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rdcontrol_aclr : string := "ON";
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outdata_reg : string := "UNREGISTERED";
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outdata_aclr : string := "ON";
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outdata_Sclr : string := "ON";
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ram_block_type : string := "AUTO";
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width_byteena : natural := 1;
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byte_size : natural := 5;
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read_during_write_mode_mixed_ports : string := "DONT_CARE";
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maximum_depth : natural:= 2048;
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intended_device_family : string := "Stratix";
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lpm_type : string := "altdpram" );
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port(
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wren : in std_logic := '0';
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data : in std_logic_vector(width-1 downto 0);
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wraddress : in std_logic_vector(widthad-1 downto 0);
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wraddressstall : in std_logic := '0';
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inclock : in std_logic := '1';
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inclocken : in std_logic := '1';
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rden : in std_logic := '1';
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rdaddress : in std_logic_vector(widthad-1 downto 0);
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rdaddressstall : in std_logic := '0';
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byteena : in std_logic_vector(width_byteena-1 downto 0) := (others => '1');
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outclock : in std_logic := '1';
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outclocken : in std_logic := '1';
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aclr : in std_logic := '0';
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sclr : in std_logic := '0';
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q : out std_logic_vector(width-1 downto 0) );
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end component;
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component alt3pram
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generic (
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width : natural;
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widthad : natural;
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numwords : natural := 0;
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lpm_file : string := "UNUSED";
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lpm_hint : string := "USE_EAB=ON";
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indata_reg : string := "UNREGISTERED";
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indata_aclr : string := "OFF";
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write_reg : string := "UNREGISTERED";
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write_aclr : string := "OFF";
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rdaddress_reg_a : string := "UNREGISTERED";
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rdaddress_aclr_a : string := "OFF";
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rdaddress_reg_b : string := "UNREGISTERED";
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rdaddress_aclr_b : string := "OFF";
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rdcontrol_reg_a : string := "UNREGISTERED";
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rdcontrol_aclr_a : string := "OFF";
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rdcontrol_reg_b : string := "UNREGISTERED";
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rdcontrol_aclr_b : string := "OFF";
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outdata_reg_a : string := "UNREGISTERED";
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outdata_aclr_a : string := "OFF";
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outdata_reg_b : string := "UNREGISTERED";
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outdata_aclr_b : string := "OFF";
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intended_device_family : string := "Stratix";
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ram_block_type : string := "AUTO";
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maximum_depth : integer := 0;
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lpm_type : string := "alt3pram" );
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port (
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wren : in std_logic := '0';
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data : in std_logic_vector(width-1 downto 0);
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wraddress : in std_logic_vector(widthad-1 downto 0);
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inclock : in std_logic := '0';
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inclocken : in std_logic := '1';
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rden_a : in std_logic := '1';
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rden_b : in std_logic := '1';
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rdaddress_a : in std_logic_vector(widthad-1 downto 0);
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rdaddress_b : in std_logic_vector(widthad-1 downto 0);
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outclock : in std_logic := '0';
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outclocken : in std_logic := '1';
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aclr : in std_logic := '0';
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qa : out std_logic_vector(width-1 downto 0);
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qb : out std_logic_vector(width-1 downto 0) );
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end component;
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component scfifo
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generic (
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lpm_width : natural;
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lpm_widthu : natural;
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lpm_numwords : natural;
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lpm_showahead : string := "OFF";
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lpm_hint : string := "USE_EAB=ON";
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|
|
ram_block_type : string := "AUTO";
|
307 |
|
|
intended_device_family : string := "NON_STRATIX";
|
308 |
|
|
almost_full_value : natural := 0;
|
309 |
|
|
almost_empty_value : natural := 0;
|
310 |
|
|
overflow_checking : string := "ON";
|
311 |
|
|
underflow_checking : string := "ON";
|
312 |
|
|
allow_rwcycle_when_full : string := "OFF";
|
313 |
|
|
add_ram_output_register : string := "OFF";
|
314 |
|
|
use_eab : string := "ON";
|
315 |
|
|
lpm_type : string := "scfifo";
|
316 |
|
|
enable_ecc : string := "false";
|
317 |
|
|
maximum_depth : natural := 0 );
|
318 |
|
|
port (
|
319 |
|
|
data : in std_logic_vector(lpm_width-1 downto 0);
|
320 |
|
|
clock : in std_logic;
|
321 |
|
|
wrreq : in std_logic;
|
322 |
|
|
rdreq : in std_logic;
|
323 |
|
|
aclr : in std_logic := '0';
|
324 |
|
|
sclr : in std_logic := '0';
|
325 |
|
|
full : out std_logic;
|
326 |
|
|
almost_full : out std_logic;
|
327 |
|
|
empty : out std_logic;
|
328 |
|
|
almost_empty : out std_logic;
|
329 |
|
|
eccstatus : out std_logic_vector(1 downto 0);
|
330 |
|
|
q : out std_logic_vector(lpm_width-1 downto 0);
|
331 |
|
|
usedw : out std_logic_vector(lpm_widthu-1 downto 0) );
|
332 |
|
|
end component;
|
333 |
|
|
|
334 |
|
|
component dcfifo_mixed_widths
|
335 |
|
|
generic (
|
336 |
|
|
lpm_width : natural;
|
337 |
|
|
lpm_widthu : natural;
|
338 |
|
|
lpm_width_r : natural := 0;
|
339 |
|
|
lpm_widthu_r : natural := 0;
|
340 |
|
|
lpm_numwords : natural;
|
341 |
|
|
lpm_showahead : string := "OFF";
|
342 |
|
|
lpm_hint : string := "USE_EAB=ON";
|
343 |
|
|
overflow_checking : string := "ON";
|
344 |
|
|
underflow_checking : string := "ON";
|
345 |
|
|
delay_rdusedw : natural := 1;
|
346 |
|
|
delay_wrusedw : natural := 1;
|
347 |
|
|
rdsync_delaypipe : natural := 0;
|
348 |
|
|
wrsync_delaypipe : natural := 0;
|
349 |
|
|
use_eab : string := "ON";
|
350 |
|
|
add_ram_output_register : string := "OFF";
|
351 |
|
|
add_width : natural := 1;
|
352 |
|
|
clocks_are_synchronized : string := "FALSE";
|
353 |
|
|
ram_block_type : string := "AUTO";
|
354 |
|
|
add_usedw_msb_bit : string := "OFF";
|
355 |
|
|
read_aclr_synch : string := "OFF";
|
356 |
|
|
write_aclr_synch : string := "OFF";
|
357 |
|
|
lpm_type : string := "dcfifo_mixed_widths";
|
358 |
|
|
intended_device_family : string := "NON_STRATIX" );
|
359 |
|
|
port (
|
360 |
|
|
data : in std_logic_vector(lpm_width-1 downto 0);
|
361 |
|
|
rdclk : in std_logic;
|
362 |
|
|
wrclk : in std_logic;
|
363 |
|
|
wrreq : in std_logic;
|
364 |
|
|
rdreq : in std_logic;
|
365 |
|
|
aclr : in std_logic := '0';
|
366 |
|
|
rdfull : out std_logic;
|
367 |
|
|
wrfull : out std_logic;
|
368 |
|
|
wrempty : out std_logic;
|
369 |
|
|
rdempty : out std_logic;
|
370 |
|
|
q : out std_logic_vector(lpm_width_r-1 downto 0);
|
371 |
|
|
rdusedw : out std_logic_vector(lpm_widthu_r-1 downto 0);
|
372 |
|
|
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
|
373 |
|
|
end component;
|
374 |
|
|
|
375 |
|
|
component dcfifo
|
376 |
|
|
generic (
|
377 |
|
|
lpm_width : natural;
|
378 |
|
|
lpm_widthu : natural;
|
379 |
|
|
lpm_numwords : natural;
|
380 |
|
|
lpm_showahead : string := "OFF";
|
381 |
|
|
lpm_hint : string := "USE_EAB=ON";
|
382 |
|
|
overflow_checking : string := "ON";
|
383 |
|
|
underflow_checking : string := "ON";
|
384 |
|
|
delay_rdusedw : natural := 1;
|
385 |
|
|
delay_wrusedw : natural := 1;
|
386 |
|
|
rdsync_delaypipe : natural := 0;
|
387 |
|
|
wrsync_delaypipe : natural := 0;
|
388 |
|
|
use_eab : string := "ON";
|
389 |
|
|
add_ram_output_register : string := "OFF";
|
390 |
|
|
add_width : natural := 1;
|
391 |
|
|
clocks_are_synchronized : string := "FALSE";
|
392 |
|
|
ram_block_type : string := "AUTO";
|
393 |
|
|
add_usedw_msb_bit : string := "OFF";
|
394 |
|
|
read_aclr_synch : string := "OFF";
|
395 |
|
|
write_aclr_synch : string := "OFF";
|
396 |
|
|
lpm_type : string := "dcfifo";
|
397 |
|
|
enable_ecc : string := "false";
|
398 |
|
|
intended_device_family : string := "NON_STRATIX" );
|
399 |
|
|
port (
|
400 |
|
|
data : in std_logic_vector(lpm_width-1 downto 0);
|
401 |
|
|
rdclk : in std_logic;
|
402 |
|
|
wrclk : in std_logic;
|
403 |
|
|
wrreq : in std_logic;
|
404 |
|
|
rdreq : in std_logic;
|
405 |
|
|
aclr : in std_logic := '0';
|
406 |
|
|
rdfull : out std_logic;
|
407 |
|
|
wrfull : out std_logic;
|
408 |
|
|
wrempty : out std_logic;
|
409 |
|
|
rdempty : out std_logic;
|
410 |
|
|
eccstatus : out std_logic_vector(1 downto 0);
|
411 |
|
|
q : out std_logic_vector(lpm_width-1 downto 0);
|
412 |
|
|
rdusedw : out std_logic_vector(lpm_widthu-1 downto 0);
|
413 |
|
|
wrusedw : out std_logic_vector(lpm_widthu-1 downto 0) );
|
414 |
|
|
end component;
|
415 |
|
|
|
416 |
|
|
component altddio_in
|
417 |
|
|
generic (
|
418 |
|
|
width : positive; -- required parameter
|
419 |
|
|
invert_input_clocks : string := "OFF";
|
420 |
|
|
intended_device_family : string := "Stratix";
|
421 |
|
|
power_up_high : string := "OFF";
|
422 |
|
|
lpm_hint : string := "UNUSED";
|
423 |
|
|
lpm_type : string := "altddio_in" );
|
424 |
|
|
port (
|
425 |
|
|
datain : in std_logic_vector(width-1 downto 0);
|
426 |
|
|
inclock : in std_logic;
|
427 |
|
|
inclocken : in std_logic := '1';
|
428 |
|
|
aset : in std_logic := '0';
|
429 |
|
|
aclr : in std_logic := '0';
|
430 |
|
|
sset : in std_logic := '0';
|
431 |
|
|
sclr : in std_logic := '0';
|
432 |
|
|
dataout_h : out std_logic_vector(width-1 downto 0);
|
433 |
|
|
dataout_l : out std_logic_vector(width-1 downto 0) );
|
434 |
|
|
end component;
|
435 |
|
|
|
436 |
|
|
component altddio_out
|
437 |
|
|
generic (
|
438 |
|
|
width : positive; -- required parameter
|
439 |
|
|
power_up_high : string := "OFF";
|
440 |
|
|
oe_reg : string := "UNUSED";
|
441 |
|
|
extend_oe_disable : string := "UNUSED";
|
442 |
|
|
invert_output : string := "OFF";
|
443 |
|
|
intended_device_family : string := "Stratix";
|
444 |
|
|
lpm_hint : string := "UNUSED";
|
445 |
|
|
lpm_type : string := "altddio_out" );
|
446 |
|
|
port (
|
447 |
|
|
datain_h : in std_logic_vector(width-1 downto 0);
|
448 |
|
|
datain_l : in std_logic_vector(width-1 downto 0);
|
449 |
|
|
outclock : in std_logic;
|
450 |
|
|
outclocken : in std_logic := '1';
|
451 |
|
|
aset : in std_logic := '0';
|
452 |
|
|
aclr : in std_logic := '0';
|
453 |
|
|
sset : in std_logic := '0';
|
454 |
|
|
sclr : in std_logic := '0';
|
455 |
|
|
oe : in std_logic := '1';
|
456 |
|
|
dataout : out std_logic_vector(width-1 downto 0);
|
457 |
|
|
oe_out : out std_logic_vector(width-1 downto 0) );
|
458 |
|
|
end component;
|
459 |
|
|
|
460 |
|
|
component altddio_bidir
|
461 |
|
|
generic(
|
462 |
|
|
width : positive; -- required parameter
|
463 |
|
|
power_up_high : string := "OFF";
|
464 |
|
|
oe_reg : string := "UNUSED";
|
465 |
|
|
extend_oe_disable : string := "UNUSED";
|
466 |
|
|
implement_input_in_lcell : string := "UNUSED";
|
467 |
|
|
invert_output : string := "OFF";
|
468 |
|
|
intended_device_family : string := "Stratix";
|
469 |
|
|
lpm_hint : string := "UNUSED";
|
470 |
|
|
lpm_type : string := "altddio_bidir" );
|
471 |
|
|
port (
|
472 |
|
|
datain_h : in std_logic_vector(width-1 downto 0);
|
473 |
|
|
datain_l : in std_logic_vector(width-1 downto 0);
|
474 |
|
|
inclock : in std_logic := '0';
|
475 |
|
|
inclocken : in std_logic := '1';
|
476 |
|
|
outclock : in std_logic;
|
477 |
|
|
outclocken : in std_logic := '1';
|
478 |
|
|
aset : in std_logic := '0';
|
479 |
|
|
aclr : in std_logic := '0';
|
480 |
|
|
sset : in std_logic := '0';
|
481 |
|
|
sclr : in std_logic := '0';
|
482 |
|
|
oe : in std_logic := '1';
|
483 |
|
|
dataout_h : out std_logic_vector(width-1 downto 0);
|
484 |
|
|
dataout_l : out std_logic_vector(width-1 downto 0);
|
485 |
|
|
combout : out std_logic_vector(width-1 downto 0);
|
486 |
|
|
oe_out : out std_logic_vector(width-1 downto 0);
|
487 |
|
|
dqsundelayedout : out std_logic_vector(width-1 downto 0);
|
488 |
|
|
padio : inout std_logic_vector(width-1 downto 0) );
|
489 |
|
|
end component;
|
490 |
|
|
|
491 |
|
|
component altshift_taps
|
492 |
|
|
generic (
|
493 |
|
|
number_of_taps : integer := 4;
|
494 |
|
|
tap_distance : integer := 3;
|
495 |
|
|
width : integer := 8;
|
496 |
|
|
power_up_state : string := "CLEARED";
|
497 |
|
|
lpm_hint : string := "UNUSED";
|
498 |
|
|
lpm_type : string := "altshift_taps";
|
499 |
|
|
intended_device_family : string := "Stratix" );
|
500 |
|
|
port (
|
501 |
|
|
shiftin : in std_logic_vector (width-1 downto 0);
|
502 |
|
|
clock : in std_logic;
|
503 |
|
|
clken : in std_logic := '1';
|
504 |
|
|
aclr : in std_logic := '0';
|
505 |
|
|
sclr : in std_logic := '0';
|
506 |
|
|
shiftout : out std_logic_vector (width-1 downto 0);
|
507 |
|
|
taps : out std_logic_vector ((width*number_of_taps)-1 downto 0));
|
508 |
|
|
end component;
|
509 |
|
|
|
510 |
|
|
component altmult_add
|
511 |
|
|
generic (
|
512 |
|
|
WIDTH_A : integer := 1;
|
513 |
|
|
WIDTH_B : integer := 1;
|
514 |
|
|
WIDTH_RESULT : integer := 1;
|
515 |
|
|
NUMBER_OF_MULTIPLIERS : integer := 1;
|
516 |
|
|
|
517 |
|
|
-- A inputs
|
518 |
|
|
INPUT_REGISTER_A0 : string := "CLOCK0";
|
519 |
|
|
INPUT_ACLR_A0 : string := "ACLR3";
|
520 |
|
|
INPUT_SOURCE_A0 : string := "DATAA";
|
521 |
|
|
|
522 |
|
|
INPUT_REGISTER_A1 : string := "CLOCK0";
|
523 |
|
|
INPUT_ACLR_A1 : string := "ACLR3";
|
524 |
|
|
INPUT_SOURCE_A1 : string := "DATAA";
|
525 |
|
|
|
526 |
|
|
INPUT_REGISTER_A2 : string := "CLOCK0";
|
527 |
|
|
INPUT_ACLR_A2 : string := "ACLR3";
|
528 |
|
|
INPUT_SOURCE_A2 : string := "DATAA";
|
529 |
|
|
|
530 |
|
|
INPUT_REGISTER_A3 : string := "CLOCK0";
|
531 |
|
|
INPUT_ACLR_A3 : string := "ACLR3";
|
532 |
|
|
INPUT_SOURCE_A3 : string := "DATAA";
|
533 |
|
|
|
534 |
|
|
PORT_SIGNA : string := "PORT_CONNECTIVITY";
|
535 |
|
|
REPRESENTATION_A : string := "UNSIGNED";
|
536 |
|
|
SIGNED_REGISTER_A : string := "CLOCK0";
|
537 |
|
|
SIGNED_ACLR_A : string := "ACLR3";
|
538 |
|
|
SIGNED_PIPELINE_REGISTER_A : string := "CLOCK0";
|
539 |
|
|
SIGNED_PIPELINE_ACLR_A : string := "ACLR3";
|
540 |
|
|
|
541 |
|
|
-- B inputs
|
542 |
|
|
INPUT_REGISTER_B0 : string := "CLOCK0";
|
543 |
|
|
INPUT_ACLR_B0 : string := "ACLR3";
|
544 |
|
|
INPUT_SOURCE_B0 : string := "DATAB";
|
545 |
|
|
|
546 |
|
|
INPUT_REGISTER_B1 : string := "CLOCK0";
|
547 |
|
|
INPUT_ACLR_B1 : string := "ACLR3";
|
548 |
|
|
INPUT_SOURCE_B1 : string := "DATAB";
|
549 |
|
|
|
550 |
|
|
INPUT_REGISTER_B2 : string := "CLOCK0";
|
551 |
|
|
INPUT_ACLR_B2 : string := "ACLR3";
|
552 |
|
|
INPUT_SOURCE_B2 : string := "DATAB";
|
553 |
|
|
|
554 |
|
|
INPUT_REGISTER_B3 : string := "CLOCK0";
|
555 |
|
|
INPUT_ACLR_B3 : string := "ACLR3";
|
556 |
|
|
INPUT_SOURCE_B3 : string := "DATAB";
|
557 |
|
|
|
558 |
|
|
PORT_SIGNB : string := "PORT_CONNECTIVITY";
|
559 |
|
|
REPRESENTATION_B : string := "UNSIGNED";
|
560 |
|
|
SIGNED_REGISTER_B : string := "CLOCK0";
|
561 |
|
|
SIGNED_ACLR_B : string := "ACLR3";
|
562 |
|
|
SIGNED_PIPELINE_REGISTER_B : string := "CLOCK0";
|
563 |
|
|
SIGNED_PIPELINE_ACLR_B : string := "ACLR3";
|
564 |
|
|
|
565 |
|
|
MULTIPLIER_REGISTER0 : string := "CLOCK0";
|
566 |
|
|
MULTIPLIER_ACLR0 : string := "ACLR3";
|
567 |
|
|
MULTIPLIER_REGISTER1 : string := "CLOCK0";
|
568 |
|
|
MULTIPLIER_ACLR1 : string := "ACLR3";
|
569 |
|
|
MULTIPLIER_REGISTER2 : string := "CLOCK0";
|
570 |
|
|
MULTIPLIER_ACLR2 : string := "ACLR3";
|
571 |
|
|
MULTIPLIER_REGISTER3 : string := "CLOCK0";
|
572 |
|
|
MULTIPLIER_ACLR3 : string := "ACLR3";
|
573 |
|
|
|
574 |
|
|
PORT_ADDNSUB1 : string := "PORT_CONNECTIVITY";
|
575 |
|
|
ADDNSUB_MULTIPLIER_REGISTER1 : string := "CLOCK0";
|
576 |
|
|
ADDNSUB_MULTIPLIER_ACLR1 : string := "ACLR3";
|
577 |
|
|
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 : string := "CLOCK0";
|
578 |
|
|
ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 : string := "ACLR3";
|
579 |
|
|
|
580 |
|
|
PORT_ADDNSUB3 : string := "PORT_CONNECTIVITY";
|
581 |
|
|
ADDNSUB_MULTIPLIER_REGISTER3 : string := "CLOCK0";
|
582 |
|
|
ADDNSUB_MULTIPLIER_ACLR3 : string := "ACLR3";
|
583 |
|
|
ADDNSUB_MULTIPLIER_PIPELINE_REGISTER3: string := "CLOCK0";
|
584 |
|
|
ADDNSUB_MULTIPLIER_PIPELINE_ACLR3 : string := "ACLR3";
|
585 |
|
|
|
586 |
|
|
ADDNSUB1_ROUND_ACLR : string := "ACLR3";
|
587 |
|
|
ADDNSUB1_ROUND_PIPELINE_ACLR : string := "ACLR3";
|
588 |
|
|
ADDNSUB1_ROUND_REGISTER : string := "CLOCK0";
|
589 |
|
|
ADDNSUB1_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
|
590 |
|
|
ADDNSUB3_ROUND_ACLR : string := "ACLR3";
|
591 |
|
|
ADDNSUB3_ROUND_PIPELINE_ACLR : string := "ACLR3";
|
592 |
|
|
ADDNSUB3_ROUND_REGISTER : string := "CLOCK0";
|
593 |
|
|
ADDNSUB3_ROUND_PIPELINE_REGISTER : string := "CLOCK0";
|
594 |
|
|
|
595 |
|
|
MULT01_ROUND_ACLR : string := "ACLR3";
|
596 |
|
|
MULT01_ROUND_REGISTER : string := "CLOCK0";
|
597 |
|
|
MULT01_SATURATION_REGISTER : string := "CLOCK0";
|
598 |
|
|
MULT01_SATURATION_ACLR : string := "ACLR3";
|
599 |
|
|
MULT23_ROUND_REGISTER : string := "CLOCK0";
|
600 |
|
|
MULT23_ROUND_ACLR : string := "ACLR3";
|
601 |
|
|
MULT23_SATURATION_REGISTER : string := "CLOCK0";
|
602 |
|
|
MULT23_SATURATION_ACLR : string := "ACLR3";
|
603 |
|
|
|
604 |
|
|
multiplier1_direction : string := "ADD";
|
605 |
|
|
multiplier3_direction : string := "ADD";
|
606 |
|
|
|
607 |
|
|
OUTPUT_REGISTER : string := "CLOCK0";
|
608 |
|
|
OUTPUT_ACLR : string := "ACLR0";
|
609 |
|
|
|
610 |
|
|
-- StratixII parameters
|
611 |
|
|
multiplier01_rounding : string := "NO";
|
612 |
|
|
multiplier01_saturation : string := "NO";
|
613 |
|
|
multiplier23_rounding : string := "NO";
|
614 |
|
|
multiplier23_saturation : string := "NO";
|
615 |
|
|
adder1_rounding : string := "NO";
|
616 |
|
|
adder3_rounding : string := "NO";
|
617 |
|
|
port_mult0_is_saturated : string := "UNUSED";
|
618 |
|
|
port_mult1_is_saturated : string := "UNUSED";
|
619 |
|
|
port_mult2_is_saturated : string := "UNUSED";
|
620 |
|
|
port_mult3_is_saturated : string := "UNUSED";
|
621 |
|
|
|
622 |
|
|
-- Stratix III parameters
|
623 |
|
|
scanouta_register : string := "UNREGISTERED";
|
624 |
|
|
scanouta_aclr : string := "NONE";
|
625 |
|
|
|
626 |
|
|
-- Rounding parameters
|
627 |
|
|
output_rounding : string := "NO";
|
628 |
|
|
output_round_type : string := "NEAREST_INTEGER";
|
629 |
|
|
width_msb : integer := 17;
|
630 |
|
|
output_round_register : string := "UNREGISTERED";
|
631 |
|
|
output_round_aclr : string := "NONE";
|
632 |
|
|
output_round_pipeline_register : string := "UNREGISTERED";
|
633 |
|
|
output_round_pipeline_aclr : string := "NONE";
|
634 |
|
|
|
635 |
|
|
chainout_rounding : string := "NO";
|
636 |
|
|
chainout_round_register : string := "UNREGISTERED";
|
637 |
|
|
chainout_round_aclr : string := "NONE";
|
638 |
|
|
chainout_round_pipeline_register : string := "UNREGISTERED";
|
639 |
|
|
chainout_round_pipeline_aclr : string := "NONE";
|
640 |
|
|
chainout_round_output_register : string := "UNREGISTERED";
|
641 |
|
|
chainout_round_output_aclr : string := "NONE";
|
642 |
|
|
|
643 |
|
|
-- saturation parameters
|
644 |
|
|
port_output_is_overflow : string := "PORT_UNUSED";
|
645 |
|
|
port_chainout_sat_is_overflow : string := "PORT_UNUSED";
|
646 |
|
|
output_saturation : string := "NO";
|
647 |
|
|
output_saturate_type : string := "ASYMMETRIC";
|
648 |
|
|
width_saturate_sign : integer := 1;
|
649 |
|
|
output_saturate_register : string := "UNREGISTERED";
|
650 |
|
|
output_saturate_aclr : string := "NONE";
|
651 |
|
|
output_saturate_pipeline_register : string := "UNREGISTERED";
|
652 |
|
|
output_saturate_pipeline_aclr : string := "NONE";
|
653 |
|
|
|
654 |
|
|
chainout_saturation : string := "NO";
|
655 |
|
|
chainout_saturate_register : string := "UNREGISTERED";
|
656 |
|
|
chainout_saturate_aclr : string := "NONE";
|
657 |
|
|
chainout_saturate_pipeline_register : string := "UNREGISTERED";
|
658 |
|
|
chainout_saturate_pipeline_aclr : string := "NONE";
|
659 |
|
|
chainout_saturate_output_register : string := "UNREGISTERED";
|
660 |
|
|
chainout_saturate_output_aclr : string := "NONE";
|
661 |
|
|
|
662 |
|
|
-- chainout parameters
|
663 |
|
|
chainout_adder : string := "NO";
|
664 |
|
|
chainout_register : string := "UNREGISTERED";
|
665 |
|
|
chainout_aclr : string := "NONE";
|
666 |
|
|
width_chainin : integer := 1;
|
667 |
|
|
zero_chainout_output_register : string := "UNREGISTERED";
|
668 |
|
|
zero_chainout_output_aclr : string := "NONE";
|
669 |
|
|
|
670 |
|
|
-- rotate & shift parameters
|
671 |
|
|
shift_mode : string := "NO";
|
672 |
|
|
rotate_aclr : string := "NONE";
|
673 |
|
|
rotate_register : string := "UNREGISTERED";
|
674 |
|
|
rotate_pipeline_register : string := "UNREGISTERED";
|
675 |
|
|
rotate_pipeline_aclr : string := "NONE";
|
676 |
|
|
rotate_output_register : string := "UNREGISTERED";
|
677 |
|
|
rotate_output_aclr : string := "NONE";
|
678 |
|
|
shift_right_register : string := "UNREGISTERED";
|
679 |
|
|
shift_right_aclr : string := "NONE";
|
680 |
|
|
shift_right_pipeline_register : string := "UNREGISTERED";
|
681 |
|
|
shift_right_pipeline_aclr : string := "NONE";
|
682 |
|
|
shift_right_output_register : string := "UNREGISTERED";
|
683 |
|
|
shift_right_output_aclr : string := "NONE";
|
684 |
|
|
|
685 |
|
|
-- loopback parameters
|
686 |
|
|
zero_loopback_register : string := "UNREGISTERED";
|
687 |
|
|
zero_loopback_aclr : string := "NONE";
|
688 |
|
|
zero_loopback_pipeline_register : string := "UNREGISTERED";
|
689 |
|
|
zero_loopback_pipeline_aclr : string := "NONE";
|
690 |
|
|
zero_loopback_output_register : string := "UNREGISTERED";
|
691 |
|
|
zero_loopback_output_aclr : string := "NONE";
|
692 |
|
|
|
693 |
|
|
-- accumulator parameters
|
694 |
|
|
accum_sload_register : string := "UNREGISTERED";
|
695 |
|
|
accum_sload_aclr : string := "NONE";
|
696 |
|
|
accum_sload_pipeline_register : string := "UNREGISTERED";
|
697 |
|
|
accum_sload_pipeline_aclr : string := "NONE";
|
698 |
|
|
accum_direction : string := "ADD";
|
699 |
|
|
accumulator : string := "NO";
|
700 |
|
|
|
701 |
|
|
-- Stratix V parameters
|
702 |
|
|
width_c : integer := 22;
|
703 |
|
|
loadconst_value : integer := 64;
|
704 |
|
|
preadder_mode : string := "SIMPLE";
|
705 |
|
|
preadder_direction_0 : string := "ADD";
|
706 |
|
|
preadder_direction_1 : string := "ADD";
|
707 |
|
|
preadder_direction_2 : string := "ADD";
|
708 |
|
|
preadder_direction_3 : string := "ADD";
|
709 |
|
|
input_register_c0 : string := "CLOCK0";
|
710 |
|
|
input_aclr_c0 : string := "ACLR0";
|
711 |
|
|
coefsel0_register : string := "CLOCK0";
|
712 |
|
|
coefsel1_register : string := "CLOCK0";
|
713 |
|
|
coefsel2_register : string := "CLOCK0";
|
714 |
|
|
coefsel3_register : string := "CLOCK0";
|
715 |
|
|
coefsel0_aclr : string := "ACLR0";
|
716 |
|
|
coefsel1_aclr : string := "ACLR0";
|
717 |
|
|
coefsel2_aclr : string := "ACLR0";
|
718 |
|
|
coefsel3_aclr : string := "ACLR0";
|
719 |
|
|
systolic_delay1 : string := "UNREGISTERED";
|
720 |
|
|
systolic_delay3 : string := "UNREGISTERED";
|
721 |
|
|
systolic_aclr1 : string := "NONE";
|
722 |
|
|
systolic_aclr3 : string := "NONE";
|
723 |
|
|
coef0_0 : integer := 0;
|
724 |
|
|
coef0_1 : integer := 0;
|
725 |
|
|
coef0_2 : integer := 0;
|
726 |
|
|
coef0_3 : integer := 0;
|
727 |
|
|
coef0_4 : integer := 0;
|
728 |
|
|
coef0_5 : integer := 0;
|
729 |
|
|
coef0_6 : integer := 0;
|
730 |
|
|
coef0_7 : integer := 0;
|
731 |
|
|
coef1_0 : integer := 0;
|
732 |
|
|
coef1_1 : integer := 0;
|
733 |
|
|
coef1_2 : integer := 0;
|
734 |
|
|
coef1_3 : integer := 0;
|
735 |
|
|
coef1_4 : integer := 0;
|
736 |
|
|
coef1_5 : integer := 0;
|
737 |
|
|
coef1_6 : integer := 0;
|
738 |
|
|
coef1_7 : integer := 0;
|
739 |
|
|
coef2_0 : integer := 0;
|
740 |
|
|
coef2_1 : integer := 0;
|
741 |
|
|
coef2_2 : integer := 0;
|
742 |
|
|
coef2_3 : integer := 0;
|
743 |
|
|
coef2_4 : integer := 0;
|
744 |
|
|
coef2_5 : integer := 0;
|
745 |
|
|
coef2_6 : integer := 0;
|
746 |
|
|
coef2_7 : integer := 0;
|
747 |
|
|
coef3_0 : integer := 0;
|
748 |
|
|
coef3_1 : integer := 0;
|
749 |
|
|
coef3_2 : integer := 0;
|
750 |
|
|
coef3_3 : integer := 0;
|
751 |
|
|
coef3_4 : integer := 0;
|
752 |
|
|
coef3_5 : integer := 0;
|
753 |
|
|
coef3_6 : integer := 0;
|
754 |
|
|
coef3_7 : integer := 0;
|
755 |
|
|
width_coef : integer := 18;
|
756 |
|
|
|
757 |
|
|
EXTRA_LATENCY : integer :=0;
|
758 |
|
|
DEDICATED_MULTIPLIER_CIRCUITRY:string := "AUTO";
|
759 |
|
|
DSP_BLOCK_BALANCING : string := "AUTO";
|
760 |
|
|
lpm_hint : string := "UNUSED";
|
761 |
|
|
lpm_type : string := "altmult_add";
|
762 |
|
|
intended_device_family : string := "Stratix" );
|
763 |
|
|
port (
|
764 |
|
|
dataa : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_A -1 downto 0);
|
765 |
|
|
datab : in std_logic_vector(NUMBER_OF_MULTIPLIERS * WIDTH_B -1 downto 0);
|
766 |
|
|
|
767 |
|
|
scanina : in std_logic_vector(width_a -1 downto 0) := (others => '0');
|
768 |
|
|
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => '0');
|
769 |
|
|
|
770 |
|
|
sourcea : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
|
771 |
|
|
sourceb : in std_logic_vector(NUMBER_OF_MULTIPLIERS -1 downto 0) := (others => '0');
|
772 |
|
|
|
773 |
|
|
|
774 |
|
|
-- clock ports
|
775 |
|
|
clock3 : in std_logic := '1';
|
776 |
|
|
clock2 : in std_logic := '1';
|
777 |
|
|
clock1 : in std_logic := '1';
|
778 |
|
|
clock0 : in std_logic := '1';
|
779 |
|
|
aclr3 : in std_logic := '0';
|
780 |
|
|
aclr2 : in std_logic := '0';
|
781 |
|
|
aclr1 : in std_logic := '0';
|
782 |
|
|
aclr0 : in std_logic := '0';
|
783 |
|
|
ena3 : in std_logic := '1';
|
784 |
|
|
ena2 : in std_logic := '1';
|
785 |
|
|
ena1 : in std_logic := '1';
|
786 |
|
|
ena0 : in std_logic := '1';
|
787 |
|
|
|
788 |
|
|
-- control signals
|
789 |
|
|
signa : in std_logic := 'Z';
|
790 |
|
|
signb : in std_logic := 'Z';
|
791 |
|
|
addnsub1 : in std_logic := 'Z';
|
792 |
|
|
addnsub3 : in std_logic := 'Z';
|
793 |
|
|
|
794 |
|
|
-- StratixII only input ports
|
795 |
|
|
mult01_round : in std_logic := '0';
|
796 |
|
|
mult23_round : in std_logic := '0';
|
797 |
|
|
mult01_saturation : in std_logic := '0';
|
798 |
|
|
mult23_saturation : in std_logic := '0';
|
799 |
|
|
addnsub1_round : in std_logic := '0';
|
800 |
|
|
addnsub3_round : in std_logic := '0';
|
801 |
|
|
|
802 |
|
|
-- Stratix III only input ports
|
803 |
|
|
output_round : in std_logic := '0';
|
804 |
|
|
chainout_round : in std_logic := '0';
|
805 |
|
|
output_saturate : in std_logic := '0';
|
806 |
|
|
chainout_saturate : in std_logic := '0';
|
807 |
|
|
chainin : in std_logic_vector (width_chainin - 1 downto 0) := (others => '0');
|
808 |
|
|
zero_chainout : in std_logic := '0';
|
809 |
|
|
rotate : in std_logic := '0';
|
810 |
|
|
shift_right : in std_logic := '0';
|
811 |
|
|
zero_loopback : in std_logic := '0';
|
812 |
|
|
accum_sload : in std_logic := '0';
|
813 |
|
|
|
814 |
|
|
-- Stratix V only input ports
|
815 |
|
|
coefsel0 : in std_logic_vector (2 downto 0) := (others => '0');
|
816 |
|
|
coefsel1 : in std_logic_vector (2 downto 0) := (others => '0');
|
817 |
|
|
coefsel2 : in std_logic_vector (2 downto 0) := (others => '0');
|
818 |
|
|
coefsel3 : in std_logic_vector (2 downto 0) := (others => '0');
|
819 |
|
|
datac : in std_logic_vector (NUMBER_OF_MULTIPLIERS * width_c -1 downto 0) := (others => '0');
|
820 |
|
|
|
821 |
|
|
-- output ports
|
822 |
|
|
result : out std_logic_vector(WIDTH_RESULT -1 downto 0);
|
823 |
|
|
scanouta : out std_logic_vector (WIDTH_A -1 downto 0);
|
824 |
|
|
scanoutb : out std_logic_vector (WIDTH_B -1 downto 0);
|
825 |
|
|
|
826 |
|
|
-- StratixII only output ports
|
827 |
|
|
mult0_is_saturated : out std_logic := '0';
|
828 |
|
|
mult1_is_saturated : out std_logic := '0';
|
829 |
|
|
mult2_is_saturated : out std_logic := '0';
|
830 |
|
|
mult3_is_saturated : out std_logic := '0';
|
831 |
|
|
|
832 |
|
|
-- Stratix III only output ports
|
833 |
|
|
overflow : out std_logic := '0';
|
834 |
|
|
chainout_sat_overflow : out std_logic := '0');
|
835 |
|
|
end component;
|
836 |
|
|
|
837 |
|
|
component altmult_accum
|
838 |
|
|
generic (
|
839 |
|
|
width_a : integer := 1;
|
840 |
|
|
width_b : integer := 1;
|
841 |
|
|
width_c : natural := 1;
|
842 |
|
|
width_result : integer := 2;
|
843 |
|
|
width_upper_data : integer := 1;
|
844 |
|
|
input_source_a : string := "DATAA";
|
845 |
|
|
input_source_b : string := "DATAB";
|
846 |
|
|
input_reg_a : string := "CLOCK0";
|
847 |
|
|
input_aclr_a : string := "ACLR3";
|
848 |
|
|
input_reg_b : string := "CLOCK0";
|
849 |
|
|
input_aclr_b : string := "ACLR3";
|
850 |
|
|
port_addnsub : string := "PORT_CONNECTIVITY";
|
851 |
|
|
addnsub_reg : string := "CLOCK0";
|
852 |
|
|
addnsub_aclr : string := "ACLR3";
|
853 |
|
|
addnsub_pipeline_reg : string := "CLOCK0";
|
854 |
|
|
addnsub_pipeline_aclr : string := "ACLR3";
|
855 |
|
|
accum_direction : string := "ADD";
|
856 |
|
|
accum_sload_reg : string := "CLOCK0";
|
857 |
|
|
accum_sload_aclr : string := "ACLR3";
|
858 |
|
|
accum_sload_pipeline_reg : string := "CLOCK0";
|
859 |
|
|
accum_sload_pipeline_aclr : string := "ACLR3";
|
860 |
|
|
representation_a : string := "UNSIGNED";
|
861 |
|
|
port_signa : string := "PORT_CONNECTIVITY";
|
862 |
|
|
sign_reg_a : string := "CLOCK0";
|
863 |
|
|
sign_aclr_a : string := "ACLR3";
|
864 |
|
|
sign_pipeline_reg_a : string := "CLOCK0";
|
865 |
|
|
sign_pipeline_aclr_a : string := "ACLR3";
|
866 |
|
|
representation_b : string := "UNSIGNED";
|
867 |
|
|
port_signb : string := "PORT_CONNECTIVITY";
|
868 |
|
|
sign_reg_b : string := "CLOCK0";
|
869 |
|
|
sign_aclr_b : string := "ACLR3";
|
870 |
|
|
sign_pipeline_reg_b : string := "CLOCK0";
|
871 |
|
|
sign_pipeline_aclr_b : string := "ACLR3";
|
872 |
|
|
multiplier_reg : string := "CLOCK0";
|
873 |
|
|
multiplier_aclr : string := "ACLR3";
|
874 |
|
|
output_reg : string := "CLOCK0";
|
875 |
|
|
output_aclr : string := "ACLR0";
|
876 |
|
|
extra_multiplier_latency : integer := 0;
|
877 |
|
|
extra_accumulator_latency : integer := 0;
|
878 |
|
|
dedicated_multiplier_circuitry : string := "AUTO";
|
879 |
|
|
dsp_block_balancing : string := "AUTO";
|
880 |
|
|
lpm_hint : string := "UNUSED";
|
881 |
|
|
lpm_type : string := "altmult_accum";
|
882 |
|
|
intended_device_family : string := "Stratix";
|
883 |
|
|
multiplier_rounding : string := "NO";
|
884 |
|
|
multiplier_saturation : string := "NO";
|
885 |
|
|
accumulator_rounding : string := "NO";
|
886 |
|
|
accumulator_saturation : string := "NO";
|
887 |
|
|
port_mult_is_saturated : string := "UNUSED";
|
888 |
|
|
port_accum_is_saturated : string := "UNUSED";
|
889 |
|
|
mult_round_aclr : string := "ACLR3";
|
890 |
|
|
mult_round_reg : string := "CLOCK0";
|
891 |
|
|
mult_saturation_aclr : string := "ACLR3";
|
892 |
|
|
mult_saturation_reg : string := "CLOCK0";
|
893 |
|
|
accum_round_aclr : string := "ACLR3";
|
894 |
|
|
accum_round_reg : string := "CLOCK3";
|
895 |
|
|
accum_round_pipeline_aclr : string := "ACLR3";
|
896 |
|
|
accum_round_pipeline_reg : string := "CLOCK0";
|
897 |
|
|
accum_saturation_aclr : string := "ACLR3";
|
898 |
|
|
accum_saturation_reg : string := "CLOCK0";
|
899 |
|
|
accum_saturation_pipeline_aclr : string := "ACLR3";
|
900 |
|
|
accum_saturation_pipeline_reg : string := "CLOCK0";
|
901 |
|
|
accum_sload_upper_data_aclr : string := "ACLR3";
|
902 |
|
|
accum_sload_upper_data_pipeline_aclr : string := "ACLR3";
|
903 |
|
|
accum_sload_upper_data_pipeline_reg : string := "CLOCK0";
|
904 |
|
|
accum_sload_upper_data_reg : string := "CLOCK0";
|
905 |
|
|
-- StratixV parameters
|
906 |
|
|
preadder_mode : string := "SIMPLE";
|
907 |
|
|
loadconst_value : integer := 0;
|
908 |
|
|
width_coef : integer := 0;
|
909 |
|
|
|
910 |
|
|
loadconst_control_register : string := "CLOCK0";
|
911 |
|
|
loadconst_control_aclr : string := "ACLR0";
|
912 |
|
|
|
913 |
|
|
coefsel0_register : string := "CLOCK0";
|
914 |
|
|
coefsel1_register : string := "CLOCK0";
|
915 |
|
|
coefsel2_register : string := "CLOCK0";
|
916 |
|
|
coefsel3_register : string := "CLOCK0";
|
917 |
|
|
coefsel0_aclr : string := "ACLR0";
|
918 |
|
|
coefsel1_aclr : string := "ACLR0";
|
919 |
|
|
coefsel2_aclr : string := "ACLR0";
|
920 |
|
|
coefsel3_aclr : string := "ACLR0";
|
921 |
|
|
|
922 |
|
|
preadder_direction_0 : string := "ADD";
|
923 |
|
|
preadder_direction_1 : string := "ADD";
|
924 |
|
|
preadder_direction_2 : string := "ADD";
|
925 |
|
|
preadder_direction_3 : string := "ADD";
|
926 |
|
|
|
927 |
|
|
systolic_delay1 : string := "UNREGISTERED";
|
928 |
|
|
systolic_delay3 : string := "UNREGISTERED";
|
929 |
|
|
systolic_aclr1 : string := "NONE";
|
930 |
|
|
systolic_aclr3 : string := "NONE";
|
931 |
|
|
-- coefficient storage
|
932 |
|
|
coef0_0 : integer := 0;
|
933 |
|
|
coef0_1 : integer := 0;
|
934 |
|
|
coef0_2 : integer := 0;
|
935 |
|
|
coef0_3 : integer := 0;
|
936 |
|
|
coef0_4 : integer := 0;
|
937 |
|
|
coef0_5 : integer := 0;
|
938 |
|
|
coef0_6 : integer := 0;
|
939 |
|
|
coef0_7 : integer := 0;
|
940 |
|
|
|
941 |
|
|
coef1_0 : integer := 0;
|
942 |
|
|
coef1_1 : integer := 0;
|
943 |
|
|
coef1_2 : integer := 0;
|
944 |
|
|
coef1_3 : integer := 0;
|
945 |
|
|
coef1_4 : integer := 0;
|
946 |
|
|
coef1_5 : integer := 0;
|
947 |
|
|
coef1_6 : integer := 0;
|
948 |
|
|
coef1_7 : integer := 0;
|
949 |
|
|
|
950 |
|
|
coef2_0 : integer := 0;
|
951 |
|
|
coef2_1 : integer := 0;
|
952 |
|
|
coef2_2 : integer := 0;
|
953 |
|
|
coef2_3 : integer := 0;
|
954 |
|
|
coef2_4 : integer := 0;
|
955 |
|
|
coef2_5 : integer := 0;
|
956 |
|
|
coef2_6 : integer := 0;
|
957 |
|
|
coef2_7 : integer := 0;
|
958 |
|
|
|
959 |
|
|
coef3_0 : integer := 0;
|
960 |
|
|
coef3_1 : integer := 0;
|
961 |
|
|
coef3_2 : integer := 0;
|
962 |
|
|
coef3_3 : integer := 0;
|
963 |
|
|
coef3_4 : integer := 0;
|
964 |
|
|
coef3_5 : integer := 0;
|
965 |
|
|
coef3_6 : integer := 0;
|
966 |
|
|
coef3_7 : integer := 0 );
|
967 |
|
|
|
968 |
|
|
port (
|
969 |
|
|
dataa : in std_logic_vector(width_a -1 downto 0) := (others => '0');
|
970 |
|
|
datab : in std_logic_vector(width_b -1 downto 0) := (others => '0');
|
971 |
|
|
scanina : in std_logic_vector(width_a -1 downto 0) := (others => 'Z');
|
972 |
|
|
scaninb : in std_logic_vector(width_b -1 downto 0) := (others => 'Z');
|
973 |
|
|
accum_sload_upper_data : in std_logic_vector(width_result -1 downto width_result - width_upper_data) := (others => '0');
|
974 |
|
|
sourcea : in std_logic := '1';
|
975 |
|
|
sourceb : in std_logic := '1';
|
976 |
|
|
-- control signals
|
977 |
|
|
addnsub : in std_logic := 'Z';
|
978 |
|
|
accum_sload : in std_logic := '0';
|
979 |
|
|
signa : in std_logic := 'Z';
|
980 |
|
|
signb : in std_logic := 'Z';
|
981 |
|
|
-- clock ports
|
982 |
|
|
clock0 : in std_logic := '1';
|
983 |
|
|
clock1 : in std_logic := '1';
|
984 |
|
|
clock2 : in std_logic := '1';
|
985 |
|
|
clock3 : in std_logic := '1';
|
986 |
|
|
ena0 : in std_logic := '1';
|
987 |
|
|
ena1 : in std_logic := '1';
|
988 |
|
|
ena2 : in std_logic := '1';
|
989 |
|
|
ena3 : in std_logic := '1';
|
990 |
|
|
aclr0 : in std_logic := '0';
|
991 |
|
|
aclr1 : in std_logic := '0';
|
992 |
|
|
aclr2 : in std_logic := '0';
|
993 |
|
|
aclr3 : in std_logic := '0';
|
994 |
|
|
-- round and saturation ports
|
995 |
|
|
mult_round : in std_logic := '0';
|
996 |
|
|
mult_saturation : in std_logic := '0';
|
997 |
|
|
accum_round : in std_logic := '0';
|
998 |
|
|
accum_saturation : in std_logic := '0';
|
999 |
|
|
-- StratixV only input ports
|
1000 |
|
|
coefsel0 : in std_logic_vector(2 downto 0) := (others => '0');
|
1001 |
|
|
coefsel1 : in std_logic_vector(2 downto 0) := (others => '0');
|
1002 |
|
|
coefsel2 : in std_logic_vector(2 downto 0) := (others => '0');
|
1003 |
|
|
coefsel3 : in std_logic_vector(2 downto 0) := (others => '0');
|
1004 |
|
|
-- output ports
|
1005 |
|
|
result : out std_logic_vector(width_result -1 downto 0);
|
1006 |
|
|
overflow : out std_logic;
|
1007 |
|
|
scanouta : out std_logic_vector (width_a -1 downto 0);
|
1008 |
|
|
scanoutb : out std_logic_vector (width_b -1 downto 0);
|
1009 |
|
|
mult_is_saturated : out std_logic := '0';
|
1010 |
|
|
accum_is_saturated : out std_logic := '0' );
|
1011 |
|
|
end component;
|
1012 |
|
|
|
1013 |
|
|
component altaccumulate
|
1014 |
|
|
generic (
|
1015 |
|
|
width_in : integer:= 4;
|
1016 |
|
|
width_out : integer:= 8;
|
1017 |
|
|
lpm_representation : string := "UNSIGNED";
|
1018 |
|
|
extra_latency : integer:= 0;
|
1019 |
|
|
use_wys : string := "ON";
|
1020 |
|
|
lpm_hint : string := "UNUSED";
|
1021 |
|
|
lpm_type : string := "altaccumulate" );
|
1022 |
|
|
|
1023 |
|
|
port (
|
1024 |
|
|
-- Input ports
|
1025 |
|
|
cin : in std_logic := 'Z';
|
1026 |
|
|
data : in std_logic_vector(width_in -1 downto 0); -- Required port
|
1027 |
|
|
add_sub : in std_logic := '1';
|
1028 |
|
|
clock : in std_logic; -- Required port
|
1029 |
|
|
sload : in std_logic := '0';
|
1030 |
|
|
clken : in std_logic := '1';
|
1031 |
|
|
sign_data : in std_logic := '0';
|
1032 |
|
|
aclr : in std_logic := '0';
|
1033 |
|
|
|
1034 |
|
|
-- Output ports
|
1035 |
|
|
result : out std_logic_vector(width_out -1 downto 0) := (others => '0');
|
1036 |
|
|
cout : out std_logic := '0';
|
1037 |
|
|
overflow : out std_logic := '0' );
|
1038 |
|
|
end component;
|
1039 |
|
|
|
1040 |
|
|
component altsyncram
|
1041 |
|
|
generic (
|
1042 |
|
|
operation_mode : string := "BIDIR_DUAL_PORT";
|
1043 |
|
|
-- port a parameters
|
1044 |
|
|
width_a : integer := 1;
|
1045 |
|
|
widthad_a : integer := 1;
|
1046 |
|
|
numwords_a : integer := 0;
|
1047 |
|
|
-- registering parameters
|
1048 |
|
|
-- port a read parameters
|
1049 |
|
|
outdata_reg_a : string := "UNREGISTERED";
|
1050 |
|
|
-- clearing parameters
|
1051 |
|
|
address_aclr_a : string := "NONE";
|
1052 |
|
|
outdata_aclr_a : string := "NONE";
|
1053 |
|
|
-- clearing parameters
|
1054 |
|
|
-- port a write parameters
|
1055 |
|
|
indata_aclr_a : string := "NONE";
|
1056 |
|
|
wrcontrol_aclr_a : string := "NONE";
|
1057 |
|
|
-- clear for the byte enable port reigsters which are clocked by clk0
|
1058 |
|
|
byteena_aclr_a : string := "NONE";
|
1059 |
|
|
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
|
1060 |
|
|
width_byteena_a : integer := 1;
|
1061 |
|
|
-- port b parameters
|
1062 |
|
|
width_b : integer := 1;
|
1063 |
|
|
widthad_b : integer := 1;
|
1064 |
|
|
numwords_b : integer := 0;
|
1065 |
|
|
-- registering parameters
|
1066 |
|
|
-- port b read parameters
|
1067 |
|
|
rdcontrol_reg_b : string := "CLOCK1";
|
1068 |
|
|
address_reg_b : string := "CLOCK1";
|
1069 |
|
|
outdata_reg_b : string := "UNREGISTERED";
|
1070 |
|
|
-- clearing parameters
|
1071 |
|
|
outdata_aclr_b : string := "NONE";
|
1072 |
|
|
rdcontrol_aclr_b : string := "NONE";
|
1073 |
|
|
-- registering parameters
|
1074 |
|
|
-- port b write parameters
|
1075 |
|
|
indata_reg_b : string := "CLOCK1";
|
1076 |
|
|
wrcontrol_wraddress_reg_b : string := "CLOCK1";
|
1077 |
|
|
-- registering parameter for the byte enable reister for port b
|
1078 |
|
|
byteena_reg_b : string := "CLOCK1";
|
1079 |
|
|
-- clearing parameters
|
1080 |
|
|
indata_aclr_b : string := "NONE";
|
1081 |
|
|
wrcontrol_aclr_b : string := "NONE";
|
1082 |
|
|
address_aclr_b : string := "NONE";
|
1083 |
|
|
-- clear parameter for byte enable port register
|
1084 |
|
|
byteena_aclr_b : string := "NONE";
|
1085 |
|
|
-- StratixII only : to bypass clock enable or using clock enable
|
1086 |
|
|
clock_enable_input_a : string := "NORMAL";
|
1087 |
|
|
clock_enable_output_a : string := "NORMAL";
|
1088 |
|
|
clock_enable_input_b : string := "NORMAL";
|
1089 |
|
|
clock_enable_output_b : string := "NORMAL";
|
1090 |
|
|
-- width of the byte enable ports. if it is used, must be WIDTH_WRITE_A/8 or /9
|
1091 |
|
|
width_byteena_b : integer := 1;
|
1092 |
|
|
-- clock enable setting for the core
|
1093 |
|
|
clock_enable_core_a : string := "USE_INPUT_CLKEN";
|
1094 |
|
|
clock_enable_core_b : string := "USE_INPUT_CLKEN";
|
1095 |
|
|
-- read-during-write-same-port setting
|
1096 |
|
|
read_during_write_mode_port_a : string := "NEW_DATA_NO_NBE_READ";
|
1097 |
|
|
read_during_write_mode_port_b : string := "NEW_DATA_NO_NBE_READ";
|
1098 |
|
|
-- ECC status ports setting
|
1099 |
|
|
enable_ecc : string := "FALSE";
|
1100 |
|
|
ecc_pipeline_stage_enabled : string := "FALSE";
|
1101 |
|
|
|
1102 |
|
|
width_eccstatus : integer := 3;
|
1103 |
|
|
-- global parameters
|
1104 |
|
|
-- width of a byte for byte enables
|
1105 |
|
|
byte_size : integer := 0;
|
1106 |
|
|
read_during_write_mode_mixed_ports: string := "DONT_CARE";
|
1107 |
|
|
-- ram block type choices are "AUTO", "M512", "M4K" and "MEGARAM"
|
1108 |
|
|
ram_block_type : string := "AUTO";
|
1109 |
|
|
-- determine whether LE support is turned on or off for altsyncram
|
1110 |
|
|
implement_in_les : string := "OFF";
|
1111 |
|
|
-- determine whether RAM would be power up to uninitialized or not
|
1112 |
|
|
power_up_uninitialized : string := "FALSE";
|
1113 |
|
|
|
1114 |
|
|
sim_show_memory_data_in_port_b_layout : string := "OFF";
|
1115 |
|
|
|
1116 |
|
|
-- general operation parameters
|
1117 |
|
|
init_file : string := "UNUSED";
|
1118 |
|
|
init_file_layout : string := "UNUSED";
|
1119 |
|
|
maximum_depth : integer := 0;
|
1120 |
|
|
intended_device_family : string := "Stratix";
|
1121 |
|
|
lpm_hint : string := "UNUSED";
|
1122 |
|
|
lpm_type : string := "altsyncram" );
|
1123 |
|
|
port (
|
1124 |
|
|
wren_a : in std_logic := '0';
|
1125 |
|
|
wren_b : in std_logic := '0';
|
1126 |
|
|
rden_a : in std_logic := '1';
|
1127 |
|
|
rden_b : in std_logic := '1';
|
1128 |
|
|
data_a : in std_logic_vector(width_a - 1 downto 0):= (others => '1');
|
1129 |
|
|
data_b : in std_logic_vector(width_b - 1 downto 0):= (others => '1');
|
1130 |
|
|
address_a : in std_logic_vector(widthad_a - 1 downto 0);
|
1131 |
|
|
address_b : in std_logic_vector(widthad_b - 1 downto 0) := (others => '1');
|
1132 |
|
|
|
1133 |
|
|
clock0 : in std_logic := '1';
|
1134 |
|
|
clock1 : in std_logic := 'Z';
|
1135 |
|
|
clocken0 : in std_logic := '1';
|
1136 |
|
|
clocken1 : in std_logic := '1';
|
1137 |
|
|
clocken2 : in std_logic := '1';
|
1138 |
|
|
clocken3 : in std_logic := '1';
|
1139 |
|
|
aclr0 : in std_logic := '0';
|
1140 |
|
|
aclr1 : in std_logic := '0';
|
1141 |
|
|
byteena_a : in std_logic_vector( (width_byteena_a - 1) downto 0) := (others => '1');
|
1142 |
|
|
byteena_b : in std_logic_vector( (width_byteena_b - 1) downto 0) := (others => 'Z');
|
1143 |
|
|
|
1144 |
|
|
addressstall_a : in std_logic := '0';
|
1145 |
|
|
addressstall_b : in std_logic := '0';
|
1146 |
|
|
|
1147 |
|
|
q_a : out std_logic_vector(width_a - 1 downto 0);
|
1148 |
|
|
q_b : out std_logic_vector(width_b - 1 downto 0);
|
1149 |
|
|
|
1150 |
|
|
eccstatus : out std_logic_vector(width_eccstatus-1 downto 0) := (others => '0') );
|
1151 |
|
|
end component;
|
1152 |
|
|
|
1153 |
|
|
component altpll
|
1154 |
|
|
generic (
|
1155 |
|
|
intended_device_family : string := "Stratix" ;
|
1156 |
|
|
operation_mode : string := "NORMAL" ;
|
1157 |
|
|
pll_type : string := "AUTO" ;
|
1158 |
|
|
qualify_conf_done : string := "OFF" ;
|
1159 |
|
|
compensate_clock : string := "CLK0" ;
|
1160 |
|
|
scan_chain : string := "LONG";
|
1161 |
|
|
primary_clock : string := "inclk0" ;
|
1162 |
|
|
inclk0_input_frequency : natural; -- required parameter
|
1163 |
|
|
inclk1_input_frequency : natural := 0;
|
1164 |
|
|
gate_lock_signal : string := "NO";
|
1165 |
|
|
gate_lock_counter : integer := 0;
|
1166 |
|
|
lock_high : natural := 1;
|
1167 |
|
|
lock_low : natural := 0;
|
1168 |
|
|
valid_lock_multiplier : natural := 1;
|
1169 |
|
|
invalid_lock_multiplier : natural := 5;
|
1170 |
|
|
switch_over_type : string := "AUTO";
|
1171 |
|
|
switch_over_on_lossclk : string := "OFF" ;
|
1172 |
|
|
switch_over_on_gated_lock : string := "OFF" ;
|
1173 |
|
|
enable_switch_over_counter : string := "OFF";
|
1174 |
|
|
switch_over_counter : natural := 0;
|
1175 |
|
|
feedback_source : string := "EXTCLK0" ;
|
1176 |
|
|
bandwidth : natural := 0;
|
1177 |
|
|
bandwidth_type : string := "UNUSED";
|
1178 |
|
|
spread_frequency : natural := 0;
|
1179 |
|
|
down_spread : string := "0.0";
|
1180 |
|
|
self_reset_on_gated_loss_lock : string := "OFF";
|
1181 |
|
|
self_reset_on_loss_lock : string := "OFF";
|
1182 |
|
|
lock_window_ui : string := "0.05";
|
1183 |
|
|
width_clock : natural := 6;
|
1184 |
|
|
width_phasecounterselect : natural := 4;
|
1185 |
|
|
charge_pump_current_bits : natural := 9999;
|
1186 |
|
|
loop_filter_c_bits : natural := 9999;
|
1187 |
|
|
loop_filter_r_bits : natural := 9999;
|
1188 |
|
|
scan_chain_mif_file : string := "UNUSED";
|
1189 |
|
|
|
1190 |
|
|
-- simulation-only parameters
|
1191 |
|
|
simulation_type : string := "functional";
|
1192 |
|
|
source_is_pll : string := "off";
|
1193 |
|
|
skip_vco : string := "off";
|
1194 |
|
|
|
1195 |
|
|
-- internal clock specifications
|
1196 |
|
|
clk9_multiply_by : natural := 1;
|
1197 |
|
|
clk8_multiply_by : natural := 1;
|
1198 |
|
|
clk7_multiply_by : natural := 1;
|
1199 |
|
|
clk6_multiply_by : natural := 1;
|
1200 |
|
|
clk5_multiply_by : natural := 1;
|
1201 |
|
|
clk4_multiply_by : natural := 1;
|
1202 |
|
|
clk3_multiply_by : natural := 1;
|
1203 |
|
|
clk2_multiply_by : natural := 1;
|
1204 |
|
|
clk1_multiply_by : natural := 1;
|
1205 |
|
|
clk0_multiply_by : natural := 1;
|
1206 |
|
|
clk9_divide_by : natural := 1;
|
1207 |
|
|
clk8_divide_by : natural := 1;
|
1208 |
|
|
clk7_divide_by : natural := 1;
|
1209 |
|
|
clk6_divide_by : natural := 1;
|
1210 |
|
|
clk5_divide_by : natural := 1;
|
1211 |
|
|
clk4_divide_by : natural := 1;
|
1212 |
|
|
clk3_divide_by : natural := 1;
|
1213 |
|
|
clk2_divide_by : natural := 1;
|
1214 |
|
|
clk1_divide_by : natural := 1;
|
1215 |
|
|
clk0_divide_by : natural := 1;
|
1216 |
|
|
clk9_phase_shift : string := "0";
|
1217 |
|
|
clk8_phase_shift : string := "0";
|
1218 |
|
|
clk7_phase_shift : string := "0";
|
1219 |
|
|
clk6_phase_shift : string := "0";
|
1220 |
|
|
clk5_phase_shift : string := "0";
|
1221 |
|
|
clk4_phase_shift : string := "0";
|
1222 |
|
|
clk3_phase_shift : string := "0";
|
1223 |
|
|
clk2_phase_shift : string := "0";
|
1224 |
|
|
clk1_phase_shift : string := "0";
|
1225 |
|
|
clk0_phase_shift : string := "0";
|
1226 |
|
|
clk5_time_delay : string := "0";
|
1227 |
|
|
clk4_time_delay : string := "0";
|
1228 |
|
|
clk3_time_delay : string := "0";
|
1229 |
|
|
clk2_time_delay : string := "0";
|
1230 |
|
|
clk1_time_delay : string := "0";
|
1231 |
|
|
clk0_time_delay : string := "0";
|
1232 |
|
|
clk9_duty_cycle : natural := 50;
|
1233 |
|
|
clk8_duty_cycle : natural := 50;
|
1234 |
|
|
clk7_duty_cycle : natural := 50;
|
1235 |
|
|
clk6_duty_cycle : natural := 50;
|
1236 |
|
|
clk5_duty_cycle : natural := 50;
|
1237 |
|
|
clk4_duty_cycle : natural := 50;
|
1238 |
|
|
clk3_duty_cycle : natural := 50;
|
1239 |
|
|
clk2_duty_cycle : natural := 50;
|
1240 |
|
|
clk1_duty_cycle : natural := 50;
|
1241 |
|
|
clk0_duty_cycle : natural := 50;
|
1242 |
|
|
clk2_output_frequency : natural := 0;
|
1243 |
|
|
clk1_output_frequency : natural := 0;
|
1244 |
|
|
clk0_output_frequency : natural := 0;
|
1245 |
|
|
clk9_use_even_counter_mode : string := "OFF";
|
1246 |
|
|
clk8_use_even_counter_mode : string := "OFF";
|
1247 |
|
|
clk7_use_even_counter_mode : string := "OFF";
|
1248 |
|
|
clk6_use_even_counter_mode : string := "OFF";
|
1249 |
|
|
clk5_use_even_counter_mode : string := "OFF";
|
1250 |
|
|
clk4_use_even_counter_mode : string := "OFF";
|
1251 |
|
|
clk3_use_even_counter_mode : string := "OFF";
|
1252 |
|
|
clk2_use_even_counter_mode : string := "OFF";
|
1253 |
|
|
clk1_use_even_counter_mode : string := "OFF";
|
1254 |
|
|
clk0_use_even_counter_mode : string := "OFF";
|
1255 |
|
|
clk9_use_even_counter_value : string := "OFF";
|
1256 |
|
|
clk8_use_even_counter_value : string := "OFF";
|
1257 |
|
|
clk7_use_even_counter_value : string := "OFF";
|
1258 |
|
|
clk6_use_even_counter_value : string := "OFF";
|
1259 |
|
|
clk5_use_even_counter_value : string := "OFF";
|
1260 |
|
|
clk4_use_even_counter_value : string := "OFF";
|
1261 |
|
|
clk3_use_even_counter_value : string := "OFF";
|
1262 |
|
|
clk2_use_even_counter_value : string := "OFF";
|
1263 |
|
|
clk1_use_even_counter_value : string := "OFF";
|
1264 |
|
|
clk0_use_even_counter_value : string := "OFF";
|
1265 |
|
|
|
1266 |
|
|
-- external clock specifications
|
1267 |
|
|
extclk3_multiply_by : natural := 1;
|
1268 |
|
|
extclk2_multiply_by : natural := 1;
|
1269 |
|
|
extclk1_multiply_by : natural := 1;
|
1270 |
|
|
extclk0_multiply_by : natural := 1;
|
1271 |
|
|
extclk3_divide_by : natural := 1;
|
1272 |
|
|
extclk2_divide_by : natural := 1;
|
1273 |
|
|
extclk1_divide_by : natural := 1;
|
1274 |
|
|
extclk0_divide_by : natural := 1;
|
1275 |
|
|
extclk3_phase_shift : string := "0";
|
1276 |
|
|
extclk2_phase_shift : string := "0";
|
1277 |
|
|
extclk1_phase_shift : string := "0";
|
1278 |
|
|
extclk0_phase_shift : string := "0";
|
1279 |
|
|
extclk3_time_delay : string := "0";
|
1280 |
|
|
extclk2_time_delay : string := "0";
|
1281 |
|
|
extclk1_time_delay : string := "0";
|
1282 |
|
|
extclk0_time_delay : string := "0";
|
1283 |
|
|
extclk3_duty_cycle : natural := 50;
|
1284 |
|
|
extclk2_duty_cycle : natural := 50;
|
1285 |
|
|
extclk1_duty_cycle : natural := 50;
|
1286 |
|
|
extclk0_duty_cycle : natural := 50;
|
1287 |
|
|
vco_multiply_by : integer := 0;
|
1288 |
|
|
vco_divide_by : integer := 0;
|
1289 |
|
|
sclkout0_phase_shift : string := "0";
|
1290 |
|
|
sclkout1_phase_shift : string := "0";
|
1291 |
|
|
|
1292 |
|
|
dpa_multiply_by : integer := 0;
|
1293 |
|
|
dpa_divide_by : integer := 0;
|
1294 |
|
|
dpa_divider : integer := 0;
|
1295 |
|
|
|
1296 |
|
|
-- advanced user parameters
|
1297 |
|
|
vco_min : natural := 0;
|
1298 |
|
|
vco_max : natural := 0;
|
1299 |
|
|
vco_center : natural := 0;
|
1300 |
|
|
pfd_min : natural := 0;
|
1301 |
|
|
pfd_max : natural := 0;
|
1302 |
|
|
m_initial : natural := 1;
|
1303 |
|
|
m : natural := 0; -- m must default to 0 to force altpll to calculate the internal parameters for itself
|
1304 |
|
|
n : natural := 1;
|
1305 |
|
|
m2 : natural := 1;
|
1306 |
|
|
n2 : natural := 1;
|
1307 |
|
|
ss : natural := 0;
|
1308 |
|
|
c0_high : natural := 1;
|
1309 |
|
|
c1_high : natural := 1;
|
1310 |
|
|
c2_high : natural := 1;
|
1311 |
|
|
c3_high : natural := 1;
|
1312 |
|
|
c4_high : natural := 1;
|
1313 |
|
|
c5_high : natural := 1;
|
1314 |
|
|
c6_high : natural := 1;
|
1315 |
|
|
c7_high : natural := 1;
|
1316 |
|
|
c8_high : natural := 1;
|
1317 |
|
|
c9_high : natural := 1;
|
1318 |
|
|
l0_high : natural := 1;
|
1319 |
|
|
l1_high : natural := 1;
|
1320 |
|
|
g0_high : natural := 1;
|
1321 |
|
|
g1_high : natural := 1;
|
1322 |
|
|
g2_high : natural := 1;
|
1323 |
|
|
g3_high : natural := 1;
|
1324 |
|
|
e0_high : natural := 1;
|
1325 |
|
|
e1_high : natural := 1;
|
1326 |
|
|
e2_high : natural := 1;
|
1327 |
|
|
e3_high : natural := 1;
|
1328 |
|
|
c0_low : natural := 1;
|
1329 |
|
|
c1_low : natural := 1;
|
1330 |
|
|
c2_low : natural := 1;
|
1331 |
|
|
c3_low : natural := 1;
|
1332 |
|
|
c4_low : natural := 1;
|
1333 |
|
|
c5_low : natural := 1;
|
1334 |
|
|
c6_low : natural := 1;
|
1335 |
|
|
c7_low : natural := 1;
|
1336 |
|
|
c8_low : natural := 1;
|
1337 |
|
|
c9_low : natural := 1;
|
1338 |
|
|
l0_low : natural := 1;
|
1339 |
|
|
l1_low : natural := 1;
|
1340 |
|
|
g0_low : natural := 1;
|
1341 |
|
|
g1_low : natural := 1;
|
1342 |
|
|
g2_low : natural := 1;
|
1343 |
|
|
g3_low : natural := 1;
|
1344 |
|
|
e0_low : natural := 1;
|
1345 |
|
|
e1_low : natural := 1;
|
1346 |
|
|
e2_low : natural := 1;
|
1347 |
|
|
e3_low : natural := 1;
|
1348 |
|
|
c0_initial : natural := 1;
|
1349 |
|
|
c1_initial : natural := 1;
|
1350 |
|
|
c2_initial : natural := 1;
|
1351 |
|
|
c3_initial : natural := 1;
|
1352 |
|
|
c4_initial : natural := 1;
|
1353 |
|
|
c5_initial : natural := 1;
|
1354 |
|
|
c6_initial : natural := 1;
|
1355 |
|
|
c7_initial : natural := 1;
|
1356 |
|
|
c8_initial : natural := 1;
|
1357 |
|
|
c9_initial : natural := 1;
|
1358 |
|
|
l0_initial : natural := 1;
|
1359 |
|
|
l1_initial : natural := 1;
|
1360 |
|
|
g0_initial : natural := 1;
|
1361 |
|
|
g1_initial : natural := 1;
|
1362 |
|
|
g2_initial : natural := 1;
|
1363 |
|
|
g3_initial : natural := 1;
|
1364 |
|
|
e0_initial : natural := 1;
|
1365 |
|
|
e1_initial : natural := 1;
|
1366 |
|
|
e2_initial : natural := 1;
|
1367 |
|
|
e3_initial : natural := 1;
|
1368 |
|
|
c0_mode : string := "bypass" ;
|
1369 |
|
|
c1_mode : string := "bypass" ;
|
1370 |
|
|
c2_mode : string := "bypass" ;
|
1371 |
|
|
c3_mode : string := "bypass" ;
|
1372 |
|
|
c4_mode : string := "bypass" ;
|
1373 |
|
|
c5_mode : string := "bypass" ;
|
1374 |
|
|
c6_mode : string := "bypass" ;
|
1375 |
|
|
c7_mode : string := "bypass" ;
|
1376 |
|
|
c8_mode : string := "bypass" ;
|
1377 |
|
|
c9_mode : string := "bypass" ;
|
1378 |
|
|
l0_mode : string := "bypass" ;
|
1379 |
|
|
l1_mode : string := "bypass" ;
|
1380 |
|
|
g0_mode : string := "bypass" ;
|
1381 |
|
|
g1_mode : string := "bypass" ;
|
1382 |
|
|
g2_mode : string := "bypass" ;
|
1383 |
|
|
g3_mode : string := "bypass" ;
|
1384 |
|
|
e0_mode : string := "bypass" ;
|
1385 |
|
|
e1_mode : string := "bypass" ;
|
1386 |
|
|
e2_mode : string := "bypass" ;
|
1387 |
|
|
e3_mode : string := "bypass" ;
|
1388 |
|
|
c0_ph : natural := 0;
|
1389 |
|
|
c1_ph : natural := 0;
|
1390 |
|
|
c2_ph : natural := 0;
|
1391 |
|
|
c3_ph : natural := 0;
|
1392 |
|
|
c4_ph : natural := 0;
|
1393 |
|
|
c5_ph : natural := 0;
|
1394 |
|
|
c6_ph : natural := 0;
|
1395 |
|
|
c7_ph : natural := 0;
|
1396 |
|
|
c8_ph : natural := 0;
|
1397 |
|
|
c9_ph : natural := 0;
|
1398 |
|
|
l0_ph : natural := 0;
|
1399 |
|
|
l1_ph : natural := 0;
|
1400 |
|
|
g0_ph : natural := 0;
|
1401 |
|
|
g1_ph : natural := 0;
|
1402 |
|
|
g2_ph : natural := 0;
|
1403 |
|
|
g3_ph : natural := 0;
|
1404 |
|
|
e0_ph : natural := 0;
|
1405 |
|
|
e1_ph : natural := 0;
|
1406 |
|
|
e2_ph : natural := 0;
|
1407 |
|
|
e3_ph : natural := 0;
|
1408 |
|
|
m_ph : natural := 0;
|
1409 |
|
|
l0_time_delay : natural := 0;
|
1410 |
|
|
l1_time_delay : natural := 0;
|
1411 |
|
|
g0_time_delay : natural := 0;
|
1412 |
|
|
g1_time_delay : natural := 0;
|
1413 |
|
|
g2_time_delay : natural := 0;
|
1414 |
|
|
g3_time_delay : natural := 0;
|
1415 |
|
|
e0_time_delay : natural := 0;
|
1416 |
|
|
e1_time_delay : natural := 0;
|
1417 |
|
|
e2_time_delay : natural := 0;
|
1418 |
|
|
e3_time_delay : natural := 0;
|
1419 |
|
|
m_time_delay : natural := 0;
|
1420 |
|
|
n_time_delay : natural := 0;
|
1421 |
|
|
c1_use_casc_in : string := "off";
|
1422 |
|
|
c2_use_casc_in : string := "off";
|
1423 |
|
|
c3_use_casc_in : string := "off";
|
1424 |
|
|
c4_use_casc_in : string := "off";
|
1425 |
|
|
c5_use_casc_in : string := "off";
|
1426 |
|
|
c6_use_casc_in : string := "off";
|
1427 |
|
|
c7_use_casc_in : string := "off";
|
1428 |
|
|
c8_use_casc_in : string := "off";
|
1429 |
|
|
c9_use_casc_in : string := "off";
|
1430 |
|
|
m_test_source : integer := 5;
|
1431 |
|
|
c0_test_source : integer := 5;
|
1432 |
|
|
c1_test_source : integer := 5;
|
1433 |
|
|
c2_test_source : integer := 5;
|
1434 |
|
|
c3_test_source : integer := 5;
|
1435 |
|
|
c4_test_source : integer := 5;
|
1436 |
|
|
c5_test_source : integer := 5;
|
1437 |
|
|
c6_test_source : integer := 5;
|
1438 |
|
|
c7_test_source : integer := 5;
|
1439 |
|
|
c8_test_source : integer := 5;
|
1440 |
|
|
c9_test_source : integer := 5;
|
1441 |
|
|
extclk3_counter : string := "e3" ;
|
1442 |
|
|
extclk2_counter : string := "e2" ;
|
1443 |
|
|
extclk1_counter : string := "e1" ;
|
1444 |
|
|
extclk0_counter : string := "e0" ;
|
1445 |
|
|
clk9_counter : string := "c9" ;
|
1446 |
|
|
clk8_counter : string := "c8" ;
|
1447 |
|
|
clk7_counter : string := "c7" ;
|
1448 |
|
|
clk6_counter : string := "c6" ;
|
1449 |
|
|
clk5_counter : string := "l1" ;
|
1450 |
|
|
clk4_counter : string := "l0" ;
|
1451 |
|
|
clk3_counter : string := "g3" ;
|
1452 |
|
|
clk2_counter : string := "g2" ;
|
1453 |
|
|
clk1_counter : string := "g1" ;
|
1454 |
|
|
clk0_counter : string := "g0" ;
|
1455 |
|
|
enable0_counter : string := "l0";
|
1456 |
|
|
enable1_counter : string := "l0";
|
1457 |
|
|
charge_pump_current : natural := 2;
|
1458 |
|
|
loop_filter_r : string := " 1.000000";
|
1459 |
|
|
loop_filter_c : natural := 5;
|
1460 |
|
|
vco_post_scale : natural := 0;
|
1461 |
|
|
vco_frequency_control : string := "AUTO";
|
1462 |
|
|
vco_phase_shift_step : natural := 0;
|
1463 |
|
|
lpm_hint : string := "UNUSED";
|
1464 |
|
|
lpm_type : string := "altpll";
|
1465 |
|
|
port_clkena0 : string := "PORT_CONNECTIVITY";
|
1466 |
|
|
port_clkena1 : string := "PORT_CONNECTIVITY";
|
1467 |
|
|
port_clkena2 : string := "PORT_CONNECTIVITY";
|
1468 |
|
|
port_clkena3 : string := "PORT_CONNECTIVITY";
|
1469 |
|
|
port_clkena4 : string := "PORT_CONNECTIVITY";
|
1470 |
|
|
port_clkena5 : string := "PORT_CONNECTIVITY";
|
1471 |
|
|
port_extclkena0 : string := "PORT_CONNECTIVITY";
|
1472 |
|
|
port_extclkena1 : string := "PORT_CONNECTIVITY";
|
1473 |
|
|
port_extclkena2 : string := "PORT_CONNECTIVITY";
|
1474 |
|
|
port_extclkena3 : string := "PORT_CONNECTIVITY";
|
1475 |
|
|
port_extclk0 : string := "PORT_CONNECTIVITY";
|
1476 |
|
|
port_extclk1 : string := "PORT_CONNECTIVITY";
|
1477 |
|
|
port_extclk2 : string := "PORT_CONNECTIVITY";
|
1478 |
|
|
port_extclk3 : string := "PORT_CONNECTIVITY";
|
1479 |
|
|
port_clkbad0 : string := "PORT_CONNECTIVITY";
|
1480 |
|
|
port_clkbad1 : string := "PORT_CONNECTIVITY";
|
1481 |
|
|
port_clk0 : string := "PORT_CONNECTIVITY";
|
1482 |
|
|
port_clk1 : string := "PORT_CONNECTIVITY";
|
1483 |
|
|
port_clk2 : string := "PORT_CONNECTIVITY";
|
1484 |
|
|
port_clk3 : string := "PORT_CONNECTIVITY";
|
1485 |
|
|
port_clk4 : string := "PORT_CONNECTIVITY";
|
1486 |
|
|
port_clk5 : string := "PORT_CONNECTIVITY";
|
1487 |
|
|
port_clk6 : string := "PORT_CONNECTIVITY";
|
1488 |
|
|
port_clk7 : string := "PORT_CONNECTIVITY";
|
1489 |
|
|
port_clk8 : string := "PORT_CONNECTIVITY";
|
1490 |
|
|
port_clk9 : string := "PORT_CONNECTIVITY";
|
1491 |
|
|
port_scandata : string := "PORT_CONNECTIVITY";
|
1492 |
|
|
port_scandataout : string := "PORT_CONNECTIVITY";
|
1493 |
|
|
port_scandone : string := "PORT_CONNECTIVITY";
|
1494 |
|
|
port_sclkout1 : string := "PORT_CONNECTIVITY";
|
1495 |
|
|
port_sclkout0 : string := "PORT_CONNECTIVITY";
|
1496 |
|
|
port_activeclock : string := "PORT_CONNECTIVITY";
|
1497 |
|
|
port_clkloss : string := "PORT_CONNECTIVITY";
|
1498 |
|
|
port_inclk1 : string := "PORT_CONNECTIVITY";
|
1499 |
|
|
port_inclk0 : string := "PORT_CONNECTIVITY";
|
1500 |
|
|
port_fbin : string := "PORT_CONNECTIVITY";
|
1501 |
|
|
port_fbout : string := "PORT_CONNECTIVITY";
|
1502 |
|
|
port_pllena : string := "PORT_CONNECTIVITY";
|
1503 |
|
|
port_clkswitch : string := "PORT_CONNECTIVITY";
|
1504 |
|
|
port_areset : string := "PORT_CONNECTIVITY";
|
1505 |
|
|
port_pfdena : string := "PORT_CONNECTIVITY";
|
1506 |
|
|
port_scanclk : string := "PORT_CONNECTIVITY";
|
1507 |
|
|
port_scanaclr : string := "PORT_CONNECTIVITY";
|
1508 |
|
|
port_scanread : string := "PORT_CONNECTIVITY";
|
1509 |
|
|
port_scanwrite : string := "PORT_CONNECTIVITY";
|
1510 |
|
|
port_enable0 : string := "PORT_CONNECTIVITY";
|
1511 |
|
|
port_enable1 : string := "PORT_CONNECTIVITY";
|
1512 |
|
|
port_locked : string := "PORT_CONNECTIVITY";
|
1513 |
|
|
port_configupdate : string := "PORT_CONNECTIVITY";
|
1514 |
|
|
port_phasecounterselect : string := "PORT_CONNECTIVITY";
|
1515 |
|
|
port_phasedone : string := "PORT_CONNECTIVITY";
|
1516 |
|
|
port_phasestep : string := "PORT_CONNECTIVITY";
|
1517 |
|
|
port_phaseupdown : string := "PORT_CONNECTIVITY";
|
1518 |
|
|
port_vcooverrange : string := "PORT_CONNECTIVITY";
|
1519 |
|
|
port_vcounderrange : string := "PORT_CONNECTIVITY";
|
1520 |
|
|
port_scanclkena : string := "PORT_CONNECTIVITY";
|
1521 |
|
|
using_fbmimicbidir_port : string := "ON";
|
1522 |
|
|
sim_gate_lock_device_behavior : string := "OFF" );
|
1523 |
|
|
port (
|
1524 |
|
|
inclk : in std_logic_vector(1 downto 0) := (others => '0');
|
1525 |
|
|
fbin : in std_logic := '0';
|
1526 |
|
|
pllena : in std_logic := '1';
|
1527 |
|
|
clkswitch : in std_logic := '0';
|
1528 |
|
|
areset : in std_logic := '0';
|
1529 |
|
|
pfdena : in std_logic := '1';
|
1530 |
|
|
clkena : in std_logic_vector(5 downto 0) := (others => '1');
|
1531 |
|
|
extclkena : in std_logic_vector(3 downto 0) := (others => '1');
|
1532 |
|
|
scanclk : in std_logic := '0';
|
1533 |
|
|
scanclkena : in std_logic := '1';
|
1534 |
|
|
scanaclr : in std_logic := '0';
|
1535 |
|
|
scanread : in std_logic := '0';
|
1536 |
|
|
scanwrite : in std_logic := '0';
|
1537 |
|
|
scandata : in std_logic := '0';
|
1538 |
|
|
phasecounterselect : in std_logic_vector(width_phasecounterselect-1 downto 0) := (others => '0');
|
1539 |
|
|
phaseupdown : in std_logic := '0';
|
1540 |
|
|
phasestep : in std_logic := '0';
|
1541 |
|
|
configupdate : in std_logic := '0';
|
1542 |
|
|
fbmimicbidir : inout std_logic := '1';
|
1543 |
|
|
clk : out std_logic_vector(width_clock-1 downto 0);
|
1544 |
|
|
extclk : out std_logic_vector(3 downto 0);
|
1545 |
|
|
clkbad : out std_logic_vector(1 downto 0);
|
1546 |
|
|
enable0 : out std_logic;
|
1547 |
|
|
enable1 : out std_logic;
|
1548 |
|
|
activeclock : out std_logic;
|
1549 |
|
|
clkloss : out std_logic;
|
1550 |
|
|
locked : out std_logic;
|
1551 |
|
|
scandataout : out std_logic;
|
1552 |
|
|
scandone : out std_logic;
|
1553 |
|
|
sclkout0 : out std_logic;
|
1554 |
|
|
sclkout1 : out std_logic;
|
1555 |
|
|
phasedone : out std_logic;
|
1556 |
|
|
vcooverrange : out std_logic;
|
1557 |
|
|
vcounderrange : out std_logic;
|
1558 |
|
|
fbout : out std_logic;
|
1559 |
|
|
fref : out std_logic;
|
1560 |
|
|
icdrclk : out std_logic );
|
1561 |
|
|
end component;
|
1562 |
|
|
|
1563 |
|
|
component altfp_mult
|
1564 |
|
|
generic (
|
1565 |
|
|
width_exp : integer := 11;
|
1566 |
|
|
width_man : integer := 31;
|
1567 |
|
|
dedicated_multiplier_circuitry : string := "AUTO";
|
1568 |
|
|
reduced_functionality : string := "NO";
|
1569 |
|
|
pipeline : natural := 5;
|
1570 |
|
|
denormal_support : string := "YES";
|
1571 |
|
|
exception_handling : string := "YES";
|
1572 |
|
|
lpm_hint : string := "UNUSED";
|
1573 |
|
|
lpm_type : string := "altfp_mult" );
|
1574 |
|
|
port (
|
1575 |
|
|
clock : in std_logic;
|
1576 |
|
|
clk_en : in std_logic := '1';
|
1577 |
|
|
aclr : in std_logic := '0';
|
1578 |
|
|
dataa : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
|
1579 |
|
|
datab : in std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
|
1580 |
|
|
result : out std_logic_vector(WIDTH_EXP + WIDTH_MAN downto 0) ;
|
1581 |
|
|
overflow : out std_logic ;
|
1582 |
|
|
underflow : out std_logic ;
|
1583 |
|
|
zero : out std_logic ;
|
1584 |
|
|
denormal : out std_logic ;
|
1585 |
|
|
indefinite : out std_logic ;
|
1586 |
|
|
nan : out std_logic );
|
1587 |
|
|
end component;
|
1588 |
|
|
|
1589 |
|
|
component altsqrt
|
1590 |
|
|
generic (
|
1591 |
|
|
q_port_width : integer := 1;
|
1592 |
|
|
r_port_width : integer := 1;
|
1593 |
|
|
width : integer := 1;
|
1594 |
|
|
pipeline : integer := 0;
|
1595 |
|
|
lpm_hint : string := "UNUSED";
|
1596 |
|
|
lpm_type : string := "altsqrt" );
|
1597 |
|
|
port (
|
1598 |
|
|
radical : in std_logic_vector(width - 1 downto 0) ;
|
1599 |
|
|
clk : in std_logic := '1';
|
1600 |
|
|
ena : in std_logic := '1';
|
1601 |
|
|
aclr : in std_logic := '0';
|
1602 |
|
|
q : out std_logic_vector( q_port_width - 1 downto 0) ;
|
1603 |
|
|
remainder : out std_logic_vector( r_port_width - 1 downto 0) );
|
1604 |
|
|
end component;
|
1605 |
|
|
|
1606 |
|
|
component parallel_add
|
1607 |
|
|
generic (
|
1608 |
|
|
width : natural := 4;
|
1609 |
|
|
size : natural := 2;
|
1610 |
|
|
widthr : natural := 4;
|
1611 |
|
|
shift : natural := 0;
|
1612 |
|
|
msw_subtract : string := "NO";
|
1613 |
|
|
representation : string := "UNSIGNED";
|
1614 |
|
|
pipeline : natural := 0;
|
1615 |
|
|
result_alignment : string := "LSB";
|
1616 |
|
|
lpm_hint : string := "UNUSED";
|
1617 |
|
|
lpm_type : string := "parallel_add" );
|
1618 |
|
|
port (
|
1619 |
|
|
data : in altera_mf_logic_2D(size - 1 downto 0, width - 1 downto 0);
|
1620 |
|
|
clock : in std_logic := '1';
|
1621 |
|
|
aclr : in std_logic := '0';
|
1622 |
|
|
clken : in std_logic := '1';
|
1623 |
|
|
result : out std_logic_vector(widthr - 1 downto 0) );
|
1624 |
|
|
end component;
|
1625 |
|
|
|
1626 |
|
|
component a_graycounter
|
1627 |
|
|
generic (
|
1628 |
|
|
width : natural;
|
1629 |
|
|
pvalue : natural;
|
1630 |
|
|
lpm_hint : string := "UNUSED";
|
1631 |
|
|
lpm_type : string := "a_graycounter" );
|
1632 |
|
|
port (
|
1633 |
|
|
clock : in std_logic;
|
1634 |
|
|
clk_en : in std_logic := '1';
|
1635 |
|
|
cnt_en : in std_logic := '1';
|
1636 |
|
|
updown : in std_logic := '1';
|
1637 |
|
|
aclr : in std_logic := '0';
|
1638 |
|
|
sclr : in std_logic := '0';
|
1639 |
|
|
qbin : out std_logic_vector(width-1 downto 0);
|
1640 |
|
|
q : out std_logic_vector(width-1 downto 0) );
|
1641 |
|
|
end component;
|
1642 |
|
|
|
1643 |
|
|
component altsquare
|
1644 |
|
|
generic (
|
1645 |
|
|
data_width : natural;
|
1646 |
|
|
pipeline : natural;
|
1647 |
|
|
representation : string := "UNSIGNED";
|
1648 |
|
|
result_alignment : string := "LSB";
|
1649 |
|
|
result_width : natural;
|
1650 |
|
|
lpm_hint : string := "UNUSED";
|
1651 |
|
|
lpm_type : string := "altsquare"
|
1652 |
|
|
);
|
1653 |
|
|
port(
|
1654 |
|
|
aclr : in std_logic := '0';
|
1655 |
|
|
clock : in std_logic := '1';
|
1656 |
|
|
data : in std_logic_vector(data_width-1 downto 0);
|
1657 |
|
|
ena : in std_logic := '1';
|
1658 |
|
|
result : out std_logic_vector(result_width-1 downto 0)
|
1659 |
|
|
);
|
1660 |
|
|
end component;
|
1661 |
|
|
|
1662 |
|
|
component sld_virtual_jtag
|
1663 |
|
|
generic (
|
1664 |
|
|
lpm_type : string;
|
1665 |
|
|
lpm_hint : string;
|
1666 |
|
|
sld_auto_instance_index : string;
|
1667 |
|
|
sld_instance_index : integer;
|
1668 |
|
|
sld_ir_width : integer;
|
1669 |
|
|
sld_sim_n_scan : integer;
|
1670 |
|
|
sld_sim_total_length : integer;
|
1671 |
|
|
sld_sim_action : string);
|
1672 |
|
|
port (
|
1673 |
|
|
tdo : in std_logic := '0';
|
1674 |
|
|
ir_out : in std_logic_vector(sld_ir_width - 1 downto 0) := (others => '0');
|
1675 |
|
|
tck : out std_logic;
|
1676 |
|
|
tdi : out std_logic;
|
1677 |
|
|
ir_in : out std_logic_vector(sld_ir_width - 1 downto 0);
|
1678 |
|
|
virtual_state_cdr : out std_logic;
|
1679 |
|
|
virtual_state_sdr : out std_logic;
|
1680 |
|
|
virtual_state_e1dr : out std_logic;
|
1681 |
|
|
virtual_state_pdr : out std_logic;
|
1682 |
|
|
virtual_state_e2dr : out std_logic;
|
1683 |
|
|
virtual_state_udr : out std_logic;
|
1684 |
|
|
virtual_state_cir : out std_logic;
|
1685 |
|
|
virtual_state_uir : out std_logic;
|
1686 |
|
|
jtag_state_tlr : out std_logic;
|
1687 |
|
|
jtag_state_rti : out std_logic;
|
1688 |
|
|
jtag_state_sdrs : out std_logic;
|
1689 |
|
|
jtag_state_cdr : out std_logic;
|
1690 |
|
|
jtag_state_sdr : out std_logic;
|
1691 |
|
|
jtag_state_e1dr : out std_logic;
|
1692 |
|
|
jtag_state_pdr : out std_logic;
|
1693 |
|
|
jtag_state_e2dr : out std_logic;
|
1694 |
|
|
jtag_state_udr : out std_logic;
|
1695 |
|
|
jtag_state_sirs : out std_logic;
|
1696 |
|
|
jtag_state_cir : out std_logic;
|
1697 |
|
|
jtag_state_sir : out std_logic;
|
1698 |
|
|
jtag_state_e1ir : out std_logic;
|
1699 |
|
|
jtag_state_pir : out std_logic;
|
1700 |
|
|
jtag_state_e2ir : out std_logic;
|
1701 |
|
|
jtag_state_uir : out std_logic;
|
1702 |
|
|
tms : out std_logic);
|
1703 |
|
|
end component;
|
1704 |
|
|
|
1705 |
|
|
|
1706 |
|
|
component altera_std_synchronizer
|
1707 |
|
|
generic
|
1708 |
|
|
(
|
1709 |
|
|
depth : integer := 3
|
1710 |
|
|
);
|
1711 |
|
|
|
1712 |
|
|
port
|
1713 |
|
|
(
|
1714 |
|
|
clk : in std_logic;
|
1715 |
|
|
reset_n : in std_logic;
|
1716 |
|
|
din : in std_logic;
|
1717 |
|
|
dout : out std_logic
|
1718 |
|
|
);
|
1719 |
|
|
end component;
|
1720 |
|
|
|
1721 |
|
|
component altera_std_synchronizer_bundle
|
1722 |
|
|
generic
|
1723 |
|
|
(
|
1724 |
|
|
depth : integer := 3;
|
1725 |
|
|
width : integer := 1
|
1726 |
|
|
);
|
1727 |
|
|
|
1728 |
|
|
port
|
1729 |
|
|
(
|
1730 |
|
|
clk : in std_logic;
|
1731 |
|
|
reset_n : in std_logic;
|
1732 |
|
|
din : in std_logic_vector(width-1 downto 0);
|
1733 |
|
|
dout : out std_logic_vector(width-1 downto 0)
|
1734 |
|
|
);
|
1735 |
|
|
end component;
|
1736 |
|
|
|
1737 |
|
|
component alt_cal
|
1738 |
|
|
generic (
|
1739 |
|
|
number_of_channels : integer := 1;
|
1740 |
|
|
channel_address_width : integer := 1;
|
1741 |
|
|
sim_model_mode : string := "TRUE";
|
1742 |
|
|
lpm_hint : string := "UNUSED";
|
1743 |
|
|
lpm_type : string := "alt_cal"
|
1744 |
|
|
);
|
1745 |
|
|
PORT
|
1746 |
|
|
(
|
1747 |
|
|
busy : OUT STD_LOGIC;
|
1748 |
|
|
cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
1749 |
|
|
clock : IN STD_LOGIC;
|
1750 |
|
|
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1751 |
|
|
dprio_busy : IN STD_LOGIC;
|
1752 |
|
|
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1753 |
|
|
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1754 |
|
|
dprio_rden : OUT STD_LOGIC;
|
1755 |
|
|
dprio_wren : OUT STD_LOGIC;
|
1756 |
|
|
quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
|
1757 |
|
|
remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');
|
1758 |
|
|
reset : IN STD_LOGIC := '0';
|
1759 |
|
|
retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
1760 |
|
|
start : IN STD_LOGIC := '0';
|
1761 |
|
|
testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
|
1762 |
|
|
);
|
1763 |
|
|
end component;
|
1764 |
|
|
|
1765 |
|
|
component alt_cal_av
|
1766 |
|
|
generic (
|
1767 |
|
|
number_of_channels : integer := 1;
|
1768 |
|
|
channel_address_width : integer := 1;
|
1769 |
|
|
sim_model_mode : string := "TRUE";
|
1770 |
|
|
lpm_hint : string := "UNUSED";
|
1771 |
|
|
lpm_type : string := "alt_cal";
|
1772 |
|
|
sample_length : integer := 100;
|
1773 |
|
|
pma_base_address : integer := 0
|
1774 |
|
|
);
|
1775 |
|
|
PORT
|
1776 |
|
|
(
|
1777 |
|
|
busy : OUT STD_LOGIC;
|
1778 |
|
|
clock : IN STD_LOGIC;
|
1779 |
|
|
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1780 |
|
|
dprio_busy : IN STD_LOGIC;
|
1781 |
|
|
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1782 |
|
|
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1783 |
|
|
dprio_rden : OUT STD_LOGIC;
|
1784 |
|
|
dprio_wren : OUT STD_LOGIC;
|
1785 |
|
|
quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
|
1786 |
|
|
remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
|
1787 |
|
|
reset : IN STD_LOGIC := '0';
|
1788 |
|
|
start : IN STD_LOGIC := '0';
|
1789 |
|
|
testbuses : IN STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0')
|
1790 |
|
|
);
|
1791 |
|
|
end component;
|
1792 |
|
|
|
1793 |
|
|
component alt_cal_c3gxb
|
1794 |
|
|
generic (
|
1795 |
|
|
number_of_channels : integer := 1;
|
1796 |
|
|
channel_address_width : integer := 1;
|
1797 |
|
|
sim_model_mode : string := "TRUE";
|
1798 |
|
|
lpm_hint : string := "UNUSED";
|
1799 |
|
|
lpm_type : string := "alt_cal_c3gxb"
|
1800 |
|
|
);
|
1801 |
|
|
PORT
|
1802 |
|
|
(
|
1803 |
|
|
busy : OUT STD_LOGIC;
|
1804 |
|
|
cal_error : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
1805 |
|
|
clock : IN STD_LOGIC;
|
1806 |
|
|
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1807 |
|
|
dprio_busy : IN STD_LOGIC;
|
1808 |
|
|
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1809 |
|
|
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1810 |
|
|
dprio_rden : OUT STD_LOGIC;
|
1811 |
|
|
dprio_wren : OUT STD_LOGIC;
|
1812 |
|
|
quad_addr : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
|
1813 |
|
|
remap_addr : IN STD_LOGIC_VECTOR (9 DOWNTO 0) := (OTHERS => '0');
|
1814 |
|
|
reset : IN STD_LOGIC := '0';
|
1815 |
|
|
retain_addr : OUT STD_LOGIC_VECTOR (0 DOWNTO 0);
|
1816 |
|
|
start : IN STD_LOGIC := '0';
|
1817 |
|
|
testbuses : IN STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
|
1818 |
|
|
);
|
1819 |
|
|
end component;
|
1820 |
|
|
|
1821 |
|
|
component alt_cal_mm
|
1822 |
|
|
generic (
|
1823 |
|
|
number_of_channels : integer := 1;
|
1824 |
|
|
channel_address_width : integer := 1;
|
1825 |
|
|
sim_model_mode : string := "TRUE";
|
1826 |
|
|
CAL_PD_WR : string := "00101";
|
1827 |
|
|
CAL_RX_RD : string := "00110";
|
1828 |
|
|
CAL_RX_WR : string := "00111";
|
1829 |
|
|
CH_ADV : string := "01100";
|
1830 |
|
|
CH_WAIT : string := "00001";
|
1831 |
|
|
DPRIO_READ : string := "01110";
|
1832 |
|
|
DPRIO_WAIT : string := "01000";
|
1833 |
|
|
DPRIO_WRITE : string := "01111";
|
1834 |
|
|
IDLE : string := "00000";
|
1835 |
|
|
KICK_DELAY_OC : integer := 10010;
|
1836 |
|
|
KICK_PAUSE : integer := 10001;
|
1837 |
|
|
KICK_START_RD : string := "01101";
|
1838 |
|
|
KICK_START_WR : integer := 10000;
|
1839 |
|
|
OFFSETS_PDEN_RD : string := "00011";
|
1840 |
|
|
OFFSETS_PDEN_WR : string := "00100";
|
1841 |
|
|
sample_length : string := "01100100";
|
1842 |
|
|
SAMPLE_TB : string := "01001";
|
1843 |
|
|
TEST_INPUT : string := "01010";
|
1844 |
|
|
TESTBUS_SET : string := "00010";
|
1845 |
|
|
lpm_hint : string := "UNUSED";
|
1846 |
|
|
lpm_type : string := "alt_cal_mm"
|
1847 |
|
|
);
|
1848 |
|
|
PORT
|
1849 |
|
|
(
|
1850 |
|
|
busy : OUT STD_LOGIC;
|
1851 |
|
|
cal_error : OUT STD_LOGIC_VECTOR (number_of_channels - 1 DOWNTO 0);
|
1852 |
|
|
clock : IN STD_LOGIC;
|
1853 |
|
|
dprio_addr : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1854 |
|
|
dprio_busy : IN STD_LOGIC;
|
1855 |
|
|
dprio_datain : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1856 |
|
|
dprio_dataout : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
|
1857 |
|
|
dprio_rden : OUT STD_LOGIC;
|
1858 |
|
|
dprio_wren : OUT STD_LOGIC;
|
1859 |
|
|
quad_addr : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
|
1860 |
|
|
remap_addr : IN STD_LOGIC_VECTOR (11 DOWNTO 0) := (OTHERS => '0');
|
1861 |
|
|
reset : IN STD_LOGIC := '0';
|
1862 |
|
|
retain_addr : OUT STD_LOGIC;
|
1863 |
|
|
start : IN STD_LOGIC := '0';
|
1864 |
|
|
transceiver_init : IN STD_LOGIC := '0';
|
1865 |
|
|
testbuses : IN STD_LOGIC_VECTOR (4 * number_of_channels - 1 DOWNTO 0) := (OTHERS => '0')
|
1866 |
|
|
);
|
1867 |
|
|
END component;
|
1868 |
|
|
|
1869 |
|
|
|
1870 |
|
|
|
1871 |
|
|
|
1872 |
|
|
|
1873 |
|
|
|
1874 |
|
|
|
1875 |
|
|
constant SLD_IR_BITS : natural := 10;
|
1876 |
|
|
|
1877 |
|
|
component sld_signaltap
|
1878 |
|
|
generic (
|
1879 |
|
|
SLD_USE_JTAG_SIGNAL_ADAPTER : natural := 1;
|
1880 |
|
|
SLD_CURRENT_RESOURCE_WIDTH : natural := 0;
|
1881 |
|
|
SLD_INVERSION_MASK : std_logic_vector := "0";
|
1882 |
|
|
SLD_POWER_UP_TRIGGER : natural := 0;
|
1883 |
|
|
SLD_ADVANCED_TRIGGER_6 : string := "NONE";
|
1884 |
|
|
SLD_ADVANCED_TRIGGER_9 : string := "NONE";
|
1885 |
|
|
SLD_RAM_PIPELINE : natural := 0;
|
1886 |
|
|
SLD_ADVANCED_TRIGGER_7 : string := "NONE";
|
1887 |
|
|
SLD_HPS_EVENT_ENABLED : natural := 0;
|
1888 |
|
|
SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY : string := "basic";
|
1889 |
|
|
SLD_STORAGE_QUALIFIER_GAP_RECORD : natural := 0;
|
1890 |
|
|
SLD_SECTION_ID : string := "hdl_signaltap_0";
|
1891 |
|
|
SLD_INCREMENTAL_ROUTING : natural := 0;
|
1892 |
|
|
SLD_STORAGE_QUALIFIER_PIPELINE : natural := 0;
|
1893 |
|
|
SLD_TRIGGER_IN_ENABLED : natural := 0;
|
1894 |
|
|
SLD_STATE_BITS : natural := 11;
|
1895 |
|
|
SLD_HPS_EVENT_ID : natural := 0;
|
1896 |
|
|
SLD_CREATE_MONITOR_INTERFACE : natural := 0;
|
1897 |
|
|
SLD_STATE_FLOW_USE_GENERATED : natural := 0;
|
1898 |
|
|
SLD_INVERSION_MASK_LENGTH : integer := 1;
|
1899 |
|
|
SLD_DATA_BITS : natural := 1;
|
1900 |
|
|
SLD_COUNTER_PIPELINE : natural := 0;
|
1901 |
|
|
SLD_BUFFER_FULL_STOP : natural := 1;
|
1902 |
|
|
SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH : natural := 0;
|
1903 |
|
|
SLD_ATTRIBUTE_MEM_MODE : string := "OFF";
|
1904 |
|
|
SLD_STORAGE_QUALIFIER_MODE : string := "OFF";
|
1905 |
|
|
SLD_STATE_FLOW_MGR_ENTITY : string := "state_flow_mgr_entity.vhd";
|
1906 |
|
|
SLD_HPS_TRIGGER_IN_ENABLED : natural := 0;
|
1907 |
|
|
SLD_ADVANCED_TRIGGER_5 : string := "NONE";
|
1908 |
|
|
SLD_NODE_CRC_LOWORD : natural := 50132;
|
1909 |
|
|
SLD_TRIGGER_BITS : natural := 1;
|
1910 |
|
|
SLD_STORAGE_QUALIFIER_BITS : natural := 1;
|
1911 |
|
|
SLD_TRIGGER_PIPELINE : natural := 0;
|
1912 |
|
|
SLD_HPS_TRIGGER_OUT_ENABLED : natural := 0;
|
1913 |
|
|
SLD_ADVANCED_TRIGGER_10 : string := "NONE";
|
1914 |
|
|
SLD_MEM_ADDRESS_BITS : natural := 7;
|
1915 |
|
|
SLD_ADVANCED_TRIGGER_ENTITY : string := "basic";
|
1916 |
|
|
SLD_ADVANCED_TRIGGER_4 : string := "NONE";
|
1917 |
|
|
SLD_ADVANCED_TRIGGER_8 : string := "NONE";
|
1918 |
|
|
SLD_TRIGGER_LEVEL : natural := 10;
|
1919 |
|
|
SLD_RAM_BLOCK_TYPE : string := "AUTO";
|
1920 |
|
|
SLD_ADVANCED_TRIGGER_2 : string := "NONE";
|
1921 |
|
|
SLD_ADVANCED_TRIGGER_1 : string := "NONE";
|
1922 |
|
|
SLD_DATA_BIT_CNTR_BITS : natural := 4;
|
1923 |
|
|
SLD_SAMPLE_DEPTH : natural := 16;
|
1924 |
|
|
lpm_type : string := "sld_signaltap";
|
1925 |
|
|
SLD_NODE_CRC_BITS : natural := 32;
|
1926 |
|
|
SLD_ENABLE_ADVANCED_TRIGGER : natural := 0;
|
1927 |
|
|
SLD_SEGMENT_SIZE : natural := 0;
|
1928 |
|
|
SLD_NODE_INFO : natural := 0;
|
1929 |
|
|
SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION : natural := 0;
|
1930 |
|
|
SLD_NODE_CRC_HIWORD : natural := 41394;
|
1931 |
|
|
SLD_TRIGGER_LEVEL_PIPELINE : natural := 1;
|
1932 |
|
|
SLD_ADVANCED_TRIGGER_3 : string := "NONE"
|
1933 |
|
|
);
|
1934 |
|
|
port (
|
1935 |
|
|
jtag_state_sdr : in std_logic := '0';
|
1936 |
|
|
ir_in : in std_logic_vector(SLD_IR_BITS-1 downto 0) := (others => '0');
|
1937 |
|
|
acq_trigger_out : out std_logic_vector(SLD_TRIGGER_BITS-1 downto 0);
|
1938 |
|
|
gnd : out std_logic;
|
1939 |
|
|
jtag_state_cir : in std_logic := '0';
|
1940 |
|
|
jtag_state_e2ir : in std_logic := '0';
|
1941 |
|
|
jtag_state_pir : in std_logic := '0';
|
1942 |
|
|
jtag_state_udr : in std_logic := '0';
|
1943 |
|
|
vcc : out std_logic;
|
1944 |
|
|
jtag_state_e1dr : in std_logic := '0';
|
1945 |
|
|
jtag_state_rti : in std_logic := '0';
|
1946 |
|
|
jtag_state_e1ir : in std_logic := '0';
|
1947 |
|
|
jtag_state_pdr : in std_logic := '0';
|
1948 |
|
|
acq_clk : in std_logic;
|
1949 |
|
|
clr : in std_logic := '0';
|
1950 |
|
|
trigger_in : in std_logic := '0';
|
1951 |
|
|
ir_out : out std_logic_vector(SLD_IR_BITS-1 downto 0);
|
1952 |
|
|
jtag_state_sirs : in std_logic := '0';
|
1953 |
|
|
jtag_state_cdr : in std_logic := '0';
|
1954 |
|
|
jtag_state_sir : in std_logic := '0';
|
1955 |
|
|
jtag_state_e2dr : in std_logic := '0';
|
1956 |
|
|
tms : in std_logic := '0';
|
1957 |
|
|
jtag_state_tlr : in std_logic := '0';
|
1958 |
|
|
jtag_state_sdrs : in std_logic := '0';
|
1959 |
|
|
tdi : in std_logic := '0';
|
1960 |
|
|
jtag_state_uir : in std_logic := '0';
|
1961 |
|
|
acq_trigger_in : in std_logic_vector(SLD_TRIGGER_BITS-1 downto 0) := (others => '0');
|
1962 |
|
|
trigger_out : out std_logic;
|
1963 |
|
|
storage_enable : in std_logic := '0';
|
1964 |
|
|
acq_data_out : out std_logic_vector(SLD_DATA_BITS-1 downto 0);
|
1965 |
|
|
acq_storage_qualifier_in : in std_logic_vector(SLD_STORAGE_QUALIFIER_BITS-1 downto 0) := (others => '0');
|
1966 |
|
|
acq_data_in : in std_logic_vector(SLD_DATA_BITS-1 downto 0) := (others => '0');
|
1967 |
|
|
vir_tdi : in std_logic := '0';
|
1968 |
|
|
tdo : out std_logic;
|
1969 |
|
|
crc : in std_logic_vector(SLD_NODE_CRC_BITS-1 downto 0) := (others => '0');
|
1970 |
|
|
clrn : in std_logic := '0';
|
1971 |
|
|
raw_tck : in std_logic := '0';
|
1972 |
|
|
irq : out std_logic;
|
1973 |
|
|
usr1 : in std_logic := '0';
|
1974 |
|
|
ena : in std_logic := '0'
|
1975 |
|
|
);
|
1976 |
|
|
end component; --sld_signaltap
|
1977 |
|
|
|
1978 |
|
|
|
1979 |
|
|
component altstratixii_oct
|
1980 |
|
|
generic (
|
1981 |
|
|
lpm_type : string := "altstratixii_oct"
|
1982 |
|
|
);
|
1983 |
|
|
port (
|
1984 |
|
|
terminationenable : in std_logic;
|
1985 |
|
|
terminationclock : in std_logic;
|
1986 |
|
|
rdn : in std_logic;
|
1987 |
|
|
rup : in std_logic
|
1988 |
|
|
);
|
1989 |
|
|
end component; --altstratixii_oct
|
1990 |
|
|
|
1991 |
|
|
constant PFL_QUAD_IO_FLASH_IR_BITS : NATURAL := 8;
|
1992 |
|
|
constant PFL_CFI_FLASH_IR_BITS : NATURAL := 5;
|
1993 |
|
|
constant PFL_NAND_FLASH_IR_BITS : NATURAL := 4;
|
1994 |
|
|
constant N_FLASH_BITS : NATURAL := 4;
|
1995 |
|
|
|
1996 |
|
|
component altparallel_flash_loader
|
1997 |
|
|
generic (
|
1998 |
|
|
FLASH_STATIC_WAIT_WIDTH : NATURAL := 15;
|
1999 |
|
|
EXTRA_ADDR_BYTE : NATURAL := 0;
|
2000 |
|
|
FEATURES_CFG : NATURAL := 1;
|
2001 |
|
|
PAGE_CLK_DIVISOR : NATURAL := 1;
|
2002 |
|
|
BURST_MODE_SPANSION : NATURAL := 0;
|
2003 |
|
|
ENHANCED_FLASH_PROGRAMMING : NATURAL := 0;
|
2004 |
|
|
FLASH_ECC_CHECKBOX : NATURAL := 0;
|
2005 |
|
|
FLASH_NRESET_COUNTER : NATURAL := 1;
|
2006 |
|
|
PAGE_MODE : NATURAL := 0;
|
2007 |
|
|
NRB_ADDR : NATURAL := 65667072;
|
2008 |
|
|
BURST_MODE : NATURAL := 0;
|
2009 |
|
|
SAFE_MODE_REVERT_ADDR : NATURAL := 0;
|
2010 |
|
|
US_UNIT_COUNTER : NATURAL := 1;
|
2011 |
|
|
FIFO_SIZE : NATURAL := 16;
|
2012 |
|
|
CONF_DATA_WIDTH : NATURAL := 1;
|
2013 |
|
|
CONF_WAIT_TIMER_WIDTH : NATURAL := 16;
|
2014 |
|
|
NFLASH_MFC : STRING := "NUMONYX";
|
2015 |
|
|
OPTION_BITS_START_ADDRESS : NATURAL := 0;
|
2016 |
|
|
SAFE_MODE_RETRY : NATURAL := 1;
|
2017 |
|
|
DCLK_DIVISOR : NATURAL := 1;
|
2018 |
|
|
FLASH_TYPE : STRING := "CFI_FLASH";
|
2019 |
|
|
N_FLASH : NATURAL := 1;
|
2020 |
|
|
BURST_MODE_LATENCY_COUNT : NATURAL := 4;
|
2021 |
|
|
QSPI_DATA_DELAY : NATURAL := 0;
|
2022 |
|
|
FLASH_BURST_EXTRA_CYCLE : NATURAL := 0;
|
2023 |
|
|
TRISTATE_CHECKBOX : NATURAL := 0;
|
2024 |
|
|
QFLASH_MFC : STRING := "ALTERA";
|
2025 |
|
|
FEATURES_PGM : NATURAL := 1;
|
2026 |
|
|
QFLASH_FAST_SPEED : NATURAL := 0;
|
2027 |
|
|
DISABLE_CRC_CHECKBOX : NATURAL := 0;
|
2028 |
|
|
FLASH_DATA_WIDTH : NATURAL := 16;
|
2029 |
|
|
RSU_WATCHDOG_COUNTER : NATURAL := 100000000;
|
2030 |
|
|
PFL_RSU_WATCHDOG_ENABLED : NATURAL := 0;
|
2031 |
|
|
MT28EW_PAGE_MODE : NATURAL := 0;
|
2032 |
|
|
SAFE_MODE_HALT : NATURAL := 0;
|
2033 |
|
|
ADDR_WIDTH : NATURAL := 20;
|
2034 |
|
|
NAND_SIZE : NATURAL := 67108864;
|
2035 |
|
|
NORMAL_MODE : NATURAL := 1;
|
2036 |
|
|
FLASH_NRESET_CHECKBOX : NATURAL := 0;
|
2037 |
|
|
SAFE_MODE_REVERT : NATURAL := 0;
|
2038 |
|
|
LPM_TYPE : STRING := "ALTPARALLEL_FLASH_LOADER";
|
2039 |
|
|
AUTO_RESTART : STRING := "OFF";
|
2040 |
|
|
DCLK_CREATE_DELAY : NATURAL := 0;
|
2041 |
|
|
CLK_DIVISOR : NATURAL := 1;
|
2042 |
|
|
BURST_MODE_INTEL : NATURAL := 0;
|
2043 |
|
|
BURST_MODE_NUMONYX : NATURAL := 0;
|
2044 |
|
|
DECOMPRESSOR_MODE : STRING := "NONE";
|
2045 |
|
|
QSPI_DATA_DELAY_COUNT : NATURAL := 1
|
2046 |
|
|
);
|
2047 |
|
|
port (
|
2048 |
|
|
flash_nce : out std_logic_vector(N_FLASH-1 downto 0);
|
2049 |
|
|
fpga_data : out std_logic_vector(CONF_DATA_WIDTH-1 downto 0);
|
2050 |
|
|
fpga_dclk : out std_logic;
|
2051 |
|
|
fpga_nstatus : in std_logic := '0';
|
2052 |
|
|
flash_ale : out std_logic;
|
2053 |
|
|
pfl_clk : in std_logic := '0';
|
2054 |
|
|
fpga_nconfig : out std_logic;
|
2055 |
|
|
flash_io2 : inout std_logic_vector(N_FLASH-1 downto 0);
|
2056 |
|
|
flash_sck : out std_logic_vector(N_FLASH-1 downto 0);
|
2057 |
|
|
flash_noe : out std_logic;
|
2058 |
|
|
flash_nwe : out std_logic;
|
2059 |
|
|
pfl_watchdog_error : out std_logic;
|
2060 |
|
|
pfl_reset_watchdog : in std_logic := '0';
|
2061 |
|
|
fpga_conf_done : in std_logic := '0';
|
2062 |
|
|
flash_rdy : in std_logic := '1';
|
2063 |
|
|
pfl_flash_access_granted : in std_logic := '0';
|
2064 |
|
|
pfl_nreconfigure : in std_logic := '1';
|
2065 |
|
|
flash_cle : out std_logic;
|
2066 |
|
|
flash_nreset : out std_logic;
|
2067 |
|
|
flash_io0 : inout std_logic_vector(N_FLASH-1 downto 0);
|
2068 |
|
|
pfl_nreset : in std_logic := '0';
|
2069 |
|
|
flash_data : inout std_logic_vector(FLASH_DATA_WIDTH-1 downto 0);
|
2070 |
|
|
flash_io1 : inout std_logic_vector(N_FLASH-1 downto 0);
|
2071 |
|
|
flash_nadv : out std_logic;
|
2072 |
|
|
flash_clk : out std_logic;
|
2073 |
|
|
flash_io3 : inout std_logic_vector(N_FLASH-1 downto 0);
|
2074 |
|
|
flash_io : inout std_logic_vector(7 downto 0);
|
2075 |
|
|
flash_addr : out std_logic_vector(ADDR_WIDTH-1 downto 0);
|
2076 |
|
|
pfl_flash_access_request : out std_logic;
|
2077 |
|
|
flash_ncs : out std_logic_vector(N_FLASH-1 downto 0);
|
2078 |
|
|
fpga_pgm : in std_logic_vector(2 downto 0) := (others => '0')
|
2079 |
|
|
);
|
2080 |
|
|
end component; --altparallel_flash_loader
|
2081 |
|
|
|
2082 |
|
|
|
2083 |
|
|
component altserial_flash_loader
|
2084 |
|
|
generic (
|
2085 |
|
|
lpm_hint : STRING := "UNUSED";
|
2086 |
|
|
enhanced_mode : natural := 0;
|
2087 |
|
|
intended_device_family : STRING := "Cyclone";
|
2088 |
|
|
enable_shared_access : STRING := "OFF";
|
2089 |
|
|
enable_quad_spi_support : natural := 0;
|
2090 |
|
|
ncso_width : natural := 1;
|
2091 |
|
|
lpm_type : STRING := "ALTSERIAL_FLASH_LOADER"
|
2092 |
|
|
);
|
2093 |
|
|
port (
|
2094 |
|
|
data_in : in std_logic_vector(3 downto 0) := (others => '0');
|
2095 |
|
|
noe : in std_logic := '0';
|
2096 |
|
|
asmi_access_granted : in std_logic := '1';
|
2097 |
|
|
data_out : out std_logic_vector(3 downto 0);
|
2098 |
|
|
data_oe : in std_logic_vector(3 downto 0) := (others => '0');
|
2099 |
|
|
sdoin : in std_logic := '0';
|
2100 |
|
|
asmi_access_request : out std_logic;
|
2101 |
|
|
data0out : out std_logic;
|
2102 |
|
|
scein : in std_logic_vector(ncso_width-1 downto 0) := (others => '0');
|
2103 |
|
|
dclkin : in std_logic := '0'
|
2104 |
|
|
);
|
2105 |
|
|
end component; --altserial_flash_loader
|
2106 |
|
|
|
2107 |
|
|
|
2108 |
|
|
component alt_fault_injection
|
2109 |
|
|
generic (
|
2110 |
|
|
CRC_OSC_DIVIDER : NATURAL := 8;
|
2111 |
|
|
ENABLE_EMR_SHARE : STRING := "NO";
|
2112 |
|
|
INTENDED_DEVICE_FAMILY : STRING := "Stratix V";
|
2113 |
|
|
TEST_LOGIC_TYPE : STRING := "OR";
|
2114 |
|
|
ENABLE_INTOSC_SHARE : STRING := "NO";
|
2115 |
|
|
EMR_WIDTH : NATURAL := 67;
|
2116 |
|
|
INIT_EMR : STRING := "NO";
|
2117 |
|
|
LPM_TYPE : STRING := "ALT_FAULT_INJECTION";
|
2118 |
|
|
EMR_ARRAY_SIZE : NATURAL := 128;
|
2119 |
|
|
INSTANTIATE_PR_BLOCK : NATURAL := 1;
|
2120 |
|
|
DATA_REG_WIDTH : NATURAL := 16
|
2121 |
|
|
);
|
2122 |
|
|
port (
|
2123 |
|
|
system_error : in std_logic := '0';
|
2124 |
|
|
pr_ready : in std_logic := '0';
|
2125 |
|
|
system_reset : out std_logic;
|
2126 |
|
|
pr_request : out std_logic;
|
2127 |
|
|
emr_data : in std_logic_vector(EMR_WIDTH-1 downto 0);
|
2128 |
|
|
error_scrubbed : out std_logic;
|
2129 |
|
|
user_intosc : out std_logic;
|
2130 |
|
|
pr_ext_request : in std_logic := '0';
|
2131 |
|
|
pr_error : in std_logic := '0';
|
2132 |
|
|
emr_valid : in std_logic;
|
2133 |
|
|
crc_error : in std_logic;
|
2134 |
|
|
error_injected : out std_logic;
|
2135 |
|
|
pr_data : out std_logic_vector(DATA_REG_WIDTH-1 downto 0);
|
2136 |
|
|
pr_clk : out std_logic;
|
2137 |
|
|
pr_done : in std_logic := '0'
|
2138 |
|
|
);
|
2139 |
|
|
end component; --alt_fault_injection
|
2140 |
|
|
|
2141 |
|
|
|
2142 |
|
|
component sld_virtual_jtag_basic
|
2143 |
|
|
generic (
|
2144 |
|
|
lpm_hint : string := "UNUSED";
|
2145 |
|
|
sld_sim_action : string := "UNUSED";
|
2146 |
|
|
sld_instance_index : natural := 0;
|
2147 |
|
|
sld_ir_width : natural := 1;
|
2148 |
|
|
sld_sim_n_scan : natural := 0;
|
2149 |
|
|
sld_mfg_id : natural := 0;
|
2150 |
|
|
sld_version : natural := 0;
|
2151 |
|
|
sld_type_id : natural := 0;
|
2152 |
|
|
lpm_type : string := "sld_virtual_jtag_basic";
|
2153 |
|
|
sld_auto_instance_index : string := "NO";
|
2154 |
|
|
sld_sim_total_length : natural := 0
|
2155 |
|
|
);
|
2156 |
|
|
port (
|
2157 |
|
|
jtag_state_sdr : out std_logic;
|
2158 |
|
|
jtag_state_sirs : out std_logic;
|
2159 |
|
|
ir_out : in std_logic_vector(sld_ir_width-1 downto 0);
|
2160 |
|
|
jtag_state_sir : out std_logic;
|
2161 |
|
|
jtag_state_cdr : out std_logic;
|
2162 |
|
|
jtag_state_e2dr : out std_logic;
|
2163 |
|
|
tms : out std_logic;
|
2164 |
|
|
jtag_state_sdrs : out std_logic;
|
2165 |
|
|
jtag_state_tlr : out std_logic;
|
2166 |
|
|
ir_in : out std_logic_vector(sld_ir_width-1 downto 0);
|
2167 |
|
|
virtual_state_sdr : out std_logic;
|
2168 |
|
|
tdi : out std_logic;
|
2169 |
|
|
jtag_state_uir : out std_logic;
|
2170 |
|
|
jtag_state_cir : out std_logic;
|
2171 |
|
|
virtual_state_cdr : out std_logic;
|
2172 |
|
|
virtual_state_uir : out std_logic;
|
2173 |
|
|
virtual_state_e2dr : out std_logic;
|
2174 |
|
|
jtag_state_e2ir : out std_logic;
|
2175 |
|
|
virtual_state_cir : out std_logic;
|
2176 |
|
|
jtag_state_pir : out std_logic;
|
2177 |
|
|
jtag_state_udr : out std_logic;
|
2178 |
|
|
virtual_state_udr : out std_logic;
|
2179 |
|
|
tdo : in std_logic;
|
2180 |
|
|
jtag_state_e1dr : out std_logic;
|
2181 |
|
|
jtag_state_rti : out std_logic;
|
2182 |
|
|
virtual_state_pdr : out std_logic;
|
2183 |
|
|
virtual_state_e1dr : out std_logic;
|
2184 |
|
|
jtag_state_e1ir : out std_logic;
|
2185 |
|
|
jtag_state_pdr : out std_logic;
|
2186 |
|
|
tck : out std_logic
|
2187 |
|
|
);
|
2188 |
|
|
end component; --sld_virtual_jtag_basic
|
2189 |
|
|
|
2190 |
|
|
|
2191 |
|
|
component altsource_probe
|
2192 |
|
|
generic (
|
2193 |
|
|
lpm_hint : string := "UNUSED";
|
2194 |
|
|
sld_instance_index : natural := 0;
|
2195 |
|
|
source_initial_value : string := "0";
|
2196 |
|
|
sld_ir_width : natural := 4;
|
2197 |
|
|
probe_width : natural := 1;
|
2198 |
|
|
source_width : natural := 1;
|
2199 |
|
|
instance_id : string := "UNUSED";
|
2200 |
|
|
lpm_type : string := "altsource_probe";
|
2201 |
|
|
sld_auto_instance_index : string := "YES";
|
2202 |
|
|
SLD_NODE_INFO : natural := 4746752;
|
2203 |
|
|
enable_metastability : string := "NO"
|
2204 |
|
|
);
|
2205 |
|
|
port (
|
2206 |
|
|
source_clk : in std_logic;
|
2207 |
|
|
probe : in std_logic_vector(probe_width-1 downto 0);
|
2208 |
|
|
source : out std_logic_vector(source_width-1 downto 0);
|
2209 |
|
|
source_ena : in std_logic
|
2210 |
|
|
);
|
2211 |
|
|
end component; --altsource_probe
|
2212 |
|
|
|
2213 |
|
|
end altera_mf_components;
|