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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2014
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib, common_components_lib, common_ram_lib, technology_lib, tech_ram_lib;
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USE IEEE.std_logic_1164.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_ram_lib.common_ram_pkg.ALL;
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USE technology_lib.technology_select_pkg.ALL;
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ENTITY common_ram_crw_crw_ratio IS
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GENERIC (
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g_technology : NATURAL := c_tech_select_default;
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g_ram_a : t_c_mem := c_mem_ram; -- settings for port a
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g_ram_b : t_c_mem := c_mem_ram; -- data width and address range for port b
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g_init_file : STRING := "UNUSED"
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);
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PORT (
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rst_a : IN STD_LOGIC := '0';
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rst_b : IN STD_LOGIC := '0';
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clk_a : IN STD_LOGIC;
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clk_b : IN STD_LOGIC;
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clken_a : IN STD_LOGIC := '1';
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clken_b : IN STD_LOGIC := '1';
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wr_en_a : IN STD_LOGIC := '0';
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wr_en_b : IN STD_LOGIC := '0';
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wr_dat_a : IN STD_LOGIC_VECTOR(g_ram_a.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
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wr_dat_b : IN STD_LOGIC_VECTOR(g_ram_b.dat_w-1 DOWNTO 0) := (OTHERS=>'0');
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adr_a : IN STD_LOGIC_VECTOR(g_ram_a.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
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adr_b : IN STD_LOGIC_VECTOR(g_ram_b.adr_w-1 DOWNTO 0) := (OTHERS=>'0');
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rd_en_a : IN STD_LOGIC := '1';
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rd_en_b : IN STD_LOGIC := '1';
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rd_dat_a : OUT STD_LOGIC_VECTOR(g_ram_a.dat_w-1 DOWNTO 0);
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rd_dat_b : OUT STD_LOGIC_VECTOR(g_ram_b.dat_w-1 DOWNTO 0);
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rd_val_a : OUT STD_LOGIC;
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rd_val_b : OUT STD_LOGIC
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);
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END common_ram_crw_crw_ratio;
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ARCHITECTURE str OF common_ram_crw_crw_ratio IS
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CONSTANT c_ram : t_c_mem := g_ram_a; -- use shared parameters from port a parameter
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CONSTANT c_rd_latency : NATURAL := sel_a_b(c_ram.latency<2, c_ram.latency, 2); -- handle read latency 1 or 2 in RAM
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CONSTANT c_pipeline : NATURAL := sel_a_b(c_ram.latency>c_rd_latency, c_ram.latency-c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
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-- Intermediate signal for extra pipelining
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SIGNAL ram_rd_dat_a : STD_LOGIC_VECTOR(rd_dat_a'RANGE);
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SIGNAL ram_rd_dat_b : STD_LOGIC_VECTOR(rd_dat_b'RANGE);
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-- Map sl to single bit slv for rd_val pipelining
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SIGNAL ram_rd_en_a : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL ram_rd_en_b : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL ram_rd_val_a : STD_LOGIC_VECTOR(0 DOWNTO 0);
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SIGNAL ram_rd_val_b : STD_LOGIC_VECTOR(0 DOWNTO 0);
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BEGIN
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ASSERT c_ram.latency >= 1
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REPORT "common_ram_crw_crw_ratio : only support read latency >= 1"
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SEVERITY FAILURE;
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ASSERT g_ram_a.latency = g_ram_b.latency
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REPORT "common_ram_crw_crw_ratio : only support same read latency for both ports"
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SEVERITY FAILURE;
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-- memory access
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u_ramk : ENTITY tech_ram_lib.tech_memory_ram_crwk_crw
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GENERIC MAP (
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g_technology => g_technology,
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g_adr_a_w => g_ram_a.adr_w,
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g_adr_b_w => g_ram_b.adr_w,
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g_dat_a_w => g_ram_a.dat_w,
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g_dat_b_w => g_ram_b.dat_w,
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g_nof_words_a => g_ram_a.nof_dat,
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g_nof_words_b => g_ram_b.nof_dat,
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g_rd_latency => c_rd_latency,
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g_init_file => g_init_file
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)
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PORT MAP (
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clock_a => clk_a,
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clock_b => clk_b,
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enable_a => clken_a,
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enable_b => clken_b,
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wren_a => wr_en_a,
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wren_b => wr_en_b,
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data_a => wr_dat_a,
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data_b => wr_dat_b,
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address_a => adr_a,
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address_b => adr_b,
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q_a => ram_rd_dat_a,
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q_b => ram_rd_dat_b
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);
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-- read output
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u_pipe_a : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_pipeline => c_pipeline,
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g_in_dat_w => g_ram_a.dat_w,
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g_out_dat_w => g_ram_a.dat_w
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)
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PORT MAP (
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clk => clk_a,
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clken => clken_a,
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in_dat => ram_rd_dat_a,
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out_dat => rd_dat_a
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);
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u_pipe_b : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_pipeline => c_pipeline,
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g_in_dat_w => g_ram_b.dat_w,
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g_out_dat_w => g_ram_b.dat_w
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)
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PORT MAP (
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clk => clk_b,
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clken => clken_b,
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in_dat => ram_rd_dat_b,
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out_dat => rd_dat_b
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);
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-- rd_val control
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ram_rd_en_a(0) <= rd_en_a;
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ram_rd_en_b(0) <= rd_en_b;
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rd_val_a <= ram_rd_val_a(0);
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rd_val_b <= ram_rd_val_b(0);
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u_rd_val_a : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_pipeline => c_ram.latency,
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g_in_dat_w => 1,
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g_out_dat_w => 1
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)
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PORT MAP (
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clk => clk_a,
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clken => clken_a,
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in_dat => ram_rd_en_a,
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out_dat => ram_rd_val_a
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);
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u_rd_val_b : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_pipeline => c_ram.latency,
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g_in_dat_w => 1,
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g_out_dat_w => 1
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)
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PORT MAP (
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clk => clk_b,
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clken => clken_b,
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in_dat => ram_rd_en_b,
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out_dat => ram_rd_val_b
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);
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END str;
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