Subversion Repositories astron_ram

-- megafunction wizard: %RAM: 2-PORT%

-- GENERATION: STANDARD

-- VERSION: WM1.0

-- MODULE: altsyncram 

-- ============================================================

-- File Name: ip_stratixiv_ram_cr_cw.vhd

-- Megafunction Name(s):

--      altsyncram

--

-- Simulation Library Files(s):

--      altera_mf

-- ============================================================

-- ************************************************************

-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

--

-- 11.1 Build 259 01/25/2012 SP 2 SJ Full Version

-- ************************************************************

--Copyright (C) 1991-2011 Altera Corporation

--Your use of Altera Corporation's design tools, logic functions 

--and other software and tools, and its AMPP partner logic 

--functions, and any output files from any of the foregoing 

--(including device programming or simulation files), and any 

--associated documentation or information are expressly subject 

--to the terms and conditions of the Altera Program License 

--Subscription Agreement, Altera MegaCore Function License 

--Agreement, or other applicable license agreement, including, 

--without limitation, that your use is for the sole purpose of 

--programming logic devices manufactured by Altera and sold by 

--Altera or its authorized distributors.  Please refer to the 

--applicable agreement for further details.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

LIBRARY altera_mf;

USE altera_mf.all;

LIBRARY technology_lib;

USE technology_lib.technology_pkg.ALL;

ENTITY ip_stratixiv_ram_cr_cw IS

  GENERIC (

    g_adr_w      : NATURAL := 5;

    g_dat_w      : NATURAL := 8;

    g_nof_words  : NATURAL := 2**5;

    g_rd_latency : NATURAL := 2;  -- choose 1 or 2

    g_init_file  : STRING  := "UNUSED"

  );

  PORT

  (

    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);

    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);

    rdclock   : IN  STD_LOGIC ;

    rdclocken : IN  STD_LOGIC  := '1';

    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);

    wrclock   : IN  STD_LOGIC  := '1';

    wrclocken : IN  STD_LOGIC  := '1';

    wren      : IN  STD_LOGIC  := '0';

    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)

  );

END ip_stratixiv_ram_cr_cw;

ARCHITECTURE SYN OF ip_stratixiv_ram_cr_cw IS

  CONSTANT c_outdata_reg_b : STRING := tech_sel_a_b(g_rd_latency=1, "UNREGISTERED", "CLOCK1");

  SIGNAL sub_wire0  : STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);

  COMPONENT altsyncram

  GENERIC (

    address_aclr_b    : STRING;

    address_reg_b   : STRING;

    clock_enable_input_a    : STRING;

    clock_enable_input_b    : STRING;

    clock_enable_output_b   : STRING;

    intended_device_family    : STRING;

    lpm_type    : STRING;

    numwords_a    : NATURAL;

    numwords_b    : NATURAL;

    operation_mode    : STRING;

    outdata_aclr_b    : STRING;

    outdata_reg_b   : STRING;

    power_up_uninitialized    : STRING;

    widthad_a   : NATURAL;

    widthad_b   : NATURAL;

    width_a   : NATURAL;

    width_b   : NATURAL;

    width_byteena_a   : NATURAL

  );

  PORT (

      clock0    : IN  STD_LOGIC ;

      clocken1  : IN  STD_LOGIC ;

      wren_a    : IN  STD_LOGIC ;

      address_b : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);

      clock1    : IN  STD_LOGIC ;

      clocken0  : IN  STD_LOGIC ;

      address_a : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);

      data_a    : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);

      q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)

  );

  END COMPONENT;

BEGIN

  q    <= sub_wire0(g_dat_w-1 DOWNTO 0);

  altsyncram_component : altsyncram

  GENERIC MAP (

    address_aclr_b => "NONE",

    address_reg_b => "CLOCK1",

    clock_enable_input_a => "NORMAL",

    clock_enable_input_b => "NORMAL",

    clock_enable_output_b => "NORMAL",

    intended_device_family => "Stratix IV",

    lpm_type => "altsyncram",

    numwords_a => g_nof_words,

    numwords_b => g_nof_words,

    operation_mode => "DUAL_PORT",

    outdata_aclr_b => "NONE",

    outdata_reg_b => c_outdata_reg_b,

    power_up_uninitialized => "FALSE",

    widthad_a => g_adr_w,

    widthad_b => g_adr_w,

    width_a => g_dat_w,

    width_b => g_dat_w,

    width_byteena_a => 1

  )

  PORT MAP (

    clock0 => wrclock,

    clocken1 => rdclocken,

    wren_a => wren,

    address_b => rdaddress,

    clock1 => rdclock,

    clocken0 => wrclocken,

    address_a => wraddress,

    data_a => data,

    q_b => sub_wire0

  );

END SYN;

-- ============================================================

-- CNX file retrieval info

-- ============================================================

-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"

-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"

-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"

-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "1"

-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "1"

-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"

-- Retrieval info: PRIVATE: CLRq NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"

-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"

-- Retrieval info: PRIVATE: Clock NUMERIC "1"

-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"

-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"

-- Retrieval info: PRIVATE: ECC NUMERIC "0"

-- Retrieval info: PRIVATE: ECC_PIPELINE_STAGE NUMERIC "0"

-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"

-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"

-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"

-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"

-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"

-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"

-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"

-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"

-- Retrieval info: PRIVATE: MIFfilename STRING "fft_3n1024sin.hex"

-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"

-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"

-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"

-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"

-- Retrieval info: PRIVATE: REGdata NUMERIC "1"

-- Retrieval info: PRIVATE: REGq NUMERIC "1"

-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGrren NUMERIC "1"

-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"

-- Retrieval info: PRIVATE: REGwren NUMERIC "1"

-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"

-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"

-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"

-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"

-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"

-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"

-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"

-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"

-- Retrieval info: PRIVATE: enable NUMERIC "1"

-- Retrieval info: PRIVATE: rden NUMERIC "0"

-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

-- Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"

-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "NORMAL"

-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "NORMAL"

-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"

-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"

-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"

-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "32"

-- Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"

-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"

-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "CLOCK1"

-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"

-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"

-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "5"

-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"

-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"

-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"

-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"

-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"

-- Retrieval info: USED_PORT: rdaddress 0 0 5 0 INPUT NODEFVAL "rdaddress[4..0]"

-- Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL "rdclock"

-- Retrieval info: USED_PORT: rdclocken 0 0 0 0 INPUT VCC "rdclocken"

-- Retrieval info: USED_PORT: wraddress 0 0 5 0 INPUT NODEFVAL "wraddress[4..0]"

-- Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC "wrclock"

-- Retrieval info: USED_PORT: wrclocken 0 0 0 0 INPUT VCC "wrclocken"

-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"

-- Retrieval info: CONNECT: @address_a 0 0 5 0 wraddress 0 0 5 0

-- Retrieval info: CONNECT: @address_b 0 0 5 0 rdaddress 0 0 5 0

-- Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0

-- Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0

-- Retrieval info: CONNECT: @clocken0 0 0 0 0 wrclocken 0 0 0 0

-- Retrieval info: CONNECT: @clocken1 0 0 0 0 rdclocken 0 0 0 0

-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0

-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0

-- Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0

-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.vhd TRUE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.inc FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.cmp FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw.bsf FALSE

-- Retrieval info: GEN_FILE: TYPE_NORMAL ip_stratixiv_ram_cr_cw_inst.vhd FALSE

-- Retrieval info: LIB_FILE: altera_mf