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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY IEEE, common_pkg_lib;
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USE IEEE.std_logic_1164.ALL;
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USE IEEE.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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USE common_pkg_lib.tb_common_pkg.ALL;
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-- Purpose: Test bench for common_paged_ram_crw_crw
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--
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-- Features:
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-- . Use c_gap_sz = 0 to try writing and reading multiple page without idle
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-- cycles
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-- . Most applications use c_nof_pages = 2, but use > 2 is supported too.
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--
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-- Usage:
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-- > as 10
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-- > run -all
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ENTITY tb_common_paged_ram_crw_crw IS
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END tb_common_paged_ram_crw_crw;
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ARCHITECTURE tb OF tb_common_paged_ram_crw_crw IS
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CONSTANT clk_period : TIME := 10 ns;
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CONSTANT c_data_w : NATURAL := 8;
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CONSTANT c_nof_pages : NATURAL := 2; -- >= 2
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CONSTANT c_page_sz : NATURAL := 8;
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CONSTANT c_start_page_a : NATURAL := 0;
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CONSTANT c_start_page_b : NATURAL := 1;
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CONSTANT c_gap_sz : NATURAL := 0; -- >= 0
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CONSTANT c_rl : NATURAL := 1;
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SIGNAL rst : STD_LOGIC;
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SIGNAL clk : STD_LOGIC := '1';
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SIGNAL tb_end : STD_LOGIC := '0';
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-- DUT
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SIGNAL next_page : STD_LOGIC;
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SIGNAL next_page_a : STD_LOGIC;
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SIGNAL adr_a : STD_LOGIC_VECTOR(ceil_log2(c_page_sz)-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL wr_en_a : STD_LOGIC;
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SIGNAL wr_dat_a : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL next_page_b : STD_LOGIC;
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SIGNAL adr_b : STD_LOGIC_VECTOR(ceil_log2(c_page_sz)-1 DOWNTO 0) := (OTHERS=>'0');
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SIGNAL rd_en_b : STD_LOGIC := '0';
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SIGNAL mux_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
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SIGNAL mux_rd_val_b : STD_LOGIC;
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SIGNAL adr_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
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SIGNAL adr_rd_val_b : STD_LOGIC;
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SIGNAL ofs_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
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SIGNAL ofs_rd_val_b : STD_LOGIC;
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-- Verify
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SIGNAL verify_en : STD_LOGIC;
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SIGNAL ready : STD_LOGIC := '1';
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SIGNAL prev_mux_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
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SIGNAL prev_adr_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
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SIGNAL prev_ofs_rd_dat_b : STD_LOGIC_VECTOR(c_data_w-1 DOWNTO 0);
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BEGIN
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clk <= NOT clk AND NOT tb_end AFTER clk_period/2;
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rst <= '1', '0' AFTER clk_period*7;
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verify_en <= '0', '1' AFTER clk_period*(15+(c_nof_pages-1)*c_page_sz);
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-- Apply stimuli via port 'a', do write 'a' and read 'b', and derive the 'b' stimuli from the 'a' stimuli with 1 clock cycle latency
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next_page_a <= next_page;
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next_page_b <= next_page WHEN rising_edge(clk);
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wr_dat_a <= INCR_UVEC(wr_dat_a, 1) WHEN rising_edge(clk) AND wr_en_a='1';
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adr_a <= INCR_UVEC( adr_a, 1) WHEN rising_edge(clk) AND wr_en_a='1';
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adr_b <= adr_a WHEN rising_edge(clk);
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rd_en_b <= wr_en_a WHEN rising_edge(clk);
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p_stimuli : PROCESS
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BEGIN
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next_page <= '0';
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wr_en_a <= '0';
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proc_common_wait_until_low(clk, rst);
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proc_common_wait_some_cycles(clk, 3);
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-- Access the pages several times
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FOR I IN 0 TO c_nof_pages*3 LOOP
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wr_en_a <= '1';
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proc_common_wait_some_cycles(clk, c_page_sz-1);
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next_page <= '1';
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proc_common_wait_some_cycles(clk, 1);
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next_page <= '0';
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wr_en_a <= '0';
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proc_common_wait_some_cycles(clk, c_gap_sz); -- optinal gap between the pages
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END LOOP;
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wr_en_a <= '0';
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proc_common_wait_some_cycles(clk, c_page_sz);
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tb_end <= '1';
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WAIT;
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END PROCESS;
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u_dut_mux : ENTITY work.common_paged_ram_crw_crw
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GENERIC MAP (
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g_str => "use_mux",
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g_data_w => c_data_w,
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g_nof_pages => c_nof_pages,
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g_page_sz => c_page_sz,
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g_start_page_a => c_start_page_a,
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g_start_page_b => c_start_page_b
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)
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PORT MAP (
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rst_a => rst,
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rst_b => rst,
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clk_a => clk,
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clk_b => clk,
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clken_a => '1',
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clken_b => '1',
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next_page_a => next_page_a,
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adr_a => adr_a,
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wr_en_a => wr_en_a,
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wr_dat_a => wr_dat_a,
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rd_en_a => '0',
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rd_dat_a => OPEN,
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rd_val_a => OPEN,
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next_page_b => next_page_b,
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adr_b => adr_b,
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wr_en_b => '0',
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wr_dat_b => (OTHERS=>'0'),
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rd_en_b => rd_en_b,
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rd_dat_b => mux_rd_dat_b,
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rd_val_b => mux_rd_val_b
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);
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u_dut_adr : ENTITY work.common_paged_ram_crw_crw
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GENERIC MAP (
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g_str => "use_adr",
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g_data_w => c_data_w,
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g_nof_pages => c_nof_pages,
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g_page_sz => c_page_sz,
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g_start_page_a => c_start_page_a,
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g_start_page_b => c_start_page_b
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)
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PORT MAP (
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rst_a => rst,
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rst_b => rst,
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clk_a => clk,
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clk_b => clk,
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clken_a => '1',
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clken_b => '1',
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next_page_a => next_page_a,
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adr_a => adr_a,
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wr_en_a => wr_en_a,
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wr_dat_a => wr_dat_a,
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rd_en_a => '0',
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rd_dat_a => OPEN,
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rd_val_a => OPEN,
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next_page_b => next_page_b,
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adr_b => adr_b,
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wr_en_b => '0',
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wr_dat_b => (OTHERS=>'0'),
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rd_en_b => rd_en_b,
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rd_dat_b => adr_rd_dat_b,
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rd_val_b => adr_rd_val_b
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);
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u_dut_ofs : ENTITY work.common_paged_ram_crw_crw
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GENERIC MAP (
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g_str => "use_ofs",
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g_data_w => c_data_w,
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g_nof_pages => c_nof_pages,
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g_page_sz => c_page_sz,
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g_start_page_a => c_start_page_a,
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g_start_page_b => c_start_page_b
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)
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PORT MAP (
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rst_a => rst,
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rst_b => rst,
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clk_a => clk,
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clk_b => clk,
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clken_a => '1',
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clken_b => '1',
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next_page_a => next_page_a,
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adr_a => adr_a,
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wr_en_a => wr_en_a,
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wr_dat_a => wr_dat_a,
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rd_en_a => '0',
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rd_dat_a => OPEN,
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rd_val_a => OPEN,
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next_page_b => next_page_b,
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adr_b => adr_b,
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wr_en_b => '0',
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wr_dat_b => (OTHERS=>'0'),
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rd_en_b => rd_en_b,
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rd_dat_b => ofs_rd_dat_b,
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rd_val_b => ofs_rd_val_b
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);
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-- Verify that the read data is incrementing data
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proc_common_verify_data(c_rl, clk, verify_en, ready, mux_rd_val_b, mux_rd_dat_b, prev_mux_rd_dat_b);
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proc_common_verify_data(c_rl, clk, verify_en, ready, adr_rd_val_b, adr_rd_dat_b, prev_adr_rd_dat_b);
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proc_common_verify_data(c_rl, clk, verify_en, ready, ofs_rd_val_b, ofs_rd_dat_b, prev_ofs_rd_dat_b);
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-- Verify that the read data is the same for all three DUT variants
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p_verify_equal : PROCESS(clk)
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BEGIN
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IF rising_edge(clk) THEN
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IF UNSIGNED(mux_rd_dat_b) /= UNSIGNED(adr_rd_dat_b) OR UNSIGNED(mux_rd_dat_b) /= UNSIGNED(ofs_rd_dat_b) THEN
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REPORT "DUT : read data differs between two implementations" SEVERITY ERROR;
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END IF;
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IF mux_rd_val_b /= adr_rd_val_b OR mux_rd_val_b /= ofs_rd_val_b THEN
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REPORT "DUT : read valid differs between two implementations" SEVERITY ERROR;
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END IF;
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END IF;
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END PROCESS;
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END tb;
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