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[/] [astron_ram/] [trunk/] [tech_memory_component_pkg.vhd] - Blame information for rev 2

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1 2 danv 
-------------------------------------------------------------------------------
2 
--
3 
-- Copyright (C) 2014
4 
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5 
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 
--
7 
-- This program is free software: you can redistribute it and/or modify
8 
-- it under the terms of the GNU General Public License as published by
9 
-- the Free Software Foundation, either version 3 of the License, or
10 
-- (at your option) any later version.
11 
--
12 
-- This program is distributed in the hope that it will be useful,
13 
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
-- GNU General Public License for more details.
16 
--
17 
-- You should have received a copy of the GNU General Public License
18 
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
19 
--
20 
-------------------------------------------------------------------------------
21 
 
22 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
23 
 
24 
LIBRARY IEEE;
25 
USE IEEE.STD_LOGIC_1164.ALL;
26 
 
27 
PACKAGE tech_memory_component_pkg IS
28 
 
29 
  -----------------------------------------------------------------------------
30 
  -- ip_stratixiv
31 
  -----------------------------------------------------------------------------
32 
 
33 
  COMPONENT ip_stratixiv_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
34 
  GENERIC (
35 
    g_adr_a_w     : NATURAL := 5;
36 
    g_dat_a_w     : NATURAL := 32;
37 
    g_adr_b_w     : NATURAL := 7;
38 
    g_dat_b_w     : NATURAL := 8;
39 
    g_nof_words_a : NATURAL := 2**5;
40 
    g_nof_words_b : NATURAL := 2**7;
41 
    g_rd_latency  : NATURAL := 2;     -- choose 1 or 2
42 
    g_init_file   : STRING  := "UNUSED"
43 
  );
44 
  PORT (
45 
    address_a   : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
46 
    address_b   : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
47 
    clock_a   : IN STD_LOGIC  := '1';
48 
    clock_b   : IN STD_LOGIC ;
49 
    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
50 
    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
51 
    enable_a    : IN STD_LOGIC  := '1';
52 
    enable_b    : IN STD_LOGIC  := '1';
53 
    rden_a    : IN STD_LOGIC  := '1';
54 
    rden_b    : IN STD_LOGIC  := '1';
55 
    wren_a    : IN STD_LOGIC  := '0';
56 
    wren_b    : IN STD_LOGIC  := '0';
57 
    q_a   : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
58 
    q_b   : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
59 
  );
60 
  END COMPONENT;
61 
 
62 
  COMPONENT ip_stratixiv_ram_crw_crw IS
63 
  GENERIC (
64 
    g_adr_w      : NATURAL := 5;
65 
    g_dat_w      : NATURAL := 8;
66 
    g_nof_words  : NATURAL := 2**5;
67 
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
68 
    g_init_file  : STRING  := "UNUSED"
69 
  );
70 
  PORT (
71 
    address_a   : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
72 
    address_b   : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
73 
    clock_a   : IN STD_LOGIC  := '1';
74 
    clock_b   : IN STD_LOGIC ;
75 
    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
76 
    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
77 
    enable_a    : IN STD_LOGIC  := '1';
78 
    enable_b    : IN STD_LOGIC  := '1';
79 
    rden_a    : IN STD_LOGIC  := '1';
80 
    rden_b    : IN STD_LOGIC  := '1';
81 
    wren_a    : IN STD_LOGIC  := '0';
82 
    wren_b    : IN STD_LOGIC  := '0';
83 
    q_a   : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
84 
    q_b   : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
85 
  );
86 
  END COMPONENT;
87 
 
88 
  COMPONENT ip_stratixiv_ram_cr_cw IS
89 
  GENERIC (
90 
    g_adr_w      : NATURAL := 5;
91 
    g_dat_w      : NATURAL := 8;
92 
    g_nof_words  : NATURAL := 2**5;
93 
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
94 
    g_init_file  : STRING  := "UNUSED"
95 
  );
96 
  PORT (
97 
    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
98 
    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
99 
    rdclock   : IN  STD_LOGIC ;
100 
    rdclocken : IN  STD_LOGIC  := '1';
101 
    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
102 
    wrclock   : IN  STD_LOGIC  := '1';
103 
    wrclocken : IN  STD_LOGIC  := '1';
104 
    wren      : IN  STD_LOGIC  := '0';
105 
    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
106 
  );
107 
  END COMPONENT;
108 
 
109 
  COMPONENT ip_stratixiv_ram_r_w IS
110 
  GENERIC (
111 
    g_adr_w     : NATURAL := 5;
112 
    g_dat_w     : NATURAL := 8;
113 
    g_nof_words : NATURAL := 2**5;
114 
    g_init_file : STRING  := "UNUSED"
115 
  );
116 
  PORT (
117 
    clock       : IN STD_LOGIC  := '1';
118 
    enable      : IN STD_LOGIC  := '1';
119 
    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
120 
    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
121 
    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
122 
    wren        : IN STD_LOGIC  := '0';
123 
    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
124 
  );
125 
  END COMPONENT;
126 
 
127 
--  COMPONENT ip_stratixiv_rom_r IS
128 
--  GENERIC (
129 
--    g_adr_w     : NATURAL := 5;
130 
--    g_dat_w     : NATURAL := 8;
131 
--    g_nof_words : NATURAL := 2**5;
132 
--    g_init_file : STRING  := "UNUSED"
133 
--  );
134 
--  PORT (
135 
--    address   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
136 
--    clock     : IN STD_LOGIC  := '1';
137 
--    clken     : IN STD_LOGIC  := '1';
138 
--    q         : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
139 
--  );
140 
--  END COMPONENT;
141 
 
142 
 
143 
  -----------------------------------------------------------------------------
144 
  -- ip_arria10
145 
  -----------------------------------------------------------------------------
146 
 
147 
--  COMPONENT ip_arria10_ram_crwk_crw IS
148 
--  GENERIC (
149 
--    g_adr_a_w     : NATURAL := 5;
150 
--    g_dat_a_w     : NATURAL := 32;
151 
--    g_adr_b_w     : NATURAL := 4;
152 
--    g_dat_b_w     : NATURAL := 64;
153 
--    g_nof_words_a : NATURAL := 2**5;
154 
--    g_nof_words_b : NATURAL := 2**4;
155 
--    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
156 
--    g_init_file   : STRING  := "UNUSED"
157 
--  );
158 
--  PORT
159 
--  (
160 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
161 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
162 
--    clk_a     : IN STD_LOGIC  := '1';
163 
--    clk_b     : IN STD_LOGIC ;
164 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
165 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
166 
--    wren_a    : IN STD_LOGIC  := '0';
167 
--    wren_b    : IN STD_LOGIC  := '0';
168 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
169 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
170 
--  );
171 
--  END COMPONENT;
172 
--
173 
--  COMPONENT ip_arria10_ram_crw_crw IS
174 
--  GENERIC (
175 
--    g_inferred   : BOOLEAN := FALSE;
176 
--    g_adr_w      : NATURAL := 5;
177 
--    g_dat_w      : NATURAL := 8;
178 
--    g_nof_words  : NATURAL := 2**5;
179 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
180 
--    g_init_file  : STRING  := "UNUSED"
181 
--  );
182 
--  PORT
183 
--  (
184 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
185 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
186 
--    clk_a     : IN STD_LOGIC  := '1';
187 
--    clk_b     : IN STD_LOGIC ;
188 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
189 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
190 
--    wren_a    : IN STD_LOGIC  := '0';
191 
--    wren_b    : IN STD_LOGIC  := '0';
192 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
193 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
194 
--  );
195 
--  END COMPONENT;
196 
--
197 
--  COMPONENT ip_arria10_ram_cr_cw IS
198 
--  GENERIC (
199 
--    g_inferred   : BOOLEAN := FALSE;
200 
--    g_adr_w      : NATURAL := 5;
201 
--    g_dat_w      : NATURAL := 8;
202 
--    g_nof_words  : NATURAL := 2**5;
203 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
204 
--    g_init_file  : STRING  := "UNUSED"
205 
--  );
206 
--  PORT
207 
--  (
208 
--    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
209 
--    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
210 
--    rdclk     : IN  STD_LOGIC ;
211 
--    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
212 
--    wrclk     : IN  STD_LOGIC  := '1';
213 
--    wren      : IN  STD_LOGIC  := '0';
214 
--    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
215 
--  );
216 
--  END COMPONENT;
217 
--
218 
--  COMPONENT ip_arria10_ram_r_w IS
219 
--  GENERIC (
220 
--    g_inferred   : BOOLEAN := FALSE;
221 
--    g_adr_w      : NATURAL := 5;
222 
--    g_dat_w      : NATURAL := 8;
223 
--    g_nof_words  : NATURAL := 2**5;
224 
--    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
225 
--    g_init_file  : STRING  := "UNUSED"
226 
--  );
227 
--  PORT (
228 
--    clk         : IN STD_LOGIC  := '1';
229 
--    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
230 
--    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
231 
--    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
232 
--    wren        : IN STD_LOGIC  := '0';
233 
--    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
234 
--  );
235 
--  END COMPONENT;
236 
--
237 
--  -----------------------------------------------------------------------------
238 
--  -- ip_arria10_e3sge3
239 
--  -----------------------------------------------------------------------------
240 
--
241 
--  COMPONENT ip_arria10_e3sge3_ram_crwk_crw IS
242 
--  GENERIC (
243 
--    g_adr_a_w     : NATURAL := 5;
244 
--    g_dat_a_w     : NATURAL := 32;
245 
--    g_adr_b_w     : NATURAL := 4;
246 
--    g_dat_b_w     : NATURAL := 64;
247 
--    g_nof_words_a : NATURAL := 2**5;
248 
--    g_nof_words_b : NATURAL := 2**4;
249 
--    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
250 
--    g_init_file   : STRING  := "UNUSED"
251 
--  );
252 
--  PORT
253 
--  (
254 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
255 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
256 
--    clk_a     : IN STD_LOGIC  := '1';
257 
--    clk_b     : IN STD_LOGIC ;
258 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
259 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
260 
--    wren_a    : IN STD_LOGIC  := '0';
261 
--    wren_b    : IN STD_LOGIC  := '0';
262 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
263 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
264 
--  );
265 
--  END COMPONENT;
266 
--
267 
--  COMPONENT ip_arria10_e3sge3_ram_crw_crw IS
268 
--  GENERIC (
269 
--    g_inferred   : BOOLEAN := FALSE;
270 
--    g_adr_w      : NATURAL := 5;
271 
--    g_dat_w      : NATURAL := 8;
272 
--    g_nof_words  : NATURAL := 2**5;
273 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
274 
--    g_init_file  : STRING  := "UNUSED"
275 
--  );
276 
--  PORT
277 
--  (
278 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
279 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
280 
--    clk_a     : IN STD_LOGIC  := '1';
281 
--    clk_b     : IN STD_LOGIC ;
282 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
283 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
284 
--    wren_a    : IN STD_LOGIC  := '0';
285 
--    wren_b    : IN STD_LOGIC  := '0';
286 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
287 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
288 
--  );
289 
--  END COMPONENT;
290 
--
291 
--  COMPONENT ip_arria10_e3sge3_ram_cr_cw IS
292 
--  GENERIC (
293 
--    g_inferred   : BOOLEAN := FALSE;
294 
--    g_adr_w      : NATURAL := 5;
295 
--    g_dat_w      : NATURAL := 8;
296 
--    g_nof_words  : NATURAL := 2**5;
297 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
298 
--    g_init_file  : STRING  := "UNUSED"
299 
--  );
300 
--  PORT
301 
--  (
302 
--    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
303 
--    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
304 
--    rdclk     : IN  STD_LOGIC ;
305 
--    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
306 
--    wrclk     : IN  STD_LOGIC  := '1';
307 
--    wren      : IN  STD_LOGIC  := '0';
308 
--    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
309 
--  );
310 
--  END COMPONENT;
311 
--
312 
--  COMPONENT ip_arria10_e3sge3_ram_r_w IS
313 
--  GENERIC (
314 
--    g_inferred   : BOOLEAN := FALSE;
315 
--    g_adr_w      : NATURAL := 5;
316 
--    g_dat_w      : NATURAL := 8;
317 
--    g_nof_words  : NATURAL := 2**5;
318 
--    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
319 
--    g_init_file  : STRING  := "UNUSED"
320 
--  );
321 
--  PORT (
322 
--    clk         : IN STD_LOGIC  := '1';
323 
--    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
324 
--    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
325 
--    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
326 
--    wren        : IN STD_LOGIC  := '0';
327 
--    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
328 
--  );
329 
--  END COMPONENT;
330 
--
331 
--  -----------------------------------------------------------------------------
332 
--  -- ip_arria10_e1sg
333 
--  -----------------------------------------------------------------------------
334 
--
335 
--  COMPONENT ip_arria10_e1sg_ram_crwk_crw IS
336 
--  GENERIC (
337 
--    g_adr_a_w     : NATURAL := 5;
338 
--    g_dat_a_w     : NATURAL := 32;
339 
--    g_adr_b_w     : NATURAL := 4;
340 
--    g_dat_b_w     : NATURAL := 64;
341 
--    g_nof_words_a : NATURAL := 2**5;
342 
--    g_nof_words_b : NATURAL := 2**4;
343 
--    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
344 
--    g_init_file   : STRING  := "UNUSED"
345 
--  );
346 
--  PORT
347 
--  (
348 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
349 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
350 
--    clk_a     : IN STD_LOGIC  := '1';
351 
--    clk_b     : IN STD_LOGIC ;
352 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
353 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
354 
--    wren_a    : IN STD_LOGIC  := '0';
355 
--    wren_b    : IN STD_LOGIC  := '0';
356 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
357 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
358 
--  );
359 
--  END COMPONENT;
360 
--
361 
--  COMPONENT ip_arria10_e1sg_ram_crw_crw IS
362 
--  GENERIC (
363 
--    g_inferred   : BOOLEAN := FALSE;
364 
--    g_adr_w      : NATURAL := 5;
365 
--    g_dat_w      : NATURAL := 8;
366 
--    g_nof_words  : NATURAL := 2**5;
367 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
368 
--    g_init_file  : STRING  := "UNUSED"
369 
--  );
370 
--  PORT
371 
--  (
372 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
373 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
374 
--    clk_a     : IN STD_LOGIC  := '1';
375 
--    clk_b     : IN STD_LOGIC ;
376 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
377 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
378 
--    wren_a    : IN STD_LOGIC  := '0';
379 
--    wren_b    : IN STD_LOGIC  := '0';
380 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
381 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
382 
--  );
383 
--  END COMPONENT;
384 
--
385 
--  COMPONENT ip_arria10_e1sg_ram_cr_cw IS
386 
--  GENERIC (
387 
--    g_inferred   : BOOLEAN := FALSE;
388 
--    g_adr_w      : NATURAL := 5;
389 
--    g_dat_w      : NATURAL := 8;
390 
--    g_nof_words  : NATURAL := 2**5;
391 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
392 
--    g_init_file  : STRING  := "UNUSED"
393 
--  );
394 
--  PORT
395 
--  (
396 
--    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
397 
--    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
398 
--    rdclk     : IN  STD_LOGIC ;
399 
--    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
400 
--    wrclk     : IN  STD_LOGIC  := '1';
401 
--    wren      : IN  STD_LOGIC  := '0';
402 
--    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
403 
--  );
404 
--  END COMPONENT;
405 
--
406 
--  COMPONENT ip_arria10_e1sg_ram_r_w IS
407 
--  GENERIC (
408 
--    g_inferred   : BOOLEAN := FALSE;
409 
--    g_adr_w      : NATURAL := 5;
410 
--    g_dat_w      : NATURAL := 8;
411 
--    g_nof_words  : NATURAL := 2**5;
412 
--    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
413 
--    g_init_file  : STRING  := "UNUSED"
414 
--  );
415 
--  PORT (
416 
--    clk         : IN STD_LOGIC  := '1';
417 
--    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
418 
--    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
419 
--    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
420 
--    wren        : IN STD_LOGIC  := '0';
421 
--    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
422 
--  );
423 
--  END COMPONENT;
424 
 
425 
END tech_memory_component_pkg;

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