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[/] [astron_ram/] [trunk/] [tech_memory_component_pkg.vhd] - Blame information for rev 3

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1 2 danv 
-------------------------------------------------------------------------------
2 
--
3 3 danv 
-- Copyright 2020
4 2 danv 
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
5 
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
6 3 danv 
--
7 
-- Licensed under the Apache License, Version 2.0 (the "License");
8 
-- you may not use this file except in compliance with the License.
9 
-- You may obtain a copy of the License at
10 
--
11 
--     http://www.apache.org/licenses/LICENSE-2.0
12 
--
13 
-- Unless required by applicable law or agreed to in writing, software
14 
-- distributed under the License is distributed on an "AS IS" BASIS,
15 
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 
-- See the License for the specific language governing permissions and
17 
-- limitations under the License.
18 2 danv 
--
19 
-------------------------------------------------------------------------------
20 
 
21 
-- Purpose: IP components declarations for various devices that get wrapped by the tech components
22 
 
23 
LIBRARY IEEE;
24 
USE IEEE.STD_LOGIC_1164.ALL;
25 
 
26 
PACKAGE tech_memory_component_pkg IS
27 
 
28 
  -----------------------------------------------------------------------------
29 
  -- ip_stratixiv
30 
  -----------------------------------------------------------------------------
31 
 
32 
  COMPONENT ip_stratixiv_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
33 
  GENERIC (
34 
    g_adr_a_w     : NATURAL := 5;
35 
    g_dat_a_w     : NATURAL := 32;
36 
    g_adr_b_w     : NATURAL := 7;
37 
    g_dat_b_w     : NATURAL := 8;
38 
    g_nof_words_a : NATURAL := 2**5;
39 
    g_nof_words_b : NATURAL := 2**7;
40 
    g_rd_latency  : NATURAL := 2;     -- choose 1 or 2
41 
    g_init_file   : STRING  := "UNUSED"
42 
  );
43 
  PORT (
44 
    address_a   : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
45 
    address_b   : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
46 
    clock_a   : IN STD_LOGIC  := '1';
47 
    clock_b   : IN STD_LOGIC ;
48 
    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
49 
    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
50 
    enable_a    : IN STD_LOGIC  := '1';
51 
    enable_b    : IN STD_LOGIC  := '1';
52 
    rden_a    : IN STD_LOGIC  := '1';
53 
    rden_b    : IN STD_LOGIC  := '1';
54 
    wren_a    : IN STD_LOGIC  := '0';
55 
    wren_b    : IN STD_LOGIC  := '0';
56 
    q_a   : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
57 
    q_b   : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
58 
  );
59 
  END COMPONENT;
60 
 
61 
  COMPONENT ip_stratixiv_ram_crw_crw IS
62 
  GENERIC (
63 
    g_adr_w      : NATURAL := 5;
64 
    g_dat_w      : NATURAL := 8;
65 
    g_nof_words  : NATURAL := 2**5;
66 
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
67 
    g_init_file  : STRING  := "UNUSED"
68 
  );
69 
  PORT (
70 
    address_a   : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
71 
    address_b   : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
72 
    clock_a   : IN STD_LOGIC  := '1';
73 
    clock_b   : IN STD_LOGIC ;
74 
    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
75 
    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
76 
    enable_a    : IN STD_LOGIC  := '1';
77 
    enable_b    : IN STD_LOGIC  := '1';
78 
    rden_a    : IN STD_LOGIC  := '1';
79 
    rden_b    : IN STD_LOGIC  := '1';
80 
    wren_a    : IN STD_LOGIC  := '0';
81 
    wren_b    : IN STD_LOGIC  := '0';
82 
    q_a   : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
83 
    q_b   : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
84 
  );
85 
  END COMPONENT;
86 
 
87 
  COMPONENT ip_stratixiv_ram_cr_cw IS
88 
  GENERIC (
89 
    g_adr_w      : NATURAL := 5;
90 
    g_dat_w      : NATURAL := 8;
91 
    g_nof_words  : NATURAL := 2**5;
92 
    g_rd_latency : NATURAL := 2;  -- choose 1 or 2
93 
    g_init_file  : STRING  := "UNUSED"
94 
  );
95 
  PORT (
96 
    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
97 
    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
98 
    rdclock   : IN  STD_LOGIC ;
99 
    rdclocken : IN  STD_LOGIC  := '1';
100 
    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
101 
    wrclock   : IN  STD_LOGIC  := '1';
102 
    wrclocken : IN  STD_LOGIC  := '1';
103 
    wren      : IN  STD_LOGIC  := '0';
104 
    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
105 
  );
106 
  END COMPONENT;
107 
 
108 
  COMPONENT ip_stratixiv_ram_r_w IS
109 
  GENERIC (
110 
    g_adr_w     : NATURAL := 5;
111 
    g_dat_w     : NATURAL := 8;
112 
    g_nof_words : NATURAL := 2**5;
113 
    g_init_file : STRING  := "UNUSED"
114 
  );
115 
  PORT (
116 
    clock       : IN STD_LOGIC  := '1';
117 
    enable      : IN STD_LOGIC  := '1';
118 
    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0);
119 
    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
120 
    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
121 
    wren        : IN STD_LOGIC  := '0';
122 
    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
123 
  );
124 
  END COMPONENT;
125 
 
126 
--  COMPONENT ip_stratixiv_rom_r IS
127 
--  GENERIC (
128 
--    g_adr_w     : NATURAL := 5;
129 
--    g_dat_w     : NATURAL := 8;
130 
--    g_nof_words : NATURAL := 2**5;
131 
--    g_init_file : STRING  := "UNUSED"
132 
--  );
133 
--  PORT (
134 
--    address   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0);
135 
--    clock     : IN STD_LOGIC  := '1';
136 
--    clken     : IN STD_LOGIC  := '1';
137 
--    q         : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
138 
--  );
139 
--  END COMPONENT;
140 
 
141 
 
142 
  -----------------------------------------------------------------------------
143 
  -- ip_arria10
144 
  -----------------------------------------------------------------------------
145 
 
146 
--  COMPONENT ip_arria10_ram_crwk_crw IS
147 
--  GENERIC (
148 
--    g_adr_a_w     : NATURAL := 5;
149 
--    g_dat_a_w     : NATURAL := 32;
150 
--    g_adr_b_w     : NATURAL := 4;
151 
--    g_dat_b_w     : NATURAL := 64;
152 
--    g_nof_words_a : NATURAL := 2**5;
153 
--    g_nof_words_b : NATURAL := 2**4;
154 
--    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
155 
--    g_init_file   : STRING  := "UNUSED"
156 
--  );
157 
--  PORT
158 
--  (
159 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
160 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
161 
--    clk_a     : IN STD_LOGIC  := '1';
162 
--    clk_b     : IN STD_LOGIC ;
163 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
164 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
165 
--    wren_a    : IN STD_LOGIC  := '0';
166 
--    wren_b    : IN STD_LOGIC  := '0';
167 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
168 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
169 
--  );
170 
--  END COMPONENT;
171 
--
172 
--  COMPONENT ip_arria10_ram_crw_crw IS
173 
--  GENERIC (
174 
--    g_inferred   : BOOLEAN := FALSE;
175 
--    g_adr_w      : NATURAL := 5;
176 
--    g_dat_w      : NATURAL := 8;
177 
--    g_nof_words  : NATURAL := 2**5;
178 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
179 
--    g_init_file  : STRING  := "UNUSED"
180 
--  );
181 
--  PORT
182 
--  (
183 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
184 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
185 
--    clk_a     : IN STD_LOGIC  := '1';
186 
--    clk_b     : IN STD_LOGIC ;
187 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
188 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
189 
--    wren_a    : IN STD_LOGIC  := '0';
190 
--    wren_b    : IN STD_LOGIC  := '0';
191 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
192 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
193 
--  );
194 
--  END COMPONENT;
195 
--
196 
--  COMPONENT ip_arria10_ram_cr_cw IS
197 
--  GENERIC (
198 
--    g_inferred   : BOOLEAN := FALSE;
199 
--    g_adr_w      : NATURAL := 5;
200 
--    g_dat_w      : NATURAL := 8;
201 
--    g_nof_words  : NATURAL := 2**5;
202 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
203 
--    g_init_file  : STRING  := "UNUSED"
204 
--  );
205 
--  PORT
206 
--  (
207 
--    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
208 
--    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
209 
--    rdclk     : IN  STD_LOGIC ;
210 
--    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
211 
--    wrclk     : IN  STD_LOGIC  := '1';
212 
--    wren      : IN  STD_LOGIC  := '0';
213 
--    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
214 
--  );
215 
--  END COMPONENT;
216 
--
217 
--  COMPONENT ip_arria10_ram_r_w IS
218 
--  GENERIC (
219 
--    g_inferred   : BOOLEAN := FALSE;
220 
--    g_adr_w      : NATURAL := 5;
221 
--    g_dat_w      : NATURAL := 8;
222 
--    g_nof_words  : NATURAL := 2**5;
223 
--    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
224 
--    g_init_file  : STRING  := "UNUSED"
225 
--  );
226 
--  PORT (
227 
--    clk         : IN STD_LOGIC  := '1';
228 
--    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
229 
--    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
230 
--    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
231 
--    wren        : IN STD_LOGIC  := '0';
232 
--    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
233 
--  );
234 
--  END COMPONENT;
235 
--
236 
--  -----------------------------------------------------------------------------
237 
--  -- ip_arria10_e3sge3
238 
--  -----------------------------------------------------------------------------
239 
--
240 
--  COMPONENT ip_arria10_e3sge3_ram_crwk_crw IS
241 
--  GENERIC (
242 
--    g_adr_a_w     : NATURAL := 5;
243 
--    g_dat_a_w     : NATURAL := 32;
244 
--    g_adr_b_w     : NATURAL := 4;
245 
--    g_dat_b_w     : NATURAL := 64;
246 
--    g_nof_words_a : NATURAL := 2**5;
247 
--    g_nof_words_b : NATURAL := 2**4;
248 
--    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
249 
--    g_init_file   : STRING  := "UNUSED"
250 
--  );
251 
--  PORT
252 
--  (
253 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
254 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
255 
--    clk_a     : IN STD_LOGIC  := '1';
256 
--    clk_b     : IN STD_LOGIC ;
257 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
258 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
259 
--    wren_a    : IN STD_LOGIC  := '0';
260 
--    wren_b    : IN STD_LOGIC  := '0';
261 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
262 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
263 
--  );
264 
--  END COMPONENT;
265 
--
266 
--  COMPONENT ip_arria10_e3sge3_ram_crw_crw IS
267 
--  GENERIC (
268 
--    g_inferred   : BOOLEAN := FALSE;
269 
--    g_adr_w      : NATURAL := 5;
270 
--    g_dat_w      : NATURAL := 8;
271 
--    g_nof_words  : NATURAL := 2**5;
272 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
273 
--    g_init_file  : STRING  := "UNUSED"
274 
--  );
275 
--  PORT
276 
--  (
277 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
278 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
279 
--    clk_a     : IN STD_LOGIC  := '1';
280 
--    clk_b     : IN STD_LOGIC ;
281 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
282 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
283 
--    wren_a    : IN STD_LOGIC  := '0';
284 
--    wren_b    : IN STD_LOGIC  := '0';
285 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
286 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
287 
--  );
288 
--  END COMPONENT;
289 
--
290 
--  COMPONENT ip_arria10_e3sge3_ram_cr_cw IS
291 
--  GENERIC (
292 
--    g_inferred   : BOOLEAN := FALSE;
293 
--    g_adr_w      : NATURAL := 5;
294 
--    g_dat_w      : NATURAL := 8;
295 
--    g_nof_words  : NATURAL := 2**5;
296 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
297 
--    g_init_file  : STRING  := "UNUSED"
298 
--  );
299 
--  PORT
300 
--  (
301 
--    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
302 
--    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
303 
--    rdclk     : IN  STD_LOGIC ;
304 
--    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
305 
--    wrclk     : IN  STD_LOGIC  := '1';
306 
--    wren      : IN  STD_LOGIC  := '0';
307 
--    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
308 
--  );
309 
--  END COMPONENT;
310 
--
311 
--  COMPONENT ip_arria10_e3sge3_ram_r_w IS
312 
--  GENERIC (
313 
--    g_inferred   : BOOLEAN := FALSE;
314 
--    g_adr_w      : NATURAL := 5;
315 
--    g_dat_w      : NATURAL := 8;
316 
--    g_nof_words  : NATURAL := 2**5;
317 
--    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
318 
--    g_init_file  : STRING  := "UNUSED"
319 
--  );
320 
--  PORT (
321 
--    clk         : IN STD_LOGIC  := '1';
322 
--    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
323 
--    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
324 
--    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
325 
--    wren        : IN STD_LOGIC  := '0';
326 
--    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
327 
--  );
328 
--  END COMPONENT;
329 
--
330 
--  -----------------------------------------------------------------------------
331 
--  -- ip_arria10_e1sg
332 
--  -----------------------------------------------------------------------------
333 
--
334 
--  COMPONENT ip_arria10_e1sg_ram_crwk_crw IS
335 
--  GENERIC (
336 
--    g_adr_a_w     : NATURAL := 5;
337 
--    g_dat_a_w     : NATURAL := 32;
338 
--    g_adr_b_w     : NATURAL := 4;
339 
--    g_dat_b_w     : NATURAL := 64;
340 
--    g_nof_words_a : NATURAL := 2**5;
341 
--    g_nof_words_b : NATURAL := 2**4;
342 
--    g_rd_latency  : NATURAL := 1;     -- choose 1 or 2
343 
--    g_init_file   : STRING  := "UNUSED"
344 
--  );
345 
--  PORT
346 
--  (
347 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
348 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
349 
--    clk_a     : IN STD_LOGIC  := '1';
350 
--    clk_b     : IN STD_LOGIC ;
351 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
352 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
353 
--    wren_a    : IN STD_LOGIC  := '0';
354 
--    wren_b    : IN STD_LOGIC  := '0';
355 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
356 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
357 
--  );
358 
--  END COMPONENT;
359 
--
360 
--  COMPONENT ip_arria10_e1sg_ram_crw_crw IS
361 
--  GENERIC (
362 
--    g_inferred   : BOOLEAN := FALSE;
363 
--    g_adr_w      : NATURAL := 5;
364 
--    g_dat_w      : NATURAL := 8;
365 
--    g_nof_words  : NATURAL := 2**5;
366 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
367 
--    g_init_file  : STRING  := "UNUSED"
368 
--  );
369 
--  PORT
370 
--  (
371 
--    address_a : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
372 
--    address_b : IN STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
373 
--    clk_a     : IN STD_LOGIC  := '1';
374 
--    clk_b     : IN STD_LOGIC ;
375 
--    data_a    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
376 
--    data_b    : IN STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
377 
--    wren_a    : IN STD_LOGIC  := '0';
378 
--    wren_b    : IN STD_LOGIC  := '0';
379 
--    q_a       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
380 
--    q_b       : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
381 
--  );
382 
--  END COMPONENT;
383 
--
384 
--  COMPONENT ip_arria10_e1sg_ram_cr_cw IS
385 
--  GENERIC (
386 
--    g_inferred   : BOOLEAN := FALSE;
387 
--    g_adr_w      : NATURAL := 5;
388 
--    g_dat_w      : NATURAL := 8;
389 
--    g_nof_words  : NATURAL := 2**5;
390 
--    g_rd_latency : NATURAL := 1;  -- choose 1 or 2
391 
--    g_init_file  : STRING  := "UNUSED"
392 
--  );
393 
--  PORT
394 
--  (
395 
--    data      : IN  STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0);
396 
--    rdaddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
397 
--    rdclk     : IN  STD_LOGIC ;
398 
--    wraddress : IN  STD_LOGIC_VECTOR (g_adr_w-1 DOWNTO 0);
399 
--    wrclk     : IN  STD_LOGIC  := '1';
400 
--    wren      : IN  STD_LOGIC  := '0';
401 
--    q         : OUT STD_LOGIC_VECTOR (g_dat_w-1 DOWNTO 0)
402 
--  );
403 
--  END COMPONENT;
404 
--
405 
--  COMPONENT ip_arria10_e1sg_ram_r_w IS
406 
--  GENERIC (
407 
--    g_inferred   : BOOLEAN := FALSE;
408 
--    g_adr_w      : NATURAL := 5;
409 
--    g_dat_w      : NATURAL := 8;
410 
--    g_nof_words  : NATURAL := 2**5;
411 
--    g_rd_latency : NATURAL := 1;     -- choose 1 or 2
412 
--    g_init_file  : STRING  := "UNUSED"
413 
--  );
414 
--  PORT (
415 
--    clk         : IN STD_LOGIC  := '1';
416 
--    data        : IN STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0) := (OTHERS=>'0');
417 
--    rdaddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
418 
--    wraddress   : IN STD_LOGIC_VECTOR(g_adr_w-1 DOWNTO 0) := (OTHERS=>'0');
419 
--    wren        : IN STD_LOGIC  := '0';
420 
--    q           : OUT STD_LOGIC_VECTOR(g_dat_w-1 DOWNTO 0)
421 
--  );
422 
--  END COMPONENT;
423 
 
424 
END tech_memory_component_pkg;

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