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[/] [astron_ram/] [trunk/] [tech_memory_ram_crwk_crw.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE work.tech_memory_component_pkg.ALL;
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--USE technology_lib.technology_pkg.ALL;
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--USE technology_lib.technology_select_pkg.ALL;
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-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
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--LIBRARY ip_stratixiv_ram_lib;
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--LIBRARY ip_arria10_ram_lib;
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--LIBRARY ip_arria10_e3sge3_ram_lib;
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--LIBRARY ip_arria10_e1sg_ram_lib;
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ENTITY tech_memory_ram_crwk_crw IS  -- support different port data widths and corresponding address ranges
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  GENERIC (
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    g_technology  : NATURAL := 0; --c_tech_select_default;
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    g_adr_a_w     : NATURAL := 5;
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    g_dat_a_w     : NATURAL := 32;
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    g_adr_b_w     : NATURAL := 7;
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    g_dat_b_w     : NATURAL := 8;
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    g_nof_words_a : NATURAL := 2**5;
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    g_nof_words_b : NATURAL := 2**7;
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    g_rd_latency  : NATURAL := 2;     -- choose 1 or 2
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    g_init_file   : STRING  := "UNUSED"
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  );
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  PORT
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  (
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    address_a : IN STD_LOGIC_VECTOR (g_adr_a_w-1 DOWNTO 0);
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    address_b : IN STD_LOGIC_VECTOR (g_adr_b_w-1 DOWNTO 0);
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    clock_a   : IN STD_LOGIC  := '1';
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    clock_b   : IN STD_LOGIC ;
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    data_a    : IN STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
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    data_b    : IN STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0);
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    enable_a  : IN STD_LOGIC  := '1';
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    enable_b  : IN STD_LOGIC  := '1';
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    rden_a    : IN STD_LOGIC  := '1';
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    rden_b    : IN STD_LOGIC  := '1';
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    wren_a    : IN STD_LOGIC  := '0';
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    wren_b    : IN STD_LOGIC  := '0';
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    q_a       : OUT STD_LOGIC_VECTOR (g_dat_a_w-1 DOWNTO 0);
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    q_b       : OUT STD_LOGIC_VECTOR (g_dat_b_w-1 DOWNTO 0)
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  );
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END tech_memory_ram_crwk_crw;
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ARCHITECTURE str OF tech_memory_ram_crwk_crw IS
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BEGIN
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  gen_ip_stratixiv : IF g_technology=0 GENERATE
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    u0 : ip_stratixiv_ram_crwk_crw
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    GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
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    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, enable_a, enable_b, rden_a, rden_b, wren_a, wren_b, q_a, q_b);
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  END GENERATE;
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--  gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
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--    u0 : ip_arria10_ram_crwk_crw
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--    GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
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--    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
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--  END GENERATE;
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--  
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--  gen_ip_arria10_e3sge3 : IF g_technology=c_tech_arria10_e3sge3 GENERATE
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--    u0 : ip_arria10_e3sge3_ram_crwk_crw
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--    GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
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--    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
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--  END GENERATE;
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--  
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--  gen_ip_arria10_e1sg : IF g_technology=c_tech_arria10_e1sg GENERATE
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--    u0 : ip_arria10_e1sg_ram_crwk_crw
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--    GENERIC MAP (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
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--    PORT MAP (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
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--  END GENERATE;
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END ARCHITECTURE;

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