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[/] [astron_requantizer/] [trunk/] [common_resize.vhd] - Blame information for rev 4

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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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-- 
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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-- 
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--     http://www.apache.org/licenses/LICENSE-2.0
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-- 
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee, common_pkg_lib, common_components_lib;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY common_resize IS
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  GENERIC (
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    g_representation  : STRING  := "SIGNED";  -- SIGNED or UNSIGNED resizing
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    g_clip            : BOOLEAN := FALSE;     -- when TRUE clip input if it is outside the output range, else wrap
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    g_clip_symmetric  : BOOLEAN := FALSE;     -- when TRUE clip signed symmetric to +c_smax and -c_smax, else to +c_smax and c_smin_symm
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                                              -- for wrapping when g_clip=FALSE the g_clip_symmetric is ignored, so signed wrapping is done asymmetric
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    g_pipeline_input  : NATURAL := 0;         -- >= 0
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    g_pipeline_output : NATURAL := 1;         -- >= 0
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    g_in_dat_w        : INTEGER := 36;
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    g_out_dat_w       : INTEGER := 18
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  );
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  PORT (
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    clk        : IN  STD_LOGIC;
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    clken      : IN  STD_LOGIC := '1';
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    in_dat     : IN  STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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    out_dat    : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
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    out_ovr    : OUT STD_LOGIC
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  );
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END;
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ARCHITECTURE rtl OF common_resize IS
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  -- Clipping is only necessary when g_out_dat_w<g_in_dat_w.
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  CONSTANT c_clip      : BOOLEAN := g_clip AND (g_out_dat_w<g_in_dat_w);
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  -- Use SIGNED, UNSIGNED to avoid NATURAL (32 bit range) overflow error
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  CONSTANT c_umax      : UNSIGNED(out_dat'RANGE) := UNSIGNED(      c_slv1(g_out_dat_w-1 DOWNTO 0));  -- =  2** g_out_dat_w   -1
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  CONSTANT c_smax      :   SIGNED(out_dat'RANGE) :=   SIGNED('0' & c_slv1(g_out_dat_w-2 DOWNTO 0));  -- =  2**(g_out_dat_w-1)-1
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  CONSTANT c_smin_most :   SIGNED(out_dat'RANGE) :=   SIGNED('1' & c_slv0(g_out_dat_w-2 DOWNTO 0));  -- = -2**(c_in_dat_w-1)
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  CONSTANT c_smin_symm :   SIGNED(out_dat'RANGE) := -c_smax;                                         -- = -2**(c_in_dat_w-1)+1
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  CONSTANT c_smin      :   SIGNED(out_dat'RANGE) := sel_a_b(g_clip_symmetric, c_smin_symm, c_smin_most);
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  SIGNAL reg_dat     : STD_LOGIC_VECTOR(in_dat'RANGE);
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  SIGNAL wrap        : STD_LOGIC;
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  SIGNAL clip        : STD_LOGIC;
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  SIGNAL sign        : STD_LOGIC;
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  SIGNAL res_ovr     : STD_LOGIC;
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  SIGNAL res_dat     : STD_LOGIC_VECTOR(out_dat'RANGE);
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  SIGNAL res_vec     : STD_LOGIC_VECTOR(g_out_dat_w DOWNTO 0);
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  SIGNAL out_vec     : STD_LOGIC_VECTOR(g_out_dat_w DOWNTO 0);
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BEGIN
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  u_input_pipe : ENTITY common_components_lib.common_pipeline  -- pipeline input
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  GENERIC MAP (
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    g_representation => "SIGNED",
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    g_pipeline       => g_pipeline_input,
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    g_in_dat_w       => g_in_dat_w,
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    g_out_dat_w      => g_in_dat_w
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  )
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  PORT MAP (
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    clk     => clk,
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    clken   => clken,
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    in_dat  => in_dat,
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    out_dat => reg_dat
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  );
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  no_clip : IF c_clip=FALSE GENERATE
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    -- Note that g_pipeline_input=0 AND g_clip=FALSE is equivalent to using RESIZE_SVEC or RESIZE_UVEC directly.
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    gen_s : IF g_representation="SIGNED" GENERATE
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      -- If g_out_dat_w>g_in_dat_w then IEEE resize extends the sign bit,
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      -- else IEEE resize preserves the sign bit and keeps the low part.
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      wrap <= '1' WHEN SIGNED(reg_dat)>c_smax OR SIGNED(reg_dat)< c_smin_most ELSE '0';
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      res_dat <= RESIZE_SVEC(reg_dat, g_out_dat_w);
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      res_ovr <= wrap;
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    END GENERATE;
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    gen_u : IF g_representation="UNSIGNED" GENERATE
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      -- If g_out_dat_w>g_in_dat_w then IEEE resize sign extends with '0',
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      -- else IEEE resize keeps the low part.
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      wrap <= '1' WHEN UNSIGNED(reg_dat)>c_umax ELSE '0';
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      res_dat <= RESIZE_UVEC(reg_dat, g_out_dat_w);
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      res_ovr <= wrap;
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    END GENERATE;
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  END GENERATE;
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  gen_clip : IF c_clip=TRUE GENERATE
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    gen_s_clip : IF g_representation="SIGNED" GENERATE
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      clip <= '1' WHEN SIGNED(reg_dat)>c_smax OR SIGNED(reg_dat)< c_smin ELSE '0';
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      sign <= reg_dat(reg_dat'HIGH);
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      res_dat <= reg_dat(out_dat'RANGE) WHEN clip='0' ELSE STD_LOGIC_VECTOR( c_smax) WHEN sign='0' ELSE STD_LOGIC_VECTOR(c_smin);
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      res_ovr <= clip;
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    END GENERATE;
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    gen_u_clip : IF g_representation="UNSIGNED" GENERATE
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      clip <= '1' WHEN UNSIGNED(reg_dat)>c_umax ELSE '0';
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      res_dat <= reg_dat(out_dat'RANGE) WHEN clip='0' ELSE STD_LOGIC_VECTOR(c_umax);
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      res_ovr <= clip;
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    END GENERATE;
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  END GENERATE;
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  res_vec <= res_ovr & res_dat;
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  u_output_pipe : ENTITY common_components_lib.common_pipeline  -- pipeline output
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  GENERIC MAP (
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    g_representation => "SIGNED",
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    g_pipeline       => g_pipeline_output,
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    g_in_dat_w       => g_out_dat_w+1,
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    g_out_dat_w      => g_out_dat_w+1
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  )
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  PORT MAP (
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    clk     => clk,
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    clken   => clken,
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    in_dat  => res_vec,
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    out_dat => out_vec
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  );
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  out_ovr <= out_vec(g_out_dat_w);
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  out_dat <= out_vec(g_out_dat_w-1 DOWNTO 0);
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END rtl;

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