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-------------------------------------------------------------------------------
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--
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-- Copyright 2020
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-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
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-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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LIBRARY ieee, common_pkg_lib, common_components_lib;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE common_pkg_lib.common_pkg.ALL;
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ENTITY common_round IS
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--
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-- ISE XST results for rounding 36b --> 18b:
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-- int clip --> slices FFs LUTs
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-- 1) signed TRUE 63 54 80 -- increases with input widths > 18b
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-- 2) signed FALSE 59 54 73 -- increases with input widths > 18b
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-- 3) unsigned TRUE 34 37 43 -- same for all input widths > 18b
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-- 4) unsigned FALSE 21 37 19 -- same for all input widths > 18b
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--
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-- If the input comes from a product and is rounded to the input width then g_round_clip can safely be FALSE, because e.g. for unsigned
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-- 4b*4b=8b->4b the maximum product is 15*15=225 <= 255-8, so wrapping will never occur.
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--
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GENERIC (
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g_representation : STRING := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
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g_round : BOOLEAN := TRUE; -- when TRUE round the input, else truncate the input
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g_round_clip : BOOLEAN := FALSE; -- when TRUE clip rounded input >= +max to avoid wrapping to output -min (signed) or 0 (unsigned)
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g_pipeline_input : NATURAL := 0; -- >= 0
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g_pipeline_output : NATURAL := 1; -- >= 0, use g_pipeline_input=0 and g_pipeline_output=0 for combinatorial output
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g_in_dat_w : NATURAL := 36;
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g_out_dat_w : NATURAL := 18
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);
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PORT (
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clk : IN STD_LOGIC;
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clken : IN STD_LOGIC := '1';
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in_dat : IN STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
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out_dat : OUT STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0)
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);
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END;
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ARCHITECTURE rtl OF common_round IS
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CONSTANT c_remove_w : INTEGER := g_in_dat_w-g_out_dat_w;
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SIGNAL reg_dat : STD_LOGIC_VECTOR(in_dat'RANGE);
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SIGNAL res_dat : STD_LOGIC_VECTOR(out_dat'RANGE);
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BEGIN
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u_input_pipe : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => g_representation,
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g_pipeline => g_pipeline_input,
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g_in_dat_w => g_in_dat_w,
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g_out_dat_w => g_in_dat_w
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)
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PORT MAP (
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clk => clk,
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clken => clken,
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in_dat => in_dat,
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out_dat => reg_dat
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);
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-- Increase to out_dat width
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no_s : IF c_remove_w<=0 AND g_representation="SIGNED" GENERATE
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res_dat <= RESIZE_SVEC(reg_dat, g_out_dat_w);
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END GENERATE;
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no_u : IF c_remove_w<=0 AND g_representation="UNSIGNED" GENERATE
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res_dat <= RESIZE_UVEC(reg_dat, g_out_dat_w);
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END GENERATE;
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-- Decrease to out_dat width by c_remove_w number of LSbits
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-- . rounding
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gen_s : IF c_remove_w>0 AND g_round=TRUE AND g_representation="SIGNED" GENERATE
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res_dat <= s_round(reg_dat, c_remove_w, g_round_clip);
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END GENERATE;
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gen_u : IF c_remove_w>0 AND g_round=TRUE AND g_representation="UNSIGNED" GENERATE
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res_dat <= u_round(reg_dat, c_remove_w, g_round_clip);
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END GENERATE;
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-- . truncating
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gen_t : IF c_remove_w>0 AND g_round=FALSE GENERATE
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res_dat <= truncate(reg_dat, c_remove_w);
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END GENERATE;
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u_output_pipe : ENTITY common_components_lib.common_pipeline
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GENERIC MAP (
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g_representation => g_representation,
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g_pipeline => g_pipeline_output,
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g_in_dat_w => g_out_dat_w,
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g_out_dat_w => g_out_dat_w
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)
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PORT MAP (
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clk => clk,
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clken => clken,
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in_dat => res_dat,
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out_dat => out_dat
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);
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END rtl;
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